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Simon Glass246c1192011-06-13 16:13:09 -07001/*
2 * Copyright (c) 2011 The Chromium OS Authors.
3 * Copyright (C) 2009 NVIDIA, Corporation
Simon Glass00be89c2014-09-08 13:44:14 -06004 * Copyright (C) 2007-2008 SMSC (Steve Glendinning)
Simon Glass246c1192011-06-13 16:13:09 -07005 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Simon Glass246c1192011-06-13 16:13:09 -07007 */
8
9#include <common.h>
Simon Glassce48e502015-07-07 20:53:38 -060010#include <errno.h>
11#include <malloc.h>
Simon Glass246c1192011-06-13 16:13:09 -070012#include <usb.h>
Simon Glassce48e502015-07-07 20:53:38 -060013#include <asm/unaligned.h>
Simon Glass246c1192011-06-13 16:13:09 -070014#include <linux/mii.h>
15#include "usb_ether.h"
16
17/* SMSC LAN95xx based USB 2.0 Ethernet Devices */
18
Suriyan Ramasamie0f2f8c2013-10-07 20:30:58 -070019/* LED defines */
20#define LED_GPIO_CFG (0x24)
21#define LED_GPIO_CFG_SPD_LED (0x01000000)
22#define LED_GPIO_CFG_LNK_LED (0x00100000)
23#define LED_GPIO_CFG_FDX_LED (0x00010000)
24
Simon Glass246c1192011-06-13 16:13:09 -070025/* Tx command words */
26#define TX_CMD_A_FIRST_SEG_ 0x00002000
27#define TX_CMD_A_LAST_SEG_ 0x00001000
28
29/* Rx status word */
30#define RX_STS_FL_ 0x3FFF0000 /* Frame Length */
31#define RX_STS_ES_ 0x00008000 /* Error Summary */
32
33/* SCSRs */
34#define ID_REV 0x00
35
36#define INT_STS 0x08
37
38#define TX_CFG 0x10
39#define TX_CFG_ON_ 0x00000004
40
41#define HW_CFG 0x14
42#define HW_CFG_BIR_ 0x00001000
43#define HW_CFG_RXDOFF_ 0x00000600
44#define HW_CFG_MEF_ 0x00000020
45#define HW_CFG_BCE_ 0x00000002
46#define HW_CFG_LRST_ 0x00000008
47
48#define PM_CTRL 0x20
49#define PM_CTL_PHY_RST_ 0x00000010
50
51#define AFC_CFG 0x2C
52
53/*
54 * Hi watermark = 15.5Kb (~10 mtu pkts)
55 * low watermark = 3k (~2 mtu pkts)
56 * backpressure duration = ~ 350us
57 * Apply FC on any frame.
58 */
59#define AFC_CFG_DEFAULT 0x00F830A1
60
61#define E2P_CMD 0x30
62#define E2P_CMD_BUSY_ 0x80000000
63#define E2P_CMD_READ_ 0x00000000
64#define E2P_CMD_TIMEOUT_ 0x00000400
65#define E2P_CMD_LOADED_ 0x00000200
66#define E2P_CMD_ADDR_ 0x000001FF
67
68#define E2P_DATA 0x34
69
70#define BURST_CAP 0x38
71
72#define INT_EP_CTL 0x68
73#define INT_EP_CTL_PHY_INT_ 0x00008000
74
75#define BULK_IN_DLY 0x6C
76
77/* MAC CSRs */
78#define MAC_CR 0x100
79#define MAC_CR_MCPAS_ 0x00080000
80#define MAC_CR_PRMS_ 0x00040000
81#define MAC_CR_HPFILT_ 0x00002000
82#define MAC_CR_TXEN_ 0x00000008
83#define MAC_CR_RXEN_ 0x00000004
84
85#define ADDRH 0x104
86
87#define ADDRL 0x108
88
89#define MII_ADDR 0x114
90#define MII_WRITE_ 0x02
91#define MII_BUSY_ 0x01
92#define MII_READ_ 0x00 /* ~of MII Write bit */
93
94#define MII_DATA 0x118
95
96#define FLOW 0x11C
97
98#define VLAN1 0x120
99
100#define COE_CR 0x130
101#define Tx_COE_EN_ 0x00010000
102#define Rx_COE_EN_ 0x00000001
103
104/* Vendor-specific PHY Definitions */
105#define PHY_INT_SRC 29
106
107#define PHY_INT_MASK 30
108#define PHY_INT_MASK_ANEG_COMP_ ((u16)0x0040)
109#define PHY_INT_MASK_LINK_DOWN_ ((u16)0x0010)
110#define PHY_INT_MASK_DEFAULT_ (PHY_INT_MASK_ANEG_COMP_ | \
111 PHY_INT_MASK_LINK_DOWN_)
112
113/* USB Vendor Requests */
114#define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0
115#define USB_VENDOR_REQUEST_READ_REGISTER 0xA1
116
117/* Some extra defines */
118#define HS_USB_PKT_SIZE 512
119#define FS_USB_PKT_SIZE 64
120#define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE)
121#define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE)
122#define DEFAULT_BULK_IN_DELAY 0x00002000
123#define MAX_SINGLE_PACKET_SIZE 2048
124#define EEPROM_MAC_OFFSET 0x01
125#define SMSC95XX_INTERNAL_PHY_ID 1
126#define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */
127
128/* local defines */
129#define SMSC95XX_BASE_NAME "sms"
130#define USB_CTRL_SET_TIMEOUT 5000
131#define USB_CTRL_GET_TIMEOUT 5000
132#define USB_BULK_SEND_TIMEOUT 5000
133#define USB_BULK_RECV_TIMEOUT 5000
134
Simon Glass4d89e5b2015-07-07 20:53:39 -0600135#define RX_URB_SIZE 2048
Simon Glass246c1192011-06-13 16:13:09 -0700136#define PHY_CONNECT_TIMEOUT 5000
137
138#define TURBO_MODE
139
140/* local vars */
141static int curr_eth_dev; /* index for name of next device detected */
142
Lucas Stach36267c42012-08-22 11:04:57 +0000143/* driver private */
144struct smsc95xx_private {
145 size_t rx_urb_size; /* maximum USB URB size */
146 u32 mac_cr; /* MAC control register value */
147 int have_hwaddr; /* 1 if we have a hardware MAC address */
148};
Simon Glass246c1192011-06-13 16:13:09 -0700149
150/*
151 * Smsc95xx infrastructure commands
152 */
Simon Glass3faecae2015-07-07 20:53:41 -0600153static int smsc95xx_write_reg(struct usb_device *udev, u32 index, u32 data)
Simon Glass246c1192011-06-13 16:13:09 -0700154{
155 int len;
Ilya Yanok43b56c22012-07-15 04:43:53 +0000156 ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1);
Simon Glass246c1192011-06-13 16:13:09 -0700157
158 cpu_to_le32s(&data);
Ilya Yanok43b56c22012-07-15 04:43:53 +0000159 tmpbuf[0] = data;
Simon Glass246c1192011-06-13 16:13:09 -0700160
Simon Glass3faecae2015-07-07 20:53:41 -0600161 len = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
162 USB_VENDOR_REQUEST_WRITE_REGISTER,
163 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
164 0, index, tmpbuf, sizeof(data),
165 USB_CTRL_SET_TIMEOUT);
Simon Glass246c1192011-06-13 16:13:09 -0700166 if (len != sizeof(data)) {
167 debug("smsc95xx_write_reg failed: index=%d, data=%d, len=%d",
168 index, data, len);
Simon Glassebe0e5a2015-07-07 20:53:40 -0600169 return -EIO;
Simon Glass246c1192011-06-13 16:13:09 -0700170 }
171 return 0;
172}
173
Simon Glass3faecae2015-07-07 20:53:41 -0600174static int smsc95xx_read_reg(struct usb_device *udev, u32 index, u32 *data)
Simon Glass246c1192011-06-13 16:13:09 -0700175{
176 int len;
Ilya Yanok43b56c22012-07-15 04:43:53 +0000177 ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1);
Simon Glass246c1192011-06-13 16:13:09 -0700178
Simon Glass3faecae2015-07-07 20:53:41 -0600179 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
180 USB_VENDOR_REQUEST_READ_REGISTER,
181 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
182 0, index, tmpbuf, sizeof(data),
183 USB_CTRL_GET_TIMEOUT);
Ilya Yanok43b56c22012-07-15 04:43:53 +0000184 *data = tmpbuf[0];
Simon Glass246c1192011-06-13 16:13:09 -0700185 if (len != sizeof(data)) {
186 debug("smsc95xx_read_reg failed: index=%d, len=%d",
187 index, len);
Simon Glassebe0e5a2015-07-07 20:53:40 -0600188 return -EIO;
Simon Glass246c1192011-06-13 16:13:09 -0700189 }
190
191 le32_to_cpus(data);
192 return 0;
193}
194
195/* Loop until the read is completed with timeout */
Simon Glass3faecae2015-07-07 20:53:41 -0600196static int smsc95xx_phy_wait_not_busy(struct usb_device *udev)
Simon Glass246c1192011-06-13 16:13:09 -0700197{
198 unsigned long start_time = get_timer(0);
199 u32 val;
200
201 do {
Simon Glass3faecae2015-07-07 20:53:41 -0600202 smsc95xx_read_reg(udev, MII_ADDR, &val);
Simon Glass246c1192011-06-13 16:13:09 -0700203 if (!(val & MII_BUSY_))
204 return 0;
Simon Glass3faecae2015-07-07 20:53:41 -0600205 } while (get_timer(start_time) < 1000);
Simon Glass246c1192011-06-13 16:13:09 -0700206
Simon Glassebe0e5a2015-07-07 20:53:40 -0600207 return -ETIMEDOUT;
Simon Glass246c1192011-06-13 16:13:09 -0700208}
209
Simon Glass3faecae2015-07-07 20:53:41 -0600210static int smsc95xx_mdio_read(struct usb_device *udev, int phy_id, int idx)
Simon Glass246c1192011-06-13 16:13:09 -0700211{
212 u32 val, addr;
213
214 /* confirm MII not busy */
Simon Glass3faecae2015-07-07 20:53:41 -0600215 if (smsc95xx_phy_wait_not_busy(udev)) {
Simon Glass246c1192011-06-13 16:13:09 -0700216 debug("MII is busy in smsc95xx_mdio_read\n");
Simon Glassebe0e5a2015-07-07 20:53:40 -0600217 return -ETIMEDOUT;
Simon Glass246c1192011-06-13 16:13:09 -0700218 }
219
220 /* set the address, index & direction (read from PHY) */
221 addr = (phy_id << 11) | (idx << 6) | MII_READ_;
Simon Glass3faecae2015-07-07 20:53:41 -0600222 smsc95xx_write_reg(udev, MII_ADDR, addr);
Simon Glass246c1192011-06-13 16:13:09 -0700223
Simon Glass3faecae2015-07-07 20:53:41 -0600224 if (smsc95xx_phy_wait_not_busy(udev)) {
Simon Glass246c1192011-06-13 16:13:09 -0700225 debug("Timed out reading MII reg %02X\n", idx);
Simon Glassebe0e5a2015-07-07 20:53:40 -0600226 return -ETIMEDOUT;
Simon Glass246c1192011-06-13 16:13:09 -0700227 }
228
Simon Glass3faecae2015-07-07 20:53:41 -0600229 smsc95xx_read_reg(udev, MII_DATA, &val);
Simon Glass246c1192011-06-13 16:13:09 -0700230
231 return (u16)(val & 0xFFFF);
232}
233
Simon Glass3faecae2015-07-07 20:53:41 -0600234static void smsc95xx_mdio_write(struct usb_device *udev, int phy_id, int idx,
Simon Glass246c1192011-06-13 16:13:09 -0700235 int regval)
236{
237 u32 val, addr;
238
239 /* confirm MII not busy */
Simon Glass3faecae2015-07-07 20:53:41 -0600240 if (smsc95xx_phy_wait_not_busy(udev)) {
Simon Glass246c1192011-06-13 16:13:09 -0700241 debug("MII is busy in smsc95xx_mdio_write\n");
242 return;
243 }
244
245 val = regval;
Simon Glass3faecae2015-07-07 20:53:41 -0600246 smsc95xx_write_reg(udev, MII_DATA, val);
Simon Glass246c1192011-06-13 16:13:09 -0700247
248 /* set the address, index & direction (write to PHY) */
249 addr = (phy_id << 11) | (idx << 6) | MII_WRITE_;
Simon Glass3faecae2015-07-07 20:53:41 -0600250 smsc95xx_write_reg(udev, MII_ADDR, addr);
Simon Glass246c1192011-06-13 16:13:09 -0700251
Simon Glass3faecae2015-07-07 20:53:41 -0600252 if (smsc95xx_phy_wait_not_busy(udev))
Simon Glass246c1192011-06-13 16:13:09 -0700253 debug("Timed out writing MII reg %02X\n", idx);
254}
255
Simon Glass3faecae2015-07-07 20:53:41 -0600256static int smsc95xx_eeprom_confirm_not_busy(struct usb_device *udev)
Simon Glass246c1192011-06-13 16:13:09 -0700257{
258 unsigned long start_time = get_timer(0);
259 u32 val;
260
261 do {
Simon Glass3faecae2015-07-07 20:53:41 -0600262 smsc95xx_read_reg(udev, E2P_CMD, &val);
Simon Glass246c1192011-06-13 16:13:09 -0700263 if (!(val & E2P_CMD_BUSY_))
264 return 0;
265 udelay(40);
266 } while (get_timer(start_time) < 1 * 1000 * 1000);
267
268 debug("EEPROM is busy\n");
Simon Glassebe0e5a2015-07-07 20:53:40 -0600269 return -ETIMEDOUT;
Simon Glass246c1192011-06-13 16:13:09 -0700270}
271
Simon Glass3faecae2015-07-07 20:53:41 -0600272static int smsc95xx_wait_eeprom(struct usb_device *udev)
Simon Glass246c1192011-06-13 16:13:09 -0700273{
274 unsigned long start_time = get_timer(0);
275 u32 val;
276
277 do {
Simon Glass3faecae2015-07-07 20:53:41 -0600278 smsc95xx_read_reg(udev, E2P_CMD, &val);
Simon Glass246c1192011-06-13 16:13:09 -0700279 if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_))
280 break;
281 udelay(40);
282 } while (get_timer(start_time) < 1 * 1000 * 1000);
283
284 if (val & (E2P_CMD_TIMEOUT_ | E2P_CMD_BUSY_)) {
285 debug("EEPROM read operation timeout\n");
Simon Glassebe0e5a2015-07-07 20:53:40 -0600286 return -ETIMEDOUT;
Simon Glass246c1192011-06-13 16:13:09 -0700287 }
288 return 0;
289}
290
Simon Glass3faecae2015-07-07 20:53:41 -0600291static int smsc95xx_read_eeprom(struct usb_device *udev, u32 offset, u32 length,
Simon Glass246c1192011-06-13 16:13:09 -0700292 u8 *data)
293{
294 u32 val;
295 int i, ret;
296
Simon Glass3faecae2015-07-07 20:53:41 -0600297 ret = smsc95xx_eeprom_confirm_not_busy(udev);
Simon Glass246c1192011-06-13 16:13:09 -0700298 if (ret)
299 return ret;
300
301 for (i = 0; i < length; i++) {
302 val = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_);
Simon Glass3faecae2015-07-07 20:53:41 -0600303 smsc95xx_write_reg(udev, E2P_CMD, val);
Simon Glass246c1192011-06-13 16:13:09 -0700304
Simon Glass3faecae2015-07-07 20:53:41 -0600305 ret = smsc95xx_wait_eeprom(udev);
Simon Glass246c1192011-06-13 16:13:09 -0700306 if (ret < 0)
307 return ret;
308
Simon Glass3faecae2015-07-07 20:53:41 -0600309 smsc95xx_read_reg(udev, E2P_DATA, &val);
Simon Glass246c1192011-06-13 16:13:09 -0700310 data[i] = val & 0xFF;
311 offset++;
312 }
313 return 0;
314}
315
316/*
317 * mii_nway_restart - restart NWay (autonegotiation) for this interface
318 *
319 * Returns 0 on success, negative on error.
320 */
Simon Glass3faecae2015-07-07 20:53:41 -0600321static int mii_nway_restart(struct usb_device *udev, struct ueth_data *dev)
Simon Glass246c1192011-06-13 16:13:09 -0700322{
323 int bmcr;
324 int r = -1;
325
326 /* if autoneg is off, it's an error */
Simon Glass3faecae2015-07-07 20:53:41 -0600327 bmcr = smsc95xx_mdio_read(udev, dev->phy_id, MII_BMCR);
Simon Glass246c1192011-06-13 16:13:09 -0700328
329 if (bmcr & BMCR_ANENABLE) {
330 bmcr |= BMCR_ANRESTART;
Simon Glass3faecae2015-07-07 20:53:41 -0600331 smsc95xx_mdio_write(udev, dev->phy_id, MII_BMCR, bmcr);
Simon Glass246c1192011-06-13 16:13:09 -0700332 r = 0;
333 }
334 return r;
335}
336
Simon Glass3faecae2015-07-07 20:53:41 -0600337static int smsc95xx_phy_initialize(struct usb_device *udev,
338 struct ueth_data *dev)
Simon Glass246c1192011-06-13 16:13:09 -0700339{
Simon Glass3faecae2015-07-07 20:53:41 -0600340 smsc95xx_mdio_write(udev, dev->phy_id, MII_BMCR, BMCR_RESET);
341 smsc95xx_mdio_write(udev, dev->phy_id, MII_ADVERTISE,
342 ADVERTISE_ALL | ADVERTISE_CSMA |
343 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
Simon Glass246c1192011-06-13 16:13:09 -0700344
345 /* read to clear */
Simon Glass3faecae2015-07-07 20:53:41 -0600346 smsc95xx_mdio_read(udev, dev->phy_id, PHY_INT_SRC);
Simon Glass246c1192011-06-13 16:13:09 -0700347
Simon Glass3faecae2015-07-07 20:53:41 -0600348 smsc95xx_mdio_write(udev, dev->phy_id, PHY_INT_MASK,
349 PHY_INT_MASK_DEFAULT_);
350 mii_nway_restart(udev, dev);
Simon Glass246c1192011-06-13 16:13:09 -0700351
352 debug("phy initialised succesfully\n");
353 return 0;
354}
355
Simon Glass3faecae2015-07-07 20:53:41 -0600356static int smsc95xx_init_mac_address(unsigned char *enetaddr,
357 struct usb_device *udev)
Simon Glass246c1192011-06-13 16:13:09 -0700358{
Simon Glass3faecae2015-07-07 20:53:41 -0600359 int ret;
360
Simon Glass246c1192011-06-13 16:13:09 -0700361 /* try reading mac address from EEPROM */
Simon Glass3faecae2015-07-07 20:53:41 -0600362 ret = smsc95xx_read_eeprom(udev, EEPROM_MAC_OFFSET, ETH_ALEN, enetaddr);
363 if (ret)
364 return ret;
365
366 if (is_valid_ethaddr(enetaddr)) {
367 /* eeprom values are valid so use them */
368 debug("MAC address read from EEPROM\n");
369 return 0;
Simon Glass246c1192011-06-13 16:13:09 -0700370 }
371
372 /*
373 * No eeprom, or eeprom values are invalid. Generating a random MAC
374 * address is not safe. Just return an error.
375 */
Simon Glassebe0e5a2015-07-07 20:53:40 -0600376 debug("Invalid MAC address read from EEPROM\n");
377
378 return -ENXIO;
Simon Glass246c1192011-06-13 16:13:09 -0700379}
380
Simon Glass3faecae2015-07-07 20:53:41 -0600381static int smsc95xx_write_hwaddr_common(struct usb_device *udev,
382 struct smsc95xx_private *priv,
383 unsigned char *enetaddr)
Simon Glass246c1192011-06-13 16:13:09 -0700384{
Simon Glass3faecae2015-07-07 20:53:41 -0600385 u32 addr_lo = __get_unaligned_le32(&enetaddr[0]);
386 u32 addr_hi = __get_unaligned_le16(&enetaddr[4]);
Simon Glass246c1192011-06-13 16:13:09 -0700387 int ret;
388
389 /* set hardware address */
390 debug("** %s()\n", __func__);
Simon Glass3faecae2015-07-07 20:53:41 -0600391 ret = smsc95xx_write_reg(udev, ADDRL, addr_lo);
Wolfgang Grandeggerf9af1f82011-11-14 23:19:15 +0000392 if (ret < 0)
Simon Glass246c1192011-06-13 16:13:09 -0700393 return ret;
Simon Glass246c1192011-06-13 16:13:09 -0700394
Simon Glass3faecae2015-07-07 20:53:41 -0600395 ret = smsc95xx_write_reg(udev, ADDRH, addr_hi);
Simon Glass246c1192011-06-13 16:13:09 -0700396 if (ret < 0)
397 return ret;
Wolfgang Grandeggerf9af1f82011-11-14 23:19:15 +0000398
Simon Glass3faecae2015-07-07 20:53:41 -0600399 debug("MAC %pM\n", enetaddr);
Lucas Stach36267c42012-08-22 11:04:57 +0000400 priv->have_hwaddr = 1;
Simon Glass3faecae2015-07-07 20:53:41 -0600401
Simon Glass246c1192011-06-13 16:13:09 -0700402 return 0;
403}
404
405/* Enable or disable Tx & Rx checksum offload engines */
Simon Glass3faecae2015-07-07 20:53:41 -0600406static int smsc95xx_set_csums(struct usb_device *udev, int use_tx_csum,
407 int use_rx_csum)
Simon Glass246c1192011-06-13 16:13:09 -0700408{
409 u32 read_buf;
Simon Glass3faecae2015-07-07 20:53:41 -0600410 int ret = smsc95xx_read_reg(udev, COE_CR, &read_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700411 if (ret < 0)
412 return ret;
413
414 if (use_tx_csum)
415 read_buf |= Tx_COE_EN_;
416 else
417 read_buf &= ~Tx_COE_EN_;
418
419 if (use_rx_csum)
420 read_buf |= Rx_COE_EN_;
421 else
422 read_buf &= ~Rx_COE_EN_;
423
Simon Glass3faecae2015-07-07 20:53:41 -0600424 ret = smsc95xx_write_reg(udev, COE_CR, read_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700425 if (ret < 0)
426 return ret;
427
428 debug("COE_CR = 0x%08x\n", read_buf);
429 return 0;
430}
431
Simon Glass3faecae2015-07-07 20:53:41 -0600432static void smsc95xx_set_multicast(struct smsc95xx_private *priv)
Simon Glass246c1192011-06-13 16:13:09 -0700433{
434 /* No multicast in u-boot */
Lucas Stach36267c42012-08-22 11:04:57 +0000435 priv->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
Simon Glass246c1192011-06-13 16:13:09 -0700436}
437
438/* starts the TX path */
Simon Glass3faecae2015-07-07 20:53:41 -0600439static void smsc95xx_start_tx_path(struct usb_device *udev,
440 struct smsc95xx_private *priv)
Simon Glass246c1192011-06-13 16:13:09 -0700441{
442 u32 reg_val;
443
444 /* Enable Tx at MAC */
Lucas Stach36267c42012-08-22 11:04:57 +0000445 priv->mac_cr |= MAC_CR_TXEN_;
Simon Glass246c1192011-06-13 16:13:09 -0700446
Simon Glass3faecae2015-07-07 20:53:41 -0600447 smsc95xx_write_reg(udev, MAC_CR, priv->mac_cr);
Simon Glass246c1192011-06-13 16:13:09 -0700448
449 /* Enable Tx at SCSRs */
450 reg_val = TX_CFG_ON_;
Simon Glass3faecae2015-07-07 20:53:41 -0600451 smsc95xx_write_reg(udev, TX_CFG, reg_val);
Simon Glass246c1192011-06-13 16:13:09 -0700452}
453
454/* Starts the Receive path */
Simon Glass3faecae2015-07-07 20:53:41 -0600455static void smsc95xx_start_rx_path(struct usb_device *udev,
456 struct smsc95xx_private *priv)
Simon Glass246c1192011-06-13 16:13:09 -0700457{
Lucas Stach36267c42012-08-22 11:04:57 +0000458 priv->mac_cr |= MAC_CR_RXEN_;
Simon Glass3faecae2015-07-07 20:53:41 -0600459 smsc95xx_write_reg(udev, MAC_CR, priv->mac_cr);
Simon Glass246c1192011-06-13 16:13:09 -0700460}
461
Simon Glass3faecae2015-07-07 20:53:41 -0600462static int smsc95xx_init_common(struct usb_device *udev, struct ueth_data *dev,
463 struct smsc95xx_private *priv,
464 unsigned char *enetaddr)
Simon Glass246c1192011-06-13 16:13:09 -0700465{
466 int ret;
467 u32 write_buf;
468 u32 read_buf;
469 u32 burst_cap;
470 int timeout;
Simon Glass246c1192011-06-13 16:13:09 -0700471#define TIMEOUT_RESOLUTION 50 /* ms */
472 int link_detected;
473
474 debug("** %s()\n", __func__);
475 dev->phy_id = SMSC95XX_INTERNAL_PHY_ID; /* fixed phy id */
476
477 write_buf = HW_CFG_LRST_;
Simon Glass3faecae2015-07-07 20:53:41 -0600478 ret = smsc95xx_write_reg(udev, HW_CFG, write_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700479 if (ret < 0)
480 return ret;
481
482 timeout = 0;
483 do {
Simon Glass3faecae2015-07-07 20:53:41 -0600484 ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700485 if (ret < 0)
486 return ret;
487 udelay(10 * 1000);
488 timeout++;
489 } while ((read_buf & HW_CFG_LRST_) && (timeout < 100));
490
491 if (timeout >= 100) {
492 debug("timeout waiting for completion of Lite Reset\n");
Simon Glassebe0e5a2015-07-07 20:53:40 -0600493 return -ETIMEDOUT;
Simon Glass246c1192011-06-13 16:13:09 -0700494 }
495
496 write_buf = PM_CTL_PHY_RST_;
Simon Glass3faecae2015-07-07 20:53:41 -0600497 ret = smsc95xx_write_reg(udev, PM_CTRL, write_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700498 if (ret < 0)
499 return ret;
500
501 timeout = 0;
502 do {
Simon Glass3faecae2015-07-07 20:53:41 -0600503 ret = smsc95xx_read_reg(udev, PM_CTRL, &read_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700504 if (ret < 0)
505 return ret;
506 udelay(10 * 1000);
507 timeout++;
508 } while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100));
509 if (timeout >= 100) {
510 debug("timeout waiting for PHY Reset\n");
Simon Glassebe0e5a2015-07-07 20:53:40 -0600511 return -ETIMEDOUT;
Simon Glass246c1192011-06-13 16:13:09 -0700512 }
Simon Glass3faecae2015-07-07 20:53:41 -0600513 if (!priv->have_hwaddr && smsc95xx_init_mac_address(enetaddr, udev) ==
514 0)
Lucas Stach36267c42012-08-22 11:04:57 +0000515 priv->have_hwaddr = 1;
516 if (!priv->have_hwaddr) {
Simon Glass246c1192011-06-13 16:13:09 -0700517 puts("Error: SMSC95xx: No MAC address set - set usbethaddr\n");
Simon Glassebe0e5a2015-07-07 20:53:40 -0600518 return -EADDRNOTAVAIL;
Simon Glass246c1192011-06-13 16:13:09 -0700519 }
Simon Glass3faecae2015-07-07 20:53:41 -0600520 ret = smsc95xx_write_hwaddr_common(udev, priv, enetaddr);
Simon Glassebe0e5a2015-07-07 20:53:40 -0600521 if (ret < 0)
522 return ret;
Simon Glass246c1192011-06-13 16:13:09 -0700523
Simon Glass3faecae2015-07-07 20:53:41 -0600524 ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700525 if (ret < 0)
526 return ret;
527 debug("Read Value from HW_CFG : 0x%08x\n", read_buf);
528
529 read_buf |= HW_CFG_BIR_;
Simon Glass3faecae2015-07-07 20:53:41 -0600530 ret = smsc95xx_write_reg(udev, HW_CFG, read_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700531 if (ret < 0)
532 return ret;
533
Simon Glass3faecae2015-07-07 20:53:41 -0600534 ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700535 if (ret < 0)
536 return ret;
537 debug("Read Value from HW_CFG after writing "
538 "HW_CFG_BIR_: 0x%08x\n", read_buf);
539
540#ifdef TURBO_MODE
541 if (dev->pusb_dev->speed == USB_SPEED_HIGH) {
542 burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
Lucas Stach36267c42012-08-22 11:04:57 +0000543 priv->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
Simon Glass246c1192011-06-13 16:13:09 -0700544 } else {
545 burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
Lucas Stach36267c42012-08-22 11:04:57 +0000546 priv->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
Simon Glass246c1192011-06-13 16:13:09 -0700547 }
548#else
549 burst_cap = 0;
Lucas Stach36267c42012-08-22 11:04:57 +0000550 priv->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
Simon Glass246c1192011-06-13 16:13:09 -0700551#endif
Lucas Stach36267c42012-08-22 11:04:57 +0000552 debug("rx_urb_size=%ld\n", (ulong)priv->rx_urb_size);
Simon Glass246c1192011-06-13 16:13:09 -0700553
Simon Glass3faecae2015-07-07 20:53:41 -0600554 ret = smsc95xx_write_reg(udev, BURST_CAP, burst_cap);
Simon Glass246c1192011-06-13 16:13:09 -0700555 if (ret < 0)
556 return ret;
557
Simon Glass3faecae2015-07-07 20:53:41 -0600558 ret = smsc95xx_read_reg(udev, BURST_CAP, &read_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700559 if (ret < 0)
560 return ret;
561 debug("Read Value from BURST_CAP after writing: 0x%08x\n", read_buf);
562
563 read_buf = DEFAULT_BULK_IN_DELAY;
Simon Glass3faecae2015-07-07 20:53:41 -0600564 ret = smsc95xx_write_reg(udev, BULK_IN_DLY, read_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700565 if (ret < 0)
566 return ret;
567
Simon Glass3faecae2015-07-07 20:53:41 -0600568 ret = smsc95xx_read_reg(udev, BULK_IN_DLY, &read_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700569 if (ret < 0)
570 return ret;
571 debug("Read Value from BULK_IN_DLY after writing: "
572 "0x%08x\n", read_buf);
573
Simon Glass3faecae2015-07-07 20:53:41 -0600574 ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700575 if (ret < 0)
576 return ret;
577 debug("Read Value from HW_CFG: 0x%08x\n", read_buf);
578
579#ifdef TURBO_MODE
580 read_buf |= (HW_CFG_MEF_ | HW_CFG_BCE_);
581#endif
582 read_buf &= ~HW_CFG_RXDOFF_;
583
584#define NET_IP_ALIGN 0
585 read_buf |= NET_IP_ALIGN << 9;
586
Simon Glass3faecae2015-07-07 20:53:41 -0600587 ret = smsc95xx_write_reg(udev, HW_CFG, read_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700588 if (ret < 0)
589 return ret;
590
Simon Glass3faecae2015-07-07 20:53:41 -0600591 ret = smsc95xx_read_reg(udev, HW_CFG, &read_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700592 if (ret < 0)
593 return ret;
594 debug("Read Value from HW_CFG after writing: 0x%08x\n", read_buf);
595
596 write_buf = 0xFFFFFFFF;
Simon Glass3faecae2015-07-07 20:53:41 -0600597 ret = smsc95xx_write_reg(udev, INT_STS, write_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700598 if (ret < 0)
599 return ret;
600
Simon Glass3faecae2015-07-07 20:53:41 -0600601 ret = smsc95xx_read_reg(udev, ID_REV, &read_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700602 if (ret < 0)
603 return ret;
604 debug("ID_REV = 0x%08x\n", read_buf);
605
Suriyan Ramasamie0f2f8c2013-10-07 20:30:58 -0700606 /* Configure GPIO pins as LED outputs */
607 write_buf = LED_GPIO_CFG_SPD_LED | LED_GPIO_CFG_LNK_LED |
608 LED_GPIO_CFG_FDX_LED;
Simon Glass3faecae2015-07-07 20:53:41 -0600609 ret = smsc95xx_write_reg(udev, LED_GPIO_CFG, write_buf);
Suriyan Ramasamie0f2f8c2013-10-07 20:30:58 -0700610 if (ret < 0)
611 return ret;
612 debug("LED_GPIO_CFG set\n");
613
Simon Glass246c1192011-06-13 16:13:09 -0700614 /* Init Tx */
615 write_buf = 0;
Simon Glass3faecae2015-07-07 20:53:41 -0600616 ret = smsc95xx_write_reg(udev, FLOW, write_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700617 if (ret < 0)
618 return ret;
619
620 read_buf = AFC_CFG_DEFAULT;
Simon Glass3faecae2015-07-07 20:53:41 -0600621 ret = smsc95xx_write_reg(udev, AFC_CFG, read_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700622 if (ret < 0)
623 return ret;
624
Simon Glass3faecae2015-07-07 20:53:41 -0600625 ret = smsc95xx_read_reg(udev, MAC_CR, &priv->mac_cr);
Simon Glass246c1192011-06-13 16:13:09 -0700626 if (ret < 0)
627 return ret;
628
629 /* Init Rx. Set Vlan */
630 write_buf = (u32)ETH_P_8021Q;
Simon Glass3faecae2015-07-07 20:53:41 -0600631 ret = smsc95xx_write_reg(udev, VLAN1, write_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700632 if (ret < 0)
633 return ret;
634
635 /* Disable checksum offload engines */
Simon Glass3faecae2015-07-07 20:53:41 -0600636 ret = smsc95xx_set_csums(udev, 0, 0);
Simon Glass246c1192011-06-13 16:13:09 -0700637 if (ret < 0) {
638 debug("Failed to set csum offload: %d\n", ret);
639 return ret;
640 }
Simon Glass3faecae2015-07-07 20:53:41 -0600641 smsc95xx_set_multicast(priv);
Simon Glass246c1192011-06-13 16:13:09 -0700642
Simon Glass3faecae2015-07-07 20:53:41 -0600643 ret = smsc95xx_phy_initialize(udev, dev);
Simon Glassebe0e5a2015-07-07 20:53:40 -0600644 if (ret < 0)
645 return ret;
Simon Glass3faecae2015-07-07 20:53:41 -0600646 ret = smsc95xx_read_reg(udev, INT_EP_CTL, &read_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700647 if (ret < 0)
648 return ret;
649
650 /* enable PHY interrupts */
651 read_buf |= INT_EP_CTL_PHY_INT_;
652
Simon Glass3faecae2015-07-07 20:53:41 -0600653 ret = smsc95xx_write_reg(udev, INT_EP_CTL, read_buf);
Simon Glass246c1192011-06-13 16:13:09 -0700654 if (ret < 0)
655 return ret;
656
Simon Glass3faecae2015-07-07 20:53:41 -0600657 smsc95xx_start_tx_path(udev, priv);
658 smsc95xx_start_rx_path(udev, priv);
Simon Glass246c1192011-06-13 16:13:09 -0700659
660 timeout = 0;
661 do {
Simon Glass3faecae2015-07-07 20:53:41 -0600662 link_detected = smsc95xx_mdio_read(udev, dev->phy_id, MII_BMSR)
Simon Glass246c1192011-06-13 16:13:09 -0700663 & BMSR_LSTATUS;
664 if (!link_detected) {
665 if (timeout == 0)
666 printf("Waiting for Ethernet connection... ");
667 udelay(TIMEOUT_RESOLUTION * 1000);
668 timeout += TIMEOUT_RESOLUTION;
669 }
670 } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT);
671 if (link_detected) {
672 if (timeout != 0)
673 printf("done.\n");
674 } else {
675 printf("unable to connect.\n");
Simon Glassebe0e5a2015-07-07 20:53:40 -0600676 return -EIO;
Simon Glass246c1192011-06-13 16:13:09 -0700677 }
678 return 0;
679}
680
Simon Glass3faecae2015-07-07 20:53:41 -0600681static int smsc95xx_send_common(struct ueth_data *dev, void *packet, int length)
Simon Glass246c1192011-06-13 16:13:09 -0700682{
Simon Glass246c1192011-06-13 16:13:09 -0700683 int err;
684 int actual_len;
685 u32 tx_cmd_a;
686 u32 tx_cmd_b;
Ilya Yanok43b56c22012-07-15 04:43:53 +0000687 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg,
688 PKTSIZE + sizeof(tx_cmd_a) + sizeof(tx_cmd_b));
Simon Glass246c1192011-06-13 16:13:09 -0700689
690 debug("** %s(), len %d, buf %#x\n", __func__, length, (int)msg);
691 if (length > PKTSIZE)
Simon Glassebe0e5a2015-07-07 20:53:40 -0600692 return -ENOSPC;
Simon Glass246c1192011-06-13 16:13:09 -0700693
694 tx_cmd_a = (u32)length | TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
695 tx_cmd_b = (u32)length;
696 cpu_to_le32s(&tx_cmd_a);
697 cpu_to_le32s(&tx_cmd_b);
698
699 /* prepend cmd_a and cmd_b */
700 memcpy(msg, &tx_cmd_a, sizeof(tx_cmd_a));
701 memcpy(msg + sizeof(tx_cmd_a), &tx_cmd_b, sizeof(tx_cmd_b));
702 memcpy(msg + sizeof(tx_cmd_a) + sizeof(tx_cmd_b), (void *)packet,
703 length);
704 err = usb_bulk_msg(dev->pusb_dev,
705 usb_sndbulkpipe(dev->pusb_dev, dev->ep_out),
706 (void *)msg,
707 length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b),
708 &actual_len,
709 USB_BULK_SEND_TIMEOUT);
710 debug("Tx: len = %u, actual = %u, err = %d\n",
711 length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b),
712 actual_len, err);
Simon Glass3faecae2015-07-07 20:53:41 -0600713
Simon Glass246c1192011-06-13 16:13:09 -0700714 return err;
715}
716
Simon Glass3faecae2015-07-07 20:53:41 -0600717/*
718 * Smsc95xx callbacks
719 */
720static int smsc95xx_init(struct eth_device *eth, bd_t *bd)
721{
722 struct ueth_data *dev = (struct ueth_data *)eth->priv;
723 struct usb_device *udev = dev->pusb_dev;
724 struct smsc95xx_private *priv =
725 (struct smsc95xx_private *)dev->dev_priv;
726
727 return smsc95xx_init_common(udev, dev, priv, eth->enetaddr);
728}
729
730static int smsc95xx_send(struct eth_device *eth, void *packet, int length)
731{
732 struct ueth_data *dev = (struct ueth_data *)eth->priv;
733
734 return smsc95xx_send_common(dev, packet, length);
735}
736
Simon Glass246c1192011-06-13 16:13:09 -0700737static int smsc95xx_recv(struct eth_device *eth)
738{
739 struct ueth_data *dev = (struct ueth_data *)eth->priv;
Simon Glass4d89e5b2015-07-07 20:53:39 -0600740 DEFINE_CACHE_ALIGN_BUFFER(unsigned char, recv_buf, RX_URB_SIZE);
Simon Glass246c1192011-06-13 16:13:09 -0700741 unsigned char *buf_ptr;
742 int err;
743 int actual_len;
744 u32 packet_len;
745 int cur_buf_align;
746
747 debug("** %s()\n", __func__);
748 err = usb_bulk_msg(dev->pusb_dev,
Simon Glass3faecae2015-07-07 20:53:41 -0600749 usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
750 (void *)recv_buf, RX_URB_SIZE, &actual_len,
751 USB_BULK_RECV_TIMEOUT);
Simon Glass4d89e5b2015-07-07 20:53:39 -0600752 debug("Rx: len = %u, actual = %u, err = %d\n", RX_URB_SIZE,
Simon Glass246c1192011-06-13 16:13:09 -0700753 actual_len, err);
754 if (err != 0) {
755 debug("Rx: failed to receive\n");
Simon Glass3faecae2015-07-07 20:53:41 -0600756 return -err;
Simon Glass246c1192011-06-13 16:13:09 -0700757 }
Simon Glass4d89e5b2015-07-07 20:53:39 -0600758 if (actual_len > RX_URB_SIZE) {
Simon Glass246c1192011-06-13 16:13:09 -0700759 debug("Rx: received too many bytes %d\n", actual_len);
Simon Glassebe0e5a2015-07-07 20:53:40 -0600760 return -ENOSPC;
Simon Glass246c1192011-06-13 16:13:09 -0700761 }
762
763 buf_ptr = recv_buf;
764 while (actual_len > 0) {
765 /*
766 * 1st 4 bytes contain the length of the actual data plus error
767 * info. Extract data length.
768 */
769 if (actual_len < sizeof(packet_len)) {
770 debug("Rx: incomplete packet length\n");
Simon Glassebe0e5a2015-07-07 20:53:40 -0600771 return -EIO;
Simon Glass246c1192011-06-13 16:13:09 -0700772 }
773 memcpy(&packet_len, buf_ptr, sizeof(packet_len));
774 le32_to_cpus(&packet_len);
775 if (packet_len & RX_STS_ES_) {
776 debug("Rx: Error header=%#x", packet_len);
Simon Glassebe0e5a2015-07-07 20:53:40 -0600777 return -EIO;
Simon Glass246c1192011-06-13 16:13:09 -0700778 }
779 packet_len = ((packet_len & RX_STS_FL_) >> 16);
780
781 if (packet_len > actual_len - sizeof(packet_len)) {
782 debug("Rx: too large packet: %d\n", packet_len);
Simon Glassebe0e5a2015-07-07 20:53:40 -0600783 return -EIO;
Simon Glass246c1192011-06-13 16:13:09 -0700784 }
785
786 /* Notify net stack */
Joe Hershberger9f09a362015-04-08 01:41:06 -0500787 net_process_received_packet(buf_ptr + sizeof(packet_len),
788 packet_len - 4);
Simon Glass246c1192011-06-13 16:13:09 -0700789
790 /* Adjust for next iteration */
791 actual_len -= sizeof(packet_len) + packet_len;
792 buf_ptr += sizeof(packet_len) + packet_len;
793 cur_buf_align = (int)buf_ptr - (int)recv_buf;
794
795 if (cur_buf_align & 0x03) {
796 int align = 4 - (cur_buf_align & 0x03);
797
798 actual_len -= align;
799 buf_ptr += align;
800 }
801 }
802 return err;
803}
804
805static void smsc95xx_halt(struct eth_device *eth)
806{
807 debug("** %s()\n", __func__);
808}
809
Simon Glass3faecae2015-07-07 20:53:41 -0600810static int smsc95xx_write_hwaddr(struct eth_device *eth)
811{
812 struct ueth_data *dev = eth->priv;
813 struct usb_device *udev = dev->pusb_dev;
814 struct smsc95xx_private *priv = dev->dev_priv;
815
816 return smsc95xx_write_hwaddr_common(udev, priv, eth->enetaddr);
817}
818
Simon Glass246c1192011-06-13 16:13:09 -0700819/*
820 * SMSC probing functions
821 */
822void smsc95xx_eth_before_probe(void)
823{
824 curr_eth_dev = 0;
825}
826
827struct smsc95xx_dongle {
828 unsigned short vendor;
829 unsigned short product;
830};
831
832static const struct smsc95xx_dongle smsc95xx_dongles[] = {
833 { 0x0424, 0xec00 }, /* LAN9512/LAN9514 Ethernet */
834 { 0x0424, 0x9500 }, /* LAN9500 Ethernet */
Lubomir Popov7ca25b62013-04-01 04:50:55 +0000835 { 0x0424, 0x9730 }, /* LAN9730 Ethernet (HSIC) */
Stefan Roese8aa7b042013-07-03 18:34:54 +0200836 { 0x0424, 0x9900 }, /* SMSC9500 USB Ethernet Device (SAL10) */
Ilya Ledvich180bb6a2014-03-12 10:36:31 +0200837 { 0x0424, 0x9e00 }, /* LAN9500A Ethernet */
Simon Glass246c1192011-06-13 16:13:09 -0700838 { 0x0000, 0x0000 } /* END - Do not remove */
839};
840
841/* Probe to see if a new device is actually an SMSC device */
842int smsc95xx_eth_probe(struct usb_device *dev, unsigned int ifnum,
843 struct ueth_data *ss)
844{
845 struct usb_interface *iface;
846 struct usb_interface_descriptor *iface_desc;
847 int i;
848
849 /* let's examine the device now */
850 iface = &dev->config.if_desc[ifnum];
851 iface_desc = &dev->config.if_desc[ifnum].desc;
852
853 for (i = 0; smsc95xx_dongles[i].vendor != 0; i++) {
854 if (dev->descriptor.idVendor == smsc95xx_dongles[i].vendor &&
855 dev->descriptor.idProduct == smsc95xx_dongles[i].product)
856 /* Found a supported dongle */
857 break;
858 }
859 if (smsc95xx_dongles[i].vendor == 0)
860 return 0;
861
862 /* At this point, we know we've got a live one */
863 debug("\n\nUSB Ethernet device detected\n");
864 memset(ss, '\0', sizeof(struct ueth_data));
865
866 /* Initialize the ueth_data structure with some useful info */
867 ss->ifnum = ifnum;
868 ss->pusb_dev = dev;
869 ss->subclass = iface_desc->bInterfaceSubClass;
870 ss->protocol = iface_desc->bInterfaceProtocol;
871
872 /*
873 * We are expecting a minimum of 3 endpoints - in, out (bulk), and int.
874 * We will ignore any others.
875 */
876 for (i = 0; i < iface_desc->bNumEndpoints; i++) {
877 /* is it an BULK endpoint? */
878 if ((iface->ep_desc[i].bmAttributes &
879 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) {
880 if (iface->ep_desc[i].bEndpointAddress & USB_DIR_IN)
881 ss->ep_in =
882 iface->ep_desc[i].bEndpointAddress &
883 USB_ENDPOINT_NUMBER_MASK;
884 else
885 ss->ep_out =
886 iface->ep_desc[i].bEndpointAddress &
887 USB_ENDPOINT_NUMBER_MASK;
888 }
889
890 /* is it an interrupt endpoint? */
891 if ((iface->ep_desc[i].bmAttributes &
892 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
893 ss->ep_int = iface->ep_desc[i].bEndpointAddress &
894 USB_ENDPOINT_NUMBER_MASK;
895 ss->irqinterval = iface->ep_desc[i].bInterval;
896 }
897 }
898 debug("Endpoints In %d Out %d Int %d\n",
899 ss->ep_in, ss->ep_out, ss->ep_int);
900
901 /* Do some basic sanity checks, and bail if we find a problem */
902 if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
903 !ss->ep_in || !ss->ep_out || !ss->ep_int) {
904 debug("Problems with device\n");
905 return 0;
906 }
907 dev->privptr = (void *)ss;
Lucas Stach36267c42012-08-22 11:04:57 +0000908
909 /* alloc driver private */
910 ss->dev_priv = calloc(1, sizeof(struct smsc95xx_private));
911 if (!ss->dev_priv)
912 return 0;
913
Simon Glass246c1192011-06-13 16:13:09 -0700914 return 1;
915}
916
917int smsc95xx_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
918 struct eth_device *eth)
919{
920 debug("** %s()\n", __func__);
921 if (!eth) {
922 debug("%s: missing parameter.\n", __func__);
923 return 0;
924 }
925 sprintf(eth->name, "%s%d", SMSC95XX_BASE_NAME, curr_eth_dev++);
926 eth->init = smsc95xx_init;
927 eth->send = smsc95xx_send;
928 eth->recv = smsc95xx_recv;
929 eth->halt = smsc95xx_halt;
930 eth->write_hwaddr = smsc95xx_write_hwaddr;
931 eth->priv = ss;
932 return 1;
933}