blob: b36447c4a79126b76a0c83f448687d25a40549a5 [file] [log] [blame]
Simon Glass4cc43bf2021-08-18 21:40:25 -06001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Devicetree file for running sandbox tests
4 *
5 * This includes lots of extra devices used by various tests.
6 *
7 * Note that SPL use the main sandbox.dts file
8 */
9
Simon Glassb2c1cac2014-02-26 15:59:21 -070010/dts-v1/;
11
Patrick Delaunay23aee612020-01-13 11:35:13 +010012#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/gpio/sandbox-gpio.h>
Marek Szyprowskiad398592021-02-18 11:33:18 +010014#include <dt-bindings/input/input.h>
Sean Anderson3438e3b2020-09-14 11:01:57 -040015#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +053016#include <dt-bindings/mux/mux.h>
Patrick Delaunay23aee612020-01-13 11:35:13 +010017
Simon Glassb2c1cac2014-02-26 15:59:21 -070018/ {
19 model = "sandbox";
20 compatible = "sandbox";
21 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -060022 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070023
Simon Glassfef72b72014-07-23 06:55:03 -060024 aliases {
25 console = &uart0;
Michael Walle7efcdfd2021-02-25 16:51:11 +010026 ethernet0 = "/eth@10002000";
27 ethernet2 = &swp_0;
28 ethernet3 = &eth_3;
29 ethernet4 = &dsa_eth0;
30 ethernet5 = &eth_5;
Simon Glass5620cf82018-10-01 12:22:40 -060031 gpio1 = &gpio_a;
32 gpio2 = &gpio_b;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +010033 gpio3 = &gpio_c;
Simon Glass0ccb0972015-01-25 08:27:05 -070034 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -060035 mmc0 = "/mmc0";
36 mmc1 = "/mmc1";
Bin Meng408e5902018-08-03 01:14:41 -070037 pci0 = &pci0;
38 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -070039 pci2 = &pci2;
Michael Walle7c41a222020-06-02 01:47:09 +020040 remoteproc0 = &rproc_1;
41 remoteproc1 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -060042 rtc0 = &rtc_0;
43 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -060044 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +020045 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -070046 testbus3 = "/some-bus";
47 testfdt0 = "/some-bus/c-test@0";
Simon Glass7d5e4112020-12-16 21:20:26 -070048 testfdt12 = "/some-bus/c-test@1";
Simon Glass0ccb0972015-01-25 08:27:05 -070049 testfdt3 = "/b-test";
50 testfdt5 = "/some-bus/c-test@5";
51 testfdt8 = "/a-test";
Simon Glass791a17f2020-12-16 21:20:27 -070052 testfdtm1 = &testfdtm1;
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +020053 fdt-dummy0 = "/translation-test@8000/dev@0,0";
54 fdt-dummy1 = "/translation-test@8000/dev@1,100";
55 fdt-dummy2 = "/translation-test@8000/dev@2,200";
56 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glass31680482015-03-25 12:23:05 -060057 usb0 = &usb_0;
58 usb1 = &usb_1;
59 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +020060 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +020061 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -060062 };
63
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020064 config {
65 environment {
66 from_fdt = "yes";
67 fdt_env_path = "";
68 };
69 };
70
Nandor Han6521e5d2021-06-10 16:56:44 +030071 reboot-mode0 {
72 compatible = "reboot-mode-gpio";
73 gpios = <&gpio_c 0 GPIO_ACTIVE_HIGH>, <&gpio_c 1 GPIO_ACTIVE_HIGH>;
74 u-boot,env-variable = "bootstatus";
75 mode-test = <0x01>;
76 mode-download = <0x03>;
77 };
78
Nandor Han7e4067a2021-06-10 16:56:45 +030079 reboot_mode1: reboot-mode@14 {
80 compatible = "reboot-mode-rtc";
81 rtc = <&rtc_0>;
82 reg = <0x30 4>;
83 u-boot,env-variable = "bootstatus";
84 big-endian;
85 mode-test = <0x21969147>;
86 mode-download = <0x51939147>;
87 };
88
Simon Glassed96cde2018-12-10 10:37:33 -070089 audio: audio-codec {
90 compatible = "sandbox,audio-codec";
91 #sound-dai-cells = <1>;
92 };
93
Philippe Reynes1ee26482020-07-24 18:19:51 +020094 buttons {
95 compatible = "gpio-keys";
96
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +020097 btn1 {
Philippe Reynes1ee26482020-07-24 18:19:51 +020098 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +020099 label = "button1";
Philippe Reynes1ee26482020-07-24 18:19:51 +0200100 };
101
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200102 btn2 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200103 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200104 label = "button2";
Philippe Reynes1ee26482020-07-24 18:19:51 +0200105 };
106 };
107
Marek Szyprowskiad398592021-02-18 11:33:18 +0100108 buttons2 {
109 compatible = "adc-keys";
110 io-channels = <&adc 3>;
111 keyup-threshold-microvolt = <3000000>;
112
113 button-up {
114 label = "button3";
115 linux,code = <KEY_F3>;
116 press-threshold-microvolt = <1500000>;
117 };
118
119 button-down {
120 label = "button4";
121 linux,code = <KEY_F4>;
122 press-threshold-microvolt = <1000000>;
123 };
124
125 button-enter {
126 label = "button5";
127 linux,code = <KEY_F5>;
128 press-threshold-microvolt = <500000>;
129 };
130 };
131
Simon Glassc953aaf2018-12-10 10:37:34 -0700132 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -0600133 reg = <0 0>;
134 compatible = "google,cros-ec-sandbox";
135
136 /*
137 * This describes the flash memory within the EC. Note
138 * that the STM32L flash erases to 0, not 0xff.
139 */
140 flash {
141 image-pos = <0x08000000>;
142 size = <0x20000>;
143 erase-value = <0>;
144
145 /* Information for sandbox */
146 ro {
147 image-pos = <0>;
148 size = <0xf000>;
149 };
150 wp-ro {
151 image-pos = <0xf000>;
152 size = <0x1000>;
Simon Glassbf0a6922021-01-21 13:57:14 -0700153 used = <0x884>;
154 compress = "lz4";
155 uncomp-size = <0xcf8>;
156 hash {
157 algo = "sha256";
158 value = [00 01 02 03 04 05 06 07
159 08 09 0a 0b 0c 0d 0e 0f
160 10 11 12 13 14 15 16 17
161 18 19 1a 1b 1c 1d 1e 1f];
162 };
Simon Glass699c9ca2018-10-01 12:22:08 -0600163 };
164 rw {
165 image-pos = <0x10000>;
166 size = <0x10000>;
167 };
168 };
Alper Nebi Yasak8a8cd4f2021-05-19 19:33:31 +0300169
170 cros_ec_pwm: cros-ec-pwm {
171 compatible = "google,cros-ec-pwm";
172 #pwm-cells = <1>;
173 };
174
Simon Glass699c9ca2018-10-01 12:22:08 -0600175 };
176
Yannick Fertré9712c822019-10-07 15:29:05 +0200177 dsi_host: dsi_host {
178 compatible = "sandbox,dsi-host";
179 };
180
Simon Glassb2c1cac2014-02-26 15:59:21 -0700181 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600182 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700183 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600184 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700185 ping-add = <0>;
Simon Glassfef72b72014-07-23 06:55:03 -0600186 u-boot,dm-pre-reloc;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100187 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
188 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass16e10402015-01-05 20:05:29 -0700189 <0>, <&gpio_a 12>;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100190 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
191 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
192 <&gpio_b 7 GPIO_IN 3 2 1>,
193 <&gpio_b 8 GPIO_OUT 3 2 1>,
194 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100195 test3-gpios =
196 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
197 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
198 <&gpio_c 2 GPIO_OUT>,
199 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
200 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong643778b2020-05-05 10:43:18 +0200201 <&gpio_c 5 GPIO_IN>,
202 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
203 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530204 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
205 test5-gpios = <&gpio_a 19>;
206
Simon Glass6df01f92018-12-10 10:37:37 -0700207 int-value = <1234>;
208 uint-value = <(-1234)>;
Dario Binacchi421e81e2020-03-29 18:04:40 +0200209 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi81d80b52020-03-29 18:04:41 +0200210 int-array = <5678 9123 4567>;
Simon Glassdd0ed902020-07-07 13:11:58 -0600211 str-value = "test string";
Simon Glass515dcff2020-02-06 09:55:00 -0700212 interrupts-extended = <&irq 3 0>;
Simon Glass09642392020-07-07 13:12:11 -0600213 acpi,name = "GHIJ";
Patrick Delaunay8cd28012020-09-25 09:41:16 +0200214 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530215
216 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
217 <&muxcontroller0 2>, <&muxcontroller0 3>,
218 <&muxcontroller1>;
219 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
220 mux-syscon = <&syscon3>;
Dario Binacchi836cc9d2020-12-30 00:16:26 +0100221 display-timings {
222 timing0: 240x320 {
223 clock-frequency = <6500000>;
224 hactive = <240>;
225 vactive = <320>;
226 hfront-porch = <6>;
227 hback-porch = <7>;
228 hsync-len = <1>;
229 vback-porch = <5>;
230 vfront-porch = <8>;
231 vsync-len = <2>;
232 hsync-active = <1>;
233 vsync-active = <0>;
234 de-active = <1>;
235 pixelclk-active = <1>;
236 interlaced;
237 doublescan;
238 doubleclk;
239 };
240 timing1: 480x800 {
241 clock-frequency = <9000000>;
242 hactive = <480>;
243 vactive = <800>;
244 hfront-porch = <10>;
245 hback-porch = <59>;
246 hsync-len = <12>;
247 vback-porch = <15>;
248 vfront-porch = <17>;
249 vsync-len = <16>;
250 hsync-active = <0>;
251 vsync-active = <1>;
252 de-active = <0>;
253 pixelclk-active = <0>;
254 };
255 timing2: 800x480 {
256 clock-frequency = <33500000>;
257 hactive = <800>;
258 vactive = <480>;
259 hback-porch = <89>;
260 hfront-porch = <164>;
261 vback-porch = <23>;
262 vfront-porch = <10>;
263 hsync-len = <11>;
264 vsync-len = <13>;
265 };
266 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700267 };
268
269 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600270 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700271 compatible = "not,compatible";
272 };
273
274 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600275 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700276 };
277
Simon Glass5620cf82018-10-01 12:22:40 -0600278 backlight: backlight {
279 compatible = "pwm-backlight";
280 enable-gpios = <&gpio_a 1>;
281 power-supply = <&ldo_1>;
282 pwms = <&pwm 0 1000>;
283 default-brightness-level = <5>;
284 brightness-levels = <0 16 32 64 128 170 202 234 255>;
285 };
286
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200287 bind-test {
Patrice Chotard7b7f9392020-07-28 09:13:33 +0200288 compatible = "simple-bus";
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200289 bind-test-child1 {
290 compatible = "sandbox,phy";
291 #phy-cells = <1>;
292 };
293
294 bind-test-child2 {
295 compatible = "simple-bus";
296 };
297 };
298
Simon Glassb2c1cac2014-02-26 15:59:21 -0700299 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600300 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700301 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600302 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700303 ping-add = <3>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530304
305 mux-controls = <&muxcontroller0 0>;
306 mux-control-names = "mux0";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700307 };
308
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200309 phy_provider0: gen_phy@0 {
310 compatible = "sandbox,phy";
311 #phy-cells = <1>;
312 };
313
314 phy_provider1: gen_phy@1 {
315 compatible = "sandbox,phy";
316 #phy-cells = <0>;
317 broken;
318 };
319
developer71092972020-05-02 11:35:12 +0200320 phy_provider2: gen_phy@2 {
321 compatible = "sandbox,phy";
322 #phy-cells = <0>;
323 };
324
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200325 gen_phy_user: gen_phy_user {
326 compatible = "simple-bus";
327 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
328 phy-names = "phy1", "phy2", "phy3";
329 };
330
developer71092972020-05-02 11:35:12 +0200331 gen_phy_user1: gen_phy_user1 {
332 compatible = "simple-bus";
333 phys = <&phy_provider0 0>, <&phy_provider2>;
334 phy-names = "phy1", "phy2";
335 };
336
Simon Glassb2c1cac2014-02-26 15:59:21 -0700337 some-bus {
338 #address-cells = <1>;
339 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600340 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600341 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600342 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700343 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600344 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700345 compatible = "denx,u-boot-fdt-test";
346 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600347 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700348 ping-add = <5>;
349 };
Simon Glass40717422014-07-23 06:55:18 -0600350 c-test@0 {
351 compatible = "denx,u-boot-fdt-test";
352 reg = <0>;
353 ping-expect = <6>;
354 ping-add = <6>;
355 };
356 c-test@1 {
357 compatible = "denx,u-boot-fdt-test";
358 reg = <1>;
359 ping-expect = <7>;
360 ping-add = <7>;
361 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700362 };
363
364 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600365 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600366 ping-expect = <6>;
367 ping-add = <6>;
368 compatible = "google,another-fdt-test";
369 };
370
371 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600372 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600373 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700374 ping-add = <6>;
375 compatible = "google,another-fdt-test";
376 };
377
Simon Glass0ccb0972015-01-25 08:27:05 -0700378 f-test {
379 compatible = "denx,u-boot-fdt-test";
380 };
381
382 g-test {
383 compatible = "denx,u-boot-fdt-test";
384 };
385
Bin Mengd9d24782018-10-10 22:07:01 -0700386 h-test {
387 compatible = "denx,u-boot-fdt-test1";
388 };
389
developercf8bc132020-05-02 11:35:10 +0200390 i-test {
391 compatible = "mediatek,u-boot-fdt-test";
392 #address-cells = <1>;
393 #size-cells = <0>;
394
395 subnode@0 {
396 reg = <0>;
397 };
398
399 subnode@1 {
400 reg = <1>;
401 };
402
403 subnode@2 {
404 reg = <2>;
405 };
406 };
407
Simon Glass204675c2019-12-29 21:19:25 -0700408 devres-test {
409 compatible = "denx,u-boot-devres-test";
410 };
411
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530412 another-test {
413 reg = <0 2>;
414 compatible = "denx,u-boot-fdt-test";
415 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
416 test5-gpios = <&gpio_a 19>;
417 };
418
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100419 mmio-bus@0 {
420 #address-cells = <1>;
421 #size-cells = <1>;
422 compatible = "denx,u-boot-test-bus";
423 dma-ranges = <0x10000000 0x00000000 0x00040000>;
424
425 subnode@0 {
426 compatible = "denx,u-boot-fdt-test";
427 };
428 };
429
430 mmio-bus@1 {
431 #address-cells = <1>;
432 #size-cells = <1>;
433 compatible = "denx,u-boot-test-bus";
Nicolas Saenz Julienne892e9b42021-01-12 13:55:25 +0100434
435 subnode@0 {
436 compatible = "denx,u-boot-fdt-test";
437 };
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100438 };
439
Simon Glass3c601b12020-07-07 13:12:06 -0600440 acpi_test1: acpi-test {
Simon Glass2d67fdf2020-04-08 16:57:34 -0600441 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600442 acpi-ssdt-test-data = "ab";
Simon Glass990cd5b2020-07-07 13:12:08 -0600443 acpi-dsdt-test-data = "hi";
Simon Glassebb2e832020-07-07 13:11:39 -0600444 child {
445 compatible = "denx,u-boot-acpi-test";
446 };
Simon Glass2d67fdf2020-04-08 16:57:34 -0600447 };
448
Simon Glass3c601b12020-07-07 13:12:06 -0600449 acpi_test2: acpi-test2 {
Simon Glass17968c32020-04-26 09:19:46 -0600450 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600451 acpi-ssdt-test-data = "cd";
Simon Glass990cd5b2020-07-07 13:12:08 -0600452 acpi-dsdt-test-data = "jk";
Simon Glass17968c32020-04-26 09:19:46 -0600453 };
454
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200455 clocks {
456 clk_fixed: clk-fixed {
457 compatible = "fixed-clock";
458 #clock-cells = <0>;
459 clock-frequency = <1234>;
460 };
Anup Patel8d28c3c2019-02-25 08:14:55 +0000461
462 clk_fixed_factor: clk-fixed-factor {
463 compatible = "fixed-factor-clock";
464 #clock-cells = <0>;
465 clock-div = <3>;
466 clock-mult = <2>;
467 clocks = <&clk_fixed>;
468 };
Lukasz Majewskiccafcdd2019-06-24 15:50:47 +0200469
470 osc {
471 compatible = "fixed-clock";
472 #clock-cells = <0>;
473 clock-frequency = <20000000>;
474 };
Stephen Warrena9622432016-06-17 09:44:00 -0600475 };
476
477 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600478 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600479 #clock-cells = <1>;
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200480 assigned-clocks = <&clk_sandbox 3>;
481 assigned-clock-rates = <321>;
Stephen Warrena9622432016-06-17 09:44:00 -0600482 };
483
484 clk-test {
485 compatible = "sandbox,clk-test";
486 clocks = <&clk_fixed>,
487 <&clk_sandbox 1>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200488 <&clk_sandbox 0>,
489 <&clk_sandbox 3>,
490 <&clk_sandbox 2>;
491 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass8cc4d822015-07-06 12:54:24 -0600492 };
493
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200494 ccf: clk-ccf {
495 compatible = "sandbox,clk-ccf";
496 };
497
Simon Glass5b968632015-05-22 15:42:15 -0600498 eth@10002000 {
499 compatible = "sandbox,eth";
500 reg = <0x10002000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500501 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass5b968632015-05-22 15:42:15 -0600502 };
503
504 eth_5: eth@10003000 {
505 compatible = "sandbox,eth";
506 reg = <0x10003000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500507 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass5b968632015-05-22 15:42:15 -0600508 };
509
Bin Meng04a11cb2015-08-27 22:25:53 -0700510 eth_3: sbe5 {
511 compatible = "sandbox,eth";
512 reg = <0x10005000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500513 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng04a11cb2015-08-27 22:25:53 -0700514 };
515
Simon Glass5b968632015-05-22 15:42:15 -0600516 eth@10004000 {
517 compatible = "sandbox,eth";
518 reg = <0x10004000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500519 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass5b968632015-05-22 15:42:15 -0600520 };
521
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800522 dsa_eth0: dsa-test-eth {
523 compatible = "sandbox,eth";
524 reg = <0x10006000 0x1000>;
525 fake-host-hwaddr = [00 00 66 44 22 66];
526 };
527
528 dsa-test {
529 compatible = "sandbox,dsa";
530
531 ports {
532 #address-cells = <1>;
533 #size-cells = <0>;
534 swp_0: port@0 {
535 reg = <0>;
536 label = "lan0";
537 phy-mode = "rgmii-rxid";
538
539 fixed-link {
540 speed = <100>;
541 full-duplex;
542 };
543 };
544
545 swp_1: port@1 {
546 reg = <1>;
547 label = "lan1";
548 phy-mode = "rgmii-txid";
Bin Meng381ed972021-03-14 20:14:58 +0800549 fixed-link = <0 1 100 0 0>;
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800550 };
551
552 port@2 {
553 reg = <2>;
554 ethernet = <&dsa_eth0>;
555
556 fixed-link {
557 speed = <1000>;
558 full-duplex;
559 };
560 };
561 };
562 };
563
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700564 firmware {
565 sandbox_firmware: sandbox-firmware {
566 compatible = "sandbox,firmware";
567 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200568
569 sandbox-scmi-agent@0 {
570 compatible = "sandbox,scmi-agent";
571 #address-cells = <1>;
572 #size-cells = <0>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200573
574 clk_scmi0: protocol@14 {
575 reg = <0x14>;
576 #clock-cells = <1>;
577 };
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200578
579 reset_scmi0: protocol@16 {
580 reg = <0x16>;
581 #reset-cells = <1>;
582 };
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100583
584 protocol@17 {
585 reg = <0x17>;
586
587 regulators {
588 #address-cells = <1>;
589 #size-cells = <0>;
590
591 regul0_scmi0: reg@0 {
592 reg = <0>;
593 regulator-name = "sandbox-voltd0";
594 regulator-min-microvolt = <1100000>;
595 regulator-max-microvolt = <3300000>;
596 };
597 regul1_scmi0: reg@1 {
598 reg = <0x1>;
599 regulator-name = "sandbox-voltd1";
600 regulator-min-microvolt = <1800000>;
601 };
602 };
603 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200604 };
605
606 sandbox-scmi-agent@1 {
607 compatible = "sandbox,scmi-agent";
608 #address-cells = <1>;
609 #size-cells = <0>;
610
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200611 clk_scmi1: protocol@14 {
612 reg = <0x14>;
613 #clock-cells = <1>;
614 };
615
Etienne Carriere02fd1262020-09-09 18:44:00 +0200616 protocol@10 {
617 reg = <0x10>;
618 };
619 };
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700620 };
621
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100622 pinctrl-gpio {
623 compatible = "sandbox,pinctrl-gpio";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700624
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100625 gpio_a: base-gpios {
626 compatible = "sandbox,gpio";
627 gpio-controller;
628 #gpio-cells = <1>;
629 gpio-bank-name = "a";
630 sandbox,gpio-count = <20>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200631 hog_input_active_low {
632 gpio-hog;
633 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200634 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200635 };
636 hog_input_active_high {
637 gpio-hog;
638 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200639 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200640 };
641 hog_output_low {
642 gpio-hog;
643 output-low;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200644 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200645 };
646 hog_output_high {
647 gpio-hog;
648 output-high;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200649 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200650 };
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100651 };
652
653 gpio_b: extra-gpios {
654 compatible = "sandbox,gpio";
655 gpio-controller;
656 #gpio-cells = <5>;
657 gpio-bank-name = "b";
658 sandbox,gpio-count = <10>;
659 };
Simon Glass25348a42014-10-13 23:42:11 -0600660
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100661 gpio_c: pinmux-gpios {
662 compatible = "sandbox,gpio";
663 gpio-controller;
664 #gpio-cells = <2>;
665 gpio-bank-name = "c";
666 sandbox,gpio-count = <10>;
667 };
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100668 };
669
Simon Glass7df766e2014-12-10 08:55:55 -0700670 i2c@0 {
671 #address-cells = <1>;
672 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600673 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700674 compatible = "sandbox,i2c";
675 clock-frequency = <100000>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200676 pinctrl-names = "default";
677 pinctrl-0 = <&pinmux_i2c0_pins>;
678
Simon Glass7df766e2014-12-10 08:55:55 -0700679 eeprom@2c {
680 reg = <0x2c>;
681 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700682 sandbox,emul = <&emul_eeprom>;
Michal Simek4f18f922020-05-28 11:48:55 +0200683 partitions {
684 compatible = "fixed-partitions";
685 #address-cells = <1>;
686 #size-cells = <1>;
687 bootcount_i2c: bootcount@10 {
688 reg = <10 2>;
689 };
690 };
Simon Glass7df766e2014-12-10 08:55:55 -0700691 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200692
Simon Glass336b2952015-05-22 15:42:17 -0600693 rtc_0: rtc@43 {
694 reg = <0x43>;
695 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700696 sandbox,emul = <&emul0>;
Simon Glass336b2952015-05-22 15:42:17 -0600697 };
698
699 rtc_1: rtc@61 {
700 reg = <0x61>;
701 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700702 sandbox,emul = <&emul1>;
703 };
704
705 i2c_emul: emul {
706 reg = <0xff>;
707 compatible = "sandbox,i2c-emul-parent";
708 emul_eeprom: emul-eeprom {
709 compatible = "sandbox,i2c-eeprom";
710 sandbox,filename = "i2c.bin";
711 sandbox,size = <256>;
712 };
713 emul0: emul0 {
Simon Glass98af3742021-02-03 06:01:17 -0700714 compatible = "sandbox,i2c-rtc-emul";
Simon Glass17b56f62018-11-18 08:14:34 -0700715 };
716 emul1: emull {
Simon Glass98af3742021-02-03 06:01:17 -0700717 compatible = "sandbox,i2c-rtc-emul";
Simon Glass336b2952015-05-22 15:42:17 -0600718 };
719 };
720
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200721 sandbox_pmic: sandbox_pmic {
722 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700723 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200724 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200725
726 mc34708: pmic@41 {
727 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700728 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200729 };
Simon Glass7df766e2014-12-10 08:55:55 -0700730 };
731
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100732 bootcount@0 {
733 compatible = "u-boot,bootcount-rtc";
734 rtc = <&rtc_1>;
735 offset = <0x13>;
736 };
737
Michal Simek4f18f922020-05-28 11:48:55 +0200738 bootcount {
739 compatible = "u-boot,bootcount-i2c-eeprom";
740 i2c-eeprom = <&bootcount_i2c>;
741 };
742
Nandor Han88895812021-06-10 15:40:38 +0300743 bootcount_4@0 {
744 compatible = "u-boot,bootcount-syscon";
745 syscon = <&syscon0>;
746 reg = <0x0 0x04>, <0x0 0x04>;
747 reg-names = "syscon_reg", "offset";
748 };
749
750 bootcount_2@0 {
751 compatible = "u-boot,bootcount-syscon";
752 syscon = <&syscon0>;
753 reg = <0x0 0x04>, <0x0 0x02> ;
754 reg-names = "syscon_reg", "offset";
755 };
756
Marek Szyprowskiad398592021-02-18 11:33:18 +0100757 adc: adc@0 {
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100758 compatible = "sandbox,adc";
Marek Szyprowskiad398592021-02-18 11:33:18 +0100759 #io-channel-cells = <1>;
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100760 vdd-supply = <&buck2>;
761 vss-microvolts = <0>;
762 };
763
Simon Glass515dcff2020-02-06 09:55:00 -0700764 irq: irq {
Simon Glass54028bc2019-12-06 21:41:59 -0700765 compatible = "sandbox,irq";
Simon Glass515dcff2020-02-06 09:55:00 -0700766 interrupt-controller;
767 #interrupt-cells = <2>;
Simon Glass54028bc2019-12-06 21:41:59 -0700768 };
769
Simon Glass90b6fef2016-01-18 19:52:26 -0700770 lcd {
771 u-boot,dm-pre-reloc;
772 compatible = "sandbox,lcd-sdl";
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200773 pinctrl-names = "default";
774 pinctrl-0 = <&pinmux_lcd_pins>;
Simon Glass90b6fef2016-01-18 19:52:26 -0700775 xres = <1366>;
776 yres = <768>;
777 };
778
Simon Glassd783eb32015-07-06 12:54:34 -0600779 leds {
780 compatible = "gpio-leds";
781
782 iracibble {
783 gpios = <&gpio_a 1 0>;
784 label = "sandbox:red";
785 };
786
787 martinet {
788 gpios = <&gpio_a 2 0>;
789 label = "sandbox:green";
790 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200791
792 default_on {
793 gpios = <&gpio_a 5 0>;
794 label = "sandbox:default_on";
795 default-state = "on";
796 };
797
798 default_off {
799 gpios = <&gpio_a 6 0>;
Sean Andersonfbf8d652020-09-14 11:02:03 -0400800 /* label intentionally omitted */
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200801 default-state = "off";
802 };
Simon Glassd783eb32015-07-06 12:54:34 -0600803 };
804
Rasmus Villemoes2b673872021-08-19 11:57:05 +0200805 gpio-wdt {
806 gpios = <&gpio_a 7 0>;
807 compatible = "linux,wdt-gpio";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +0200808 hw_margin_ms = <100>;
Rasmus Villemoes2b673872021-08-19 11:57:05 +0200809 always-running;
810 };
811
Stephen Warren62f2c902016-05-16 17:41:37 -0600812 mbox: mbox {
813 compatible = "sandbox,mbox";
814 #mbox-cells = <1>;
815 };
816
817 mbox-test {
818 compatible = "sandbox,mbox-test";
819 mboxes = <&mbox 100>, <&mbox 1>;
820 mbox-names = "other", "test";
821 };
822
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900823 cpus {
Sean Anderson79d3bba2020-09-28 10:52:23 -0400824 timebase-frequency = <2000000>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900825 cpu-test1 {
Sean Anderson79d3bba2020-09-28 10:52:23 -0400826 timebase-frequency = <3000000>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900827 compatible = "sandbox,cpu_sandbox";
828 u-boot,dm-pre-reloc;
829 };
Mario Sixdea5df72018-08-06 10:23:44 +0200830
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900831 cpu-test2 {
832 compatible = "sandbox,cpu_sandbox";
833 u-boot,dm-pre-reloc;
834 };
Mario Sixdea5df72018-08-06 10:23:44 +0200835
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900836 cpu-test3 {
837 compatible = "sandbox,cpu_sandbox";
838 u-boot,dm-pre-reloc;
839 };
Mario Sixdea5df72018-08-06 10:23:44 +0200840 };
841
Dave Gerlach75dbdfc2020-07-15 23:39:58 -0500842 chipid: chipid {
843 compatible = "sandbox,soc";
844 };
845
Simon Glassc953aaf2018-12-10 10:37:34 -0700846 i2s: i2s {
847 compatible = "sandbox,i2s";
848 #sound-dai-cells = <1>;
Simon Glass4d5814c2019-02-16 20:24:56 -0700849 sandbox,silent; /* Don't emit sounds while testing */
Simon Glassc953aaf2018-12-10 10:37:34 -0700850 };
851
Jean-Jacques Hiblotdb97c7f2019-07-05 09:33:57 +0200852 nop-test_0 {
853 compatible = "sandbox,nop_sandbox1";
854 nop-test_1 {
855 compatible = "sandbox,nop_sandbox2";
856 bind = "True";
857 };
858 nop-test_2 {
859 compatible = "sandbox,nop_sandbox2";
860 bind = "False";
861 };
862 };
863
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200864 misc-test {
865 compatible = "sandbox,misc_sandbox";
866 };
867
Simon Glasse4fef742017-04-23 20:02:07 -0600868 mmc2 {
869 compatible = "sandbox,mmc";
Simon Glass965cd402021-07-05 16:32:58 -0600870 non-removable;
Simon Glasse4fef742017-04-23 20:02:07 -0600871 };
872
873 mmc1 {
874 compatible = "sandbox,mmc";
875 };
876
877 mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -0600878 compatible = "sandbox,mmc";
879 };
880
Simon Glass53a68b32019-02-16 20:24:50 -0700881 pch {
882 compatible = "sandbox,pch";
883 };
884
Tom Rini4a3ca482020-02-11 12:41:23 -0500885 pci0: pci@0 {
Simon Glass3a6eae62015-03-05 12:25:34 -0700886 compatible = "sandbox,pci";
887 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500888 bus-range = <0x00 0xff>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700889 #address-cells = <3>;
890 #size-cells = <2>;
Simon Glass35464f72019-09-25 08:56:08 -0600891 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glass3a6eae62015-03-05 12:25:34 -0700892 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700893 pci@0,0 {
894 compatible = "pci-generic";
895 reg = <0x0000 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600896 sandbox,emul = <&swap_case_emul0_0>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700897 };
Alex Margineanf1274432019-06-07 11:24:24 +0300898 pci@1,0 {
899 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600900 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
901 reg = <0x02000814 0 0 0 0
902 0x01000810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600903 sandbox,emul = <&swap_case_emul0_1>;
Alex Margineanf1274432019-06-07 11:24:24 +0300904 };
Simon Glass937bb472019-12-06 21:41:57 -0700905 p2sb-pci@2,0 {
906 compatible = "sandbox,p2sb";
907 reg = <0x02001010 0 0 0 0>;
908 sandbox,emul = <&p2sb_emul>;
909
910 adder {
911 intel,p2sb-port-id = <3>;
912 compatible = "sandbox,adder";
913 };
914 };
Simon Glass8c501022019-12-06 21:41:54 -0700915 pci@1e,0 {
916 compatible = "sandbox,pmc";
917 reg = <0xf000 0 0 0 0>;
918 sandbox,emul = <&pmc_emul1e>;
919 acpi-base = <0x400>;
920 gpe0-dwx-mask = <0xf>;
921 gpe0-dwx-shift-base = <4>;
922 gpe0-dw = <6 7 9>;
923 gpe0-sts = <0x20>;
924 gpe0-en = <0x30>;
925 };
Simon Glass3a6eae62015-03-05 12:25:34 -0700926 pci@1f,0 {
927 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600928 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
929 reg = <0x0100f810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600930 sandbox,emul = <&swap_case_emul0_1f>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700931 };
932 };
933
Simon Glassb98ba4c2019-09-25 08:56:10 -0600934 pci-emul0 {
935 compatible = "sandbox,pci-emul-parent";
936 swap_case_emul0_0: emul0@0,0 {
937 compatible = "sandbox,swap-case";
938 };
939 swap_case_emul0_1: emul0@1,0 {
940 compatible = "sandbox,swap-case";
941 use-ea;
942 };
943 swap_case_emul0_1f: emul0@1f,0 {
944 compatible = "sandbox,swap-case";
945 };
Simon Glass937bb472019-12-06 21:41:57 -0700946 p2sb_emul: emul@2,0 {
947 compatible = "sandbox,p2sb-emul";
948 };
Simon Glass8c501022019-12-06 21:41:54 -0700949 pmc_emul1e: emul@1e,0 {
950 compatible = "sandbox,pmc-emul";
951 };
Simon Glassb98ba4c2019-09-25 08:56:10 -0600952 };
953
Tom Rini4a3ca482020-02-11 12:41:23 -0500954 pci1: pci@1 {
Bin Meng408e5902018-08-03 01:14:41 -0700955 compatible = "sandbox,pci";
956 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500957 bus-range = <0x00 0xff>;
Bin Meng408e5902018-08-03 01:14:41 -0700958 #address-cells = <3>;
959 #size-cells = <2>;
Suneel Garapati3ac3aec2019-10-19 17:10:20 -0700960 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
961 0x02000000 0 0x31000000 0x31000000 0 0x2000 // MEM1
962 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -0700963 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +0200964 0x0c 0x00 0x1234 0x5678
965 0x10 0x00 0x1234 0x5678>;
966 pci@10,0 {
967 reg = <0x8000 0 0 0 0>;
968 };
Bin Meng408e5902018-08-03 01:14:41 -0700969 };
970
Tom Rini4a3ca482020-02-11 12:41:23 -0500971 pci2: pci@2 {
Bin Meng510dddb2018-08-03 01:14:50 -0700972 compatible = "sandbox,pci";
973 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500974 bus-range = <0x00 0xff>;
Bin Meng510dddb2018-08-03 01:14:50 -0700975 #address-cells = <3>;
976 #size-cells = <2>;
977 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
978 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
979 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
980 pci@1f,0 {
981 compatible = "pci-generic";
982 reg = <0xf800 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600983 sandbox,emul = <&swap_case_emul2_1f>;
984 };
985 };
986
987 pci-emul2 {
988 compatible = "sandbox,pci-emul-parent";
989 swap_case_emul2_1f: emul2@1f,0 {
990 compatible = "sandbox,swap-case";
Bin Meng510dddb2018-08-03 01:14:50 -0700991 };
992 };
993
Ramon Friedc64f19b2019-04-27 11:15:23 +0300994 pci_ep: pci_ep {
995 compatible = "sandbox,pci_ep";
996 };
997
Simon Glass9c433fe2017-04-23 20:10:44 -0600998 probing {
999 compatible = "simple-bus";
1000 test1 {
1001 compatible = "denx,u-boot-probe-test";
1002 };
1003
1004 test2 {
1005 compatible = "denx,u-boot-probe-test";
1006 };
1007
1008 test3 {
1009 compatible = "denx,u-boot-probe-test";
1010 };
1011
1012 test4 {
1013 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001014 first-syscon = <&syscon0>;
1015 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunayee010432019-03-07 09:57:13 +01001016 third-syscon = <&syscon2>;
Simon Glass9c433fe2017-04-23 20:10:44 -06001017 };
1018 };
1019
Stephen Warren92c67fa2016-07-13 13:45:31 -06001020 pwrdom: power-domain {
1021 compatible = "sandbox,power-domain";
1022 #power-domain-cells = <1>;
1023 };
1024
1025 power-domain-test {
1026 compatible = "sandbox,power-domain-test";
1027 power-domains = <&pwrdom 2>;
1028 };
1029
Simon Glass5620cf82018-10-01 12:22:40 -06001030 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -06001031 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001032 #pwm-cells = <2>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001033 pinctrl-names = "default";
1034 pinctrl-0 = <&pinmux_pwm_pins>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001035 };
1036
1037 pwm2 {
1038 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001039 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001040 };
1041
Simon Glass3d355e62015-07-06 12:54:31 -06001042 ram {
1043 compatible = "sandbox,ram";
1044 };
1045
Simon Glassd860f222015-07-06 12:54:29 -06001046 reset@0 {
1047 compatible = "sandbox,warm-reset";
1048 };
1049
1050 reset@1 {
1051 compatible = "sandbox,reset";
1052 };
1053
Stephen Warren6488e642016-06-17 09:43:59 -06001054 resetc: reset-ctl {
1055 compatible = "sandbox,reset-ctl";
1056 #reset-cells = <1>;
1057 };
1058
1059 reset-ctl-test {
1060 compatible = "sandbox,reset-ctl-test";
Neil Armstrong9b4cdef2021-04-20 10:42:25 +02001061 resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>;
1062 reset-names = "other", "test", "test2", "test3";
Stephen Warren6488e642016-06-17 09:43:59 -06001063 };
1064
Sughosh Ganu23e37512019-12-28 23:58:31 +05301065 rng {
1066 compatible = "sandbox,sandbox-rng";
1067 };
1068
Nishanth Menonedf85812015-09-17 15:42:41 -05001069 rproc_1: rproc@1 {
1070 compatible = "sandbox,test-processor";
1071 remoteproc-name = "remoteproc-test-dev1";
1072 };
1073
1074 rproc_2: rproc@2 {
1075 compatible = "sandbox,test-processor";
1076 internal-memory-mapped;
1077 remoteproc-name = "remoteproc-test-dev2";
1078 };
1079
Simon Glass5620cf82018-10-01 12:22:40 -06001080 panel {
1081 compatible = "simple-panel";
1082 backlight = <&backlight 0 100>;
1083 };
1084
Ramon Fried26ed32e2018-07-02 02:57:59 +03001085 smem@0 {
1086 compatible = "sandbox,smem";
1087 };
1088
Simon Glass76072ac2018-12-10 10:37:36 -07001089 sound {
1090 compatible = "sandbox,sound";
1091 cpu {
1092 sound-dai = <&i2s 0>;
1093 };
1094
1095 codec {
1096 sound-dai = <&audio 0>;
1097 };
1098 };
1099
Simon Glass25348a42014-10-13 23:42:11 -06001100 spi@0 {
1101 #address-cells = <1>;
1102 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -06001103 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -06001104 compatible = "sandbox,spi";
Ovidiu Panaitae734732020-12-14 19:06:47 +02001105 cs-gpios = <0>, <0>, <&gpio_a 0>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001106 pinctrl-names = "default";
1107 pinctrl-0 = <&pinmux_spi0_pins>;
1108
Simon Glass25348a42014-10-13 23:42:11 -06001109 spi.bin@0 {
1110 reg = <0>;
Neil Armstronga009fa72019-02-10 10:16:20 +00001111 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass25348a42014-10-13 23:42:11 -06001112 spi-max-frequency = <40000000>;
1113 sandbox,filename = "spi.bin";
1114 };
Ovidiu Panaitae734732020-12-14 19:06:47 +02001115 spi.bin@1 {
1116 reg = <1>;
1117 compatible = "spansion,m25p16", "jedec,spi-nor";
1118 spi-max-frequency = <50000000>;
1119 sandbox,filename = "spi.bin";
1120 spi-cpol;
1121 spi-cpha;
1122 };
Simon Glass25348a42014-10-13 23:42:11 -06001123 };
1124
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001125 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -06001126 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +02001127 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -06001128 };
1129
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001130 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -06001131 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -06001132 reg = <0x20 5
1133 0x28 6
1134 0x30 7
1135 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -06001136 };
1137
Patrick Delaunayee010432019-03-07 09:57:13 +01001138 syscon2: syscon@2 {
Masahiro Yamada42ab1072018-04-23 13:26:53 +09001139 compatible = "simple-mfd", "syscon";
1140 reg = <0x40 5
1141 0x48 6
1142 0x50 7
1143 0x58 8>;
1144 };
1145
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +05301146 syscon3: syscon@3 {
1147 compatible = "simple-mfd", "syscon";
1148 reg = <0x000100 0x10>;
1149
1150 muxcontroller0: a-mux-controller {
1151 compatible = "mmio-mux";
1152 #mux-control-cells = <1>;
1153
1154 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
1155 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
1156 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
1157 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
1158 u-boot,mux-autoprobe;
1159 };
1160 };
1161
1162 muxcontroller1: emul-mux-controller {
1163 compatible = "mux-emul";
1164 #mux-control-cells = <0>;
1165 u-boot,mux-autoprobe;
1166 idle-state = <0xabcd>;
1167 };
1168
Simon Glass791a17f2020-12-16 21:20:27 -07001169 testfdtm0 {
1170 compatible = "denx,u-boot-fdtm-test";
1171 };
1172
1173 testfdtm1: testfdtm1 {
1174 compatible = "denx,u-boot-fdtm-test";
1175 };
1176
1177 testfdtm2 {
1178 compatible = "denx,u-boot-fdtm-test";
1179 };
1180
Sean Anderson79d3bba2020-09-28 10:52:23 -04001181 timer@0 {
Thomas Chou6f2cfbf2015-12-11 16:27:34 +08001182 compatible = "sandbox,timer";
1183 clock-frequency = <1000000>;
1184 };
1185
Sean Anderson79d3bba2020-09-28 10:52:23 -04001186 timer@1 {
1187 compatible = "sandbox,timer";
1188 sandbox,timebase-frequency-fallback;
1189 };
1190
Miquel Raynal80938c12018-05-15 11:57:27 +02001191 tpm2 {
1192 compatible = "sandbox,tpm2";
1193 };
1194
Simon Glass5b968632015-05-22 15:42:15 -06001195 uart0: serial {
1196 compatible = "sandbox,serial";
1197 u-boot,dm-pre-reloc;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001198 pinctrl-names = "default";
1199 pinctrl-0 = <&pinmux_uart0_pins>;
Joe Hershberger4c197242015-03-22 17:09:15 -05001200 };
1201
Simon Glass31680482015-03-25 12:23:05 -06001202 usb_0: usb@0 {
1203 compatible = "sandbox,usb";
1204 status = "disabled";
1205 hub {
1206 compatible = "sandbox,usb-hub";
1207 #address-cells = <1>;
1208 #size-cells = <0>;
1209 flash-stick {
1210 reg = <0>;
1211 compatible = "sandbox,usb-flash";
1212 };
1213 };
1214 };
1215
1216 usb_1: usb@1 {
1217 compatible = "sandbox,usb";
1218 hub {
1219 compatible = "usb-hub";
1220 usb,device-class = <9>;
Michael Walle7c961322020-06-02 01:47:07 +02001221 #address-cells = <1>;
1222 #size-cells = <0>;
Simon Glass31680482015-03-25 12:23:05 -06001223 hub-emul {
1224 compatible = "sandbox,usb-hub";
1225 #address-cells = <1>;
1226 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -07001227 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -06001228 reg = <0>;
1229 compatible = "sandbox,usb-flash";
1230 sandbox,filepath = "testflash.bin";
1231 };
1232
Simon Glass4700fe52015-11-08 23:48:01 -07001233 flash-stick@1 {
1234 reg = <1>;
1235 compatible = "sandbox,usb-flash";
1236 sandbox,filepath = "testflash1.bin";
1237 };
1238
1239 flash-stick@2 {
1240 reg = <2>;
1241 compatible = "sandbox,usb-flash";
1242 sandbox,filepath = "testflash2.bin";
1243 };
1244
Simon Glassc0ccc722015-11-08 23:48:08 -07001245 keyb@3 {
1246 reg = <3>;
1247 compatible = "sandbox,usb-keyb";
1248 };
1249
Simon Glass31680482015-03-25 12:23:05 -06001250 };
Michael Walle7c961322020-06-02 01:47:07 +02001251
1252 usbstor@1 {
1253 reg = <1>;
1254 };
1255 usbstor@3 {
1256 reg = <3>;
1257 };
Simon Glass31680482015-03-25 12:23:05 -06001258 };
1259 };
1260
1261 usb_2: usb@2 {
1262 compatible = "sandbox,usb";
1263 status = "disabled";
1264 };
1265
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001266 spmi: spmi@0 {
1267 compatible = "sandbox,spmi";
1268 #address-cells = <0x1>;
1269 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001270 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001271 pm8916@0 {
1272 compatible = "qcom,spmi-pmic";
1273 reg = <0x0 0x1>;
1274 #address-cells = <0x1>;
1275 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001276 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001277
1278 spmi_gpios: gpios@c000 {
1279 compatible = "qcom,pm8916-gpio";
1280 reg = <0xc000 0x400>;
1281 gpio-controller;
1282 gpio-count = <4>;
1283 #gpio-cells = <2>;
1284 gpio-bank-name="spmi";
1285 };
1286 };
1287 };
maxims@google.comdaea6d42017-04-17 12:00:21 -07001288
1289 wdt0: wdt@0 {
1290 compatible = "sandbox,wdt";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +02001291 hw_margin_ms = <200>;
maxims@google.comdaea6d42017-04-17 12:00:21 -07001292 };
Rob Clarka471b672018-01-10 11:33:30 +01001293
Mario Six95922152018-08-09 14:51:19 +02001294 axi: axi@0 {
1295 compatible = "sandbox,axi";
1296 #address-cells = <0x1>;
1297 #size-cells = <0x1>;
1298 store@0 {
1299 compatible = "sandbox,sandbox_store";
1300 reg = <0x0 0x400>;
1301 };
1302 };
1303
Rob Clarka471b672018-01-10 11:33:30 +01001304 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -07001305 #address-cells = <1>;
1306 #size-cells = <1>;
Simon Glassf3455962020-01-27 08:49:43 -07001307 setting = "sunrise ohoka";
1308 other-node = "/some-bus/c-test@5";
Simon Glasse09223c2020-01-27 08:49:46 -07001309 int-values = <0x1937 72993>;
Simon Glass3c601b12020-07-07 13:12:06 -06001310 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarka471b672018-01-10 11:33:30 +01001311 chosen-test {
1312 compatible = "denx,u-boot-fdt-test";
1313 reg = <9 1>;
1314 };
1315 };
Mario Six35616ef2018-03-12 14:53:33 +01001316
1317 translation-test@8000 {
1318 compatible = "simple-bus";
1319 reg = <0x8000 0x4000>;
1320
1321 #address-cells = <0x2>;
1322 #size-cells = <0x1>;
1323
1324 ranges = <0 0x0 0x8000 0x1000
1325 1 0x100 0x9000 0x1000
1326 2 0x200 0xA000 0x1000
1327 3 0x300 0xB000 0x1000
1328 >;
1329
Fabien Dessenne22236e02019-05-31 15:11:30 +02001330 dma-ranges = <0 0x000 0x10000000 0x1000
1331 1 0x100 0x20000000 0x1000
1332 >;
1333
Mario Six35616ef2018-03-12 14:53:33 +01001334 dev@0,0 {
1335 compatible = "denx,u-boot-fdt-dummy";
1336 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojasa3181152018-12-03 19:37:09 +01001337 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +01001338 };
1339
1340 dev@1,100 {
1341 compatible = "denx,u-boot-fdt-dummy";
1342 reg = <1 0x100 0x1000>;
1343
1344 };
1345
1346 dev@2,200 {
1347 compatible = "denx,u-boot-fdt-dummy";
1348 reg = <2 0x200 0x1000>;
1349 };
1350
1351
1352 noxlatebus@3,300 {
1353 compatible = "simple-bus";
1354 reg = <3 0x300 0x1000>;
1355
1356 #address-cells = <0x1>;
1357 #size-cells = <0x0>;
1358
1359 dev@42 {
1360 compatible = "denx,u-boot-fdt-dummy";
1361 reg = <0x42>;
1362 };
1363 };
1364 };
Mario Six02ad6fb2018-09-27 09:19:31 +02001365
1366 osd {
1367 compatible = "sandbox,sandbox_osd";
1368 };
Tom Rinib93eea72018-09-30 18:16:51 -04001369
Jens Wiklander86afaa62018-09-25 16:40:16 +02001370 sandbox_tee {
1371 compatible = "sandbox,tee";
1372 };
Bin Meng1bb290d2018-10-15 02:21:26 -07001373
1374 sandbox_virtio1 {
1375 compatible = "sandbox,virtio1";
1376 };
1377
1378 sandbox_virtio2 {
1379 compatible = "sandbox,virtio2";
1380 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001381
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001382 sandbox_scmi {
1383 compatible = "sandbox,scmi-devices";
1384 clocks = <&clk_scmi0 7>, <&clk_scmi0 3>, <&clk_scmi1 1>;
Etienne Carriere8b9b6892020-09-09 18:44:07 +02001385 resets = <&reset_scmi0 3>;
Etienne Carriereb8f15cd2021-03-08 22:38:07 +01001386 regul0-supply = <&regul0_scmi0>;
1387 regul1-supply = <&regul1_scmi0>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001388 };
1389
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001390 pinctrl {
1391 compatible = "sandbox,pinctrl";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001392
Sean Anderson3438e3b2020-09-14 11:01:57 -04001393 pinctrl-names = "default", "alternate";
1394 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1395 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001396
Sean Anderson3438e3b2020-09-14 11:01:57 -04001397 pinctrl_gpios: gpios {
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001398 gpio0 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001399 pins = "P5";
1400 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001401 bias-pull-up;
1402 input-disable;
1403 };
1404 gpio1 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001405 pins = "P6";
1406 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001407 output-high;
1408 drive-open-drain;
1409 };
1410 gpio2 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001411 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001412 bias-pull-down;
1413 input-enable;
1414 };
1415 gpio3 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001416 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001417 bias-disable;
1418 };
1419 };
Sean Anderson3438e3b2020-09-14 11:01:57 -04001420
1421 pinctrl_i2c: i2c {
1422 groups {
1423 groups = "I2C_UART";
1424 function = "I2C";
1425 };
1426
1427 pins {
1428 pins = "P0", "P1";
1429 drive-open-drain;
1430 };
1431 };
1432
1433 pinctrl_i2s: i2s {
1434 groups = "SPI_I2S";
1435 function = "I2S";
1436 };
1437
1438 pinctrl_spi: spi {
1439 groups = "SPI_I2S";
1440 function = "SPI";
1441
1442 cs {
1443 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1444 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1445 };
1446 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001447 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001448
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001449 pinctrl-single-no-width {
1450 compatible = "pinctrl-single";
1451 reg = <0x0000 0x238>;
1452 #pinctrl-cells = <1>;
1453 pinctrl-single,function-mask = <0x7f>;
1454 };
1455
1456 pinctrl-single-pins {
1457 compatible = "pinctrl-single";
1458 reg = <0x0000 0x238>;
1459 #pinctrl-cells = <1>;
1460 pinctrl-single,register-width = <32>;
1461 pinctrl-single,function-mask = <0x7f>;
1462
1463 pinmux_pwm_pins: pinmux_pwm_pins {
1464 pinctrl-single,pins = < 0x48 0x06 >;
1465 };
1466
1467 pinmux_spi0_pins: pinmux_spi0_pins {
1468 pinctrl-single,pins = <
1469 0x190 0x0c
1470 0x194 0x0c
1471 0x198 0x23
1472 0x19c 0x0c
1473 >;
1474 };
1475
1476 pinmux_uart0_pins: pinmux_uart0_pins {
1477 pinctrl-single,pins = <
1478 0x70 0x30
1479 0x74 0x00
1480 >;
1481 };
1482 };
1483
1484 pinctrl-single-bits {
1485 compatible = "pinctrl-single";
1486 reg = <0x0000 0x50>;
1487 #pinctrl-cells = <2>;
1488 pinctrl-single,bit-per-mux;
1489 pinctrl-single,register-width = <32>;
1490 pinctrl-single,function-mask = <0xf>;
1491
1492 pinmux_i2c0_pins: pinmux_i2c0_pins {
1493 pinctrl-single,bits = <
1494 0x10 0x00002200 0x0000ff00
1495 >;
1496 };
1497
1498 pinmux_lcd_pins: pinmux_lcd_pins {
1499 pinctrl-single,bits = <
1500 0x40 0x22222200 0xffffff00
1501 0x44 0x22222222 0xffffffff
1502 0x48 0x00000022 0x000000ff
1503 0x48 0x02000000 0x0f000000
1504 0x4c 0x02000022 0x0f0000ff
1505 >;
1506 };
1507 };
1508
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001509 hwspinlock@0 {
1510 compatible = "sandbox,hwspinlock";
1511 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +01001512
1513 dma: dma {
1514 compatible = "sandbox,dma";
1515 #dma-cells = <1>;
1516
1517 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1518 dma-names = "m2m", "tx0", "rx0";
1519 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001520
Alex Marginean0649be52019-07-12 10:13:53 +03001521 /*
1522 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1523 * end of the test. If parent mdio is removed first, clean-up of the
1524 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1525 * active at the end of the test. That it turn doesn't allow the mdio
1526 * class to be destroyed, triggering an error.
1527 */
1528 mdio-mux-test {
1529 compatible = "sandbox,mdio-mux";
1530 #address-cells = <1>;
1531 #size-cells = <0>;
1532 mdio-parent-bus = <&mdio>;
1533
1534 mdio-ch-test@0 {
1535 reg = <0>;
1536 };
1537 mdio-ch-test@1 {
1538 reg = <1>;
1539 };
1540 };
1541
1542 mdio: mdio-test {
Alex Marginean0daa53a2019-06-03 19:12:28 +03001543 compatible = "sandbox,mdio";
1544 };
Sean Andersonb7860542020-06-24 06:41:12 -04001545
1546 pm-bus-test {
1547 compatible = "simple-pm-bus";
1548 clocks = <&clk_sandbox 4>;
1549 power-domains = <&pwrdom 1>;
1550 };
Sean Anderson0c1f6bf2020-06-24 06:41:14 -04001551
1552 resetc2: syscon-reset {
1553 compatible = "syscon-reset";
1554 #reset-cells = <1>;
1555 regmap = <&syscon0>;
1556 offset = <1>;
1557 mask = <0x27FFFFFF>;
1558 assert-high = <0>;
1559 };
1560
1561 syscon-reset-test {
1562 compatible = "sandbox,misc_sandbox";
1563 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1564 reset-names = "valid", "no_mask", "out_of_range";
1565 };
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301566
Simon Glass458b66a2020-11-05 06:32:05 -07001567 sysinfo {
1568 compatible = "sandbox,sysinfo-sandbox";
1569 };
1570
Sean Anderson1c830672021-04-20 10:50:58 -04001571 sysinfo-gpio {
1572 compatible = "gpio-sysinfo";
1573 gpios = <&gpio_a 15>, <&gpio_a 16>, <&gpio_a 17>;
1574 revisions = <19>, <5>;
1575 names = "rev_a", "foo";
1576 };
1577
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301578 some_regmapped-bus {
1579 #address-cells = <0x1>;
1580 #size-cells = <0x1>;
1581
1582 ranges = <0x0 0x0 0x10>;
1583 compatible = "simple-bus";
1584
1585 regmap-test_0 {
1586 reg = <0 0x10>;
1587 compatible = "sandbox,regmap_test";
1588 };
1589 };
Simon Glassb2c1cac2014-02-26 15:59:21 -07001590};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +02001591
1592#include "sandbox_pmic.dtsi"
Heinrich Schuchardte24fdef2021-02-18 13:01:35 +01001593#include "cros-ec-keyboard.dtsi"