Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) |
| 2 | /* |
| 3 | * Copyright (C) STMicroelectronics 2017 - All Rights Reserved |
| 4 | * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. |
| 5 | */ |
| 6 | #include <dt-bindings/pinctrl/stm32-pinfunc.h> |
| 7 | |
| 8 | / { |
| 9 | soc { |
| 10 | pinctrl: pin-controller@50002000 { |
| 11 | #address-cells = <1>; |
| 12 | #size-cells = <1>; |
| 13 | compatible = "st,stm32mp157-pinctrl"; |
| 14 | ranges = <0 0x50002000 0xa400>; |
| 15 | interrupt-parent = <&exti>; |
| 16 | st,syscfg = <&exti 0x60 0xff>; |
Patrick Delaunay | a370530 | 2019-07-11 11:15:28 +0200 | [diff] [blame] | 17 | hwlocks = <&hwspinlock 0>; |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 18 | pins-are-numbered; |
| 19 | |
| 20 | gpioa: gpio@50002000 { |
| 21 | gpio-controller; |
| 22 | #gpio-cells = <2>; |
| 23 | interrupt-controller; |
| 24 | #interrupt-cells = <2>; |
| 25 | reg = <0x0 0x400>; |
| 26 | clocks = <&rcc GPIOA>; |
| 27 | st,bank-name = "GPIOA"; |
Patrick Delaunay | 708cae7 | 2019-07-30 19:16:12 +0200 | [diff] [blame] | 28 | status = "disabled"; |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 29 | }; |
| 30 | |
| 31 | gpiob: gpio@50003000 { |
| 32 | gpio-controller; |
| 33 | #gpio-cells = <2>; |
| 34 | interrupt-controller; |
| 35 | #interrupt-cells = <2>; |
| 36 | reg = <0x1000 0x400>; |
| 37 | clocks = <&rcc GPIOB>; |
| 38 | st,bank-name = "GPIOB"; |
Patrick Delaunay | 708cae7 | 2019-07-30 19:16:12 +0200 | [diff] [blame] | 39 | status = "disabled"; |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 40 | }; |
| 41 | |
| 42 | gpioc: gpio@50004000 { |
| 43 | gpio-controller; |
| 44 | #gpio-cells = <2>; |
| 45 | interrupt-controller; |
| 46 | #interrupt-cells = <2>; |
| 47 | reg = <0x2000 0x400>; |
| 48 | clocks = <&rcc GPIOC>; |
| 49 | st,bank-name = "GPIOC"; |
Patrick Delaunay | 708cae7 | 2019-07-30 19:16:12 +0200 | [diff] [blame] | 50 | status = "disabled"; |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 51 | }; |
| 52 | |
| 53 | gpiod: gpio@50005000 { |
| 54 | gpio-controller; |
| 55 | #gpio-cells = <2>; |
| 56 | interrupt-controller; |
| 57 | #interrupt-cells = <2>; |
| 58 | reg = <0x3000 0x400>; |
| 59 | clocks = <&rcc GPIOD>; |
| 60 | st,bank-name = "GPIOD"; |
Patrick Delaunay | 708cae7 | 2019-07-30 19:16:12 +0200 | [diff] [blame] | 61 | status = "disabled"; |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 62 | }; |
| 63 | |
| 64 | gpioe: gpio@50006000 { |
| 65 | gpio-controller; |
| 66 | #gpio-cells = <2>; |
| 67 | interrupt-controller; |
| 68 | #interrupt-cells = <2>; |
| 69 | reg = <0x4000 0x400>; |
| 70 | clocks = <&rcc GPIOE>; |
| 71 | st,bank-name = "GPIOE"; |
Patrick Delaunay | 708cae7 | 2019-07-30 19:16:12 +0200 | [diff] [blame] | 72 | status = "disabled"; |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 73 | }; |
| 74 | |
| 75 | gpiof: gpio@50007000 { |
| 76 | gpio-controller; |
| 77 | #gpio-cells = <2>; |
| 78 | interrupt-controller; |
| 79 | #interrupt-cells = <2>; |
| 80 | reg = <0x5000 0x400>; |
| 81 | clocks = <&rcc GPIOF>; |
| 82 | st,bank-name = "GPIOF"; |
Patrick Delaunay | 708cae7 | 2019-07-30 19:16:12 +0200 | [diff] [blame] | 83 | status = "disabled"; |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 84 | }; |
| 85 | |
| 86 | gpiog: gpio@50008000 { |
| 87 | gpio-controller; |
| 88 | #gpio-cells = <2>; |
| 89 | interrupt-controller; |
| 90 | #interrupt-cells = <2>; |
| 91 | reg = <0x6000 0x400>; |
| 92 | clocks = <&rcc GPIOG>; |
| 93 | st,bank-name = "GPIOG"; |
Patrick Delaunay | 708cae7 | 2019-07-30 19:16:12 +0200 | [diff] [blame] | 94 | status = "disabled"; |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 95 | }; |
| 96 | |
| 97 | gpioh: gpio@50009000 { |
| 98 | gpio-controller; |
| 99 | #gpio-cells = <2>; |
| 100 | interrupt-controller; |
| 101 | #interrupt-cells = <2>; |
| 102 | reg = <0x7000 0x400>; |
| 103 | clocks = <&rcc GPIOH>; |
| 104 | st,bank-name = "GPIOH"; |
Patrick Delaunay | 708cae7 | 2019-07-30 19:16:12 +0200 | [diff] [blame] | 105 | status = "disabled"; |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 106 | }; |
| 107 | |
| 108 | gpioi: gpio@5000a000 { |
| 109 | gpio-controller; |
| 110 | #gpio-cells = <2>; |
| 111 | interrupt-controller; |
| 112 | #interrupt-cells = <2>; |
| 113 | reg = <0x8000 0x400>; |
| 114 | clocks = <&rcc GPIOI>; |
| 115 | st,bank-name = "GPIOI"; |
Patrick Delaunay | 708cae7 | 2019-07-30 19:16:12 +0200 | [diff] [blame] | 116 | status = "disabled"; |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 117 | }; |
| 118 | |
| 119 | gpioj: gpio@5000b000 { |
| 120 | gpio-controller; |
| 121 | #gpio-cells = <2>; |
| 122 | interrupt-controller; |
| 123 | #interrupt-cells = <2>; |
| 124 | reg = <0x9000 0x400>; |
| 125 | clocks = <&rcc GPIOJ>; |
| 126 | st,bank-name = "GPIOJ"; |
Patrick Delaunay | 708cae7 | 2019-07-30 19:16:12 +0200 | [diff] [blame] | 127 | status = "disabled"; |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 128 | }; |
| 129 | |
| 130 | gpiok: gpio@5000c000 { |
| 131 | gpio-controller; |
| 132 | #gpio-cells = <2>; |
| 133 | interrupt-controller; |
| 134 | #interrupt-cells = <2>; |
| 135 | reg = <0xa000 0x400>; |
| 136 | clocks = <&rcc GPIOK>; |
| 137 | st,bank-name = "GPIOK"; |
Patrick Delaunay | 708cae7 | 2019-07-30 19:16:12 +0200 | [diff] [blame] | 138 | status = "disabled"; |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 139 | }; |
| 140 | |
Patrice Chotard | e861c20 | 2019-02-12 16:50:41 +0100 | [diff] [blame] | 141 | adc12_usb_pwr_pins_a: adc12-usb-pwr-pins-0 { |
| 142 | pins { |
| 143 | pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* ADC12 in18 */ |
| 144 | <STM32_PINMUX('A', 5, ANALOG)>; /* ADC12 in19 */ |
| 145 | }; |
| 146 | }; |
| 147 | |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 148 | cec_pins_a: cec-0 { |
| 149 | pins { |
| 150 | pinmux = <STM32_PINMUX('A', 15, AF4)>; |
| 151 | bias-disable; |
| 152 | drive-open-drain; |
| 153 | slew-rate = <0>; |
| 154 | }; |
| 155 | }; |
| 156 | |
Patrick Delaunay | a370530 | 2019-07-11 11:15:28 +0200 | [diff] [blame] | 157 | cec_pins_sleep_a: cec-sleep-0 { |
| 158 | pins { |
| 159 | pinmux = <STM32_PINMUX('A', 15, ANALOG)>; /* HDMI_CEC */ |
| 160 | }; |
| 161 | }; |
| 162 | |
| 163 | cec_pins_b: cec-1 { |
| 164 | pins { |
| 165 | pinmux = <STM32_PINMUX('B', 6, AF5)>; |
| 166 | bias-disable; |
| 167 | drive-open-drain; |
| 168 | slew-rate = <0>; |
| 169 | }; |
| 170 | }; |
| 171 | |
| 172 | cec_pins_sleep_b: cec-sleep-1 { |
| 173 | pins { |
| 174 | pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* HDMI_CEC */ |
| 175 | }; |
| 176 | }; |
| 177 | |
Patrick Delaunay | 708cae7 | 2019-07-30 19:16:12 +0200 | [diff] [blame] | 178 | dcmi_pins_a: dcmi-0 { |
| 179 | pins { |
| 180 | pinmux = <STM32_PINMUX('H', 8, AF13)>,/* DCMI_HSYNC */ |
| 181 | <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */ |
| 182 | <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */ |
| 183 | <STM32_PINMUX('H', 9, AF13)>,/* DCMI_D0 */ |
| 184 | <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */ |
| 185 | <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */ |
| 186 | <STM32_PINMUX('H', 12, AF13)>,/* DCMI_D3 */ |
| 187 | <STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */ |
| 188 | <STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */ |
| 189 | <STM32_PINMUX('B', 8, AF13)>,/* DCMI_D6 */ |
| 190 | <STM32_PINMUX('E', 6, AF13)>,/* DCMI_D7 */ |
| 191 | <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */ |
| 192 | <STM32_PINMUX('H', 7, AF13)>,/* DCMI_D9 */ |
| 193 | <STM32_PINMUX('I', 3, AF13)>,/* DCMI_D10 */ |
| 194 | <STM32_PINMUX('H', 15, AF13)>;/* DCMI_D11 */ |
| 195 | bias-disable; |
| 196 | }; |
| 197 | }; |
| 198 | |
| 199 | dcmi_sleep_pins_a: dcmi-sleep-0 { |
| 200 | pins { |
| 201 | pinmux = <STM32_PINMUX('H', 8, ANALOG)>,/* DCMI_HSYNC */ |
| 202 | <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */ |
| 203 | <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */ |
| 204 | <STM32_PINMUX('H', 9, ANALOG)>,/* DCMI_D0 */ |
| 205 | <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */ |
| 206 | <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */ |
| 207 | <STM32_PINMUX('H', 12, ANALOG)>,/* DCMI_D3 */ |
| 208 | <STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */ |
| 209 | <STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */ |
| 210 | <STM32_PINMUX('B', 8, ANALOG)>,/* DCMI_D6 */ |
| 211 | <STM32_PINMUX('E', 6, ANALOG)>,/* DCMI_D7 */ |
| 212 | <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */ |
| 213 | <STM32_PINMUX('H', 7, ANALOG)>,/* DCMI_D9 */ |
| 214 | <STM32_PINMUX('I', 3, ANALOG)>,/* DCMI_D10 */ |
| 215 | <STM32_PINMUX('H', 15, ANALOG)>;/* DCMI_D11 */ |
| 216 | }; |
| 217 | }; |
| 218 | |
Patrice Chotard | 00442d0 | 2019-02-12 16:50:38 +0100 | [diff] [blame] | 219 | ethernet0_rgmii_pins_a: rgmii-0 { |
| 220 | pins1 { |
| 221 | pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */ |
| 222 | <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */ |
| 223 | <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */ |
| 224 | <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */ |
| 225 | <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */ |
| 226 | <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */ |
| 227 | <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */ |
Patrice Chotard | 00442d0 | 2019-02-12 16:50:38 +0100 | [diff] [blame] | 228 | <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */ |
| 229 | bias-disable; |
| 230 | drive-push-pull; |
Christophe Roullier | 32ac305 | 2019-05-17 15:08:45 +0200 | [diff] [blame] | 231 | slew-rate = <2>; |
Patrice Chotard | 00442d0 | 2019-02-12 16:50:38 +0100 | [diff] [blame] | 232 | }; |
| 233 | pins2 { |
Christophe Roullier | 32ac305 | 2019-05-17 15:08:45 +0200 | [diff] [blame] | 234 | pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */ |
| 235 | bias-disable; |
| 236 | drive-push-pull; |
| 237 | slew-rate = <0>; |
| 238 | }; |
| 239 | pins3 { |
Patrice Chotard | 00442d0 | 2019-02-12 16:50:38 +0100 | [diff] [blame] | 240 | pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */ |
| 241 | <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */ |
| 242 | <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */ |
| 243 | <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */ |
| 244 | <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */ |
| 245 | <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */ |
| 246 | bias-disable; |
| 247 | }; |
| 248 | }; |
| 249 | |
| 250 | ethernet0_rgmii_pins_sleep_a: rgmii-sleep-0 { |
| 251 | pins1 { |
| 252 | pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */ |
| 253 | <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */ |
| 254 | <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */ |
| 255 | <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */ |
| 256 | <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */ |
| 257 | <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */ |
| 258 | <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */ |
| 259 | <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */ |
| 260 | <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */ |
| 261 | <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ |
| 262 | <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */ |
| 263 | <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD2 */ |
| 264 | <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */ |
| 265 | <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */ |
| 266 | <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */ |
| 267 | }; |
| 268 | }; |
| 269 | |
Patrick Delaunay | e0188ac | 2019-04-08 15:30:52 +0200 | [diff] [blame] | 270 | fmc_pins_a: fmc-0 { |
| 271 | pins1 { |
| 272 | pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */ |
| 273 | <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */ |
| 274 | <STM32_PINMUX('D', 11, AF12)>, /* FMC_A16_FMC_CLE */ |
| 275 | <STM32_PINMUX('D', 12, AF12)>, /* FMC_A17_FMC_ALE */ |
| 276 | <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */ |
| 277 | <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */ |
| 278 | <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */ |
| 279 | <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */ |
| 280 | <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */ |
| 281 | <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */ |
| 282 | <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */ |
| 283 | <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */ |
| 284 | <STM32_PINMUX('G', 9, AF12)>; /* FMC_NE2_FMC_NCE */ |
| 285 | bias-disable; |
| 286 | drive-push-pull; |
| 287 | slew-rate = <1>; |
| 288 | }; |
| 289 | pins2 { |
| 290 | pinmux = <STM32_PINMUX('D', 6, AF12)>; /* FMC_NWAIT */ |
| 291 | bias-pull-up; |
| 292 | }; |
| 293 | }; |
| 294 | |
| 295 | fmc_sleep_pins_a: fmc-sleep-0 { |
| 296 | pins { |
| 297 | pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */ |
| 298 | <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */ |
| 299 | <STM32_PINMUX('D', 11, ANALOG)>, /* FMC_A16_FMC_CLE */ |
| 300 | <STM32_PINMUX('D', 12, ANALOG)>, /* FMC_A17_FMC_ALE */ |
| 301 | <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */ |
| 302 | <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */ |
| 303 | <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */ |
| 304 | <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */ |
| 305 | <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */ |
| 306 | <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */ |
| 307 | <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */ |
| 308 | <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */ |
| 309 | <STM32_PINMUX('D', 6, ANALOG)>, /* FMC_NWAIT */ |
| 310 | <STM32_PINMUX('G', 9, ANALOG)>; /* FMC_NE2_FMC_NCE */ |
| 311 | }; |
| 312 | }; |
| 313 | |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 314 | i2c1_pins_a: i2c1-0 { |
| 315 | pins { |
| 316 | pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */ |
| 317 | <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */ |
| 318 | bias-disable; |
| 319 | drive-open-drain; |
| 320 | slew-rate = <0>; |
| 321 | }; |
| 322 | }; |
| 323 | |
Patrick Delaunay | a370530 | 2019-07-11 11:15:28 +0200 | [diff] [blame] | 324 | i2c1_pins_sleep_a: i2c1-1 { |
| 325 | pins { |
| 326 | pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */ |
| 327 | <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */ |
| 328 | }; |
| 329 | }; |
| 330 | |
| 331 | i2c1_pins_b: i2c1-2 { |
Manivannan Sadhasivam | c70ef69 | 2019-05-02 13:26:43 +0530 | [diff] [blame] | 332 | pins { |
| 333 | pinmux = <STM32_PINMUX('F', 14, AF5)>, /* I2C1_SCL */ |
| 334 | <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */ |
| 335 | bias-disable; |
| 336 | drive-open-drain; |
| 337 | slew-rate = <0>; |
| 338 | }; |
| 339 | }; |
| 340 | |
Patrick Delaunay | 708cae7 | 2019-07-30 19:16:12 +0200 | [diff] [blame] | 341 | i2c1_pins_sleep_b: i2c1-3 { |
| 342 | pins { |
| 343 | pinmux = <STM32_PINMUX('F', 14, ANALOG)>, /* I2C1_SCL */ |
| 344 | <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */ |
| 345 | }; |
| 346 | }; |
| 347 | |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 348 | i2c2_pins_a: i2c2-0 { |
| 349 | pins { |
| 350 | pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */ |
| 351 | <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */ |
| 352 | bias-disable; |
| 353 | drive-open-drain; |
| 354 | slew-rate = <0>; |
| 355 | }; |
| 356 | }; |
| 357 | |
Patrick Delaunay | a370530 | 2019-07-11 11:15:28 +0200 | [diff] [blame] | 358 | i2c2_pins_sleep_a: i2c2-1 { |
| 359 | pins { |
| 360 | pinmux = <STM32_PINMUX('H', 4, ANALOG)>, /* I2C2_SCL */ |
| 361 | <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */ |
| 362 | }; |
| 363 | }; |
| 364 | |
Patrick Delaunay | 708cae7 | 2019-07-30 19:16:12 +0200 | [diff] [blame] | 365 | i2c2_pins_b1: i2c2-2 { |
Manivannan Sadhasivam | c70ef69 | 2019-05-02 13:26:43 +0530 | [diff] [blame] | 366 | pins { |
Patrick Delaunay | 708cae7 | 2019-07-30 19:16:12 +0200 | [diff] [blame] | 367 | pinmux = <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */ |
Manivannan Sadhasivam | c70ef69 | 2019-05-02 13:26:43 +0530 | [diff] [blame] | 368 | bias-disable; |
| 369 | drive-open-drain; |
| 370 | slew-rate = <0>; |
| 371 | }; |
| 372 | }; |
| 373 | |
Patrick Delaunay | 708cae7 | 2019-07-30 19:16:12 +0200 | [diff] [blame] | 374 | i2c2_pins_sleep_b1: i2c2-3 { |
| 375 | pins { |
| 376 | pinmux = <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */ |
| 377 | }; |
| 378 | }; |
| 379 | |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 380 | i2c5_pins_a: i2c5-0 { |
| 381 | pins { |
| 382 | pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */ |
| 383 | <STM32_PINMUX('A', 12, AF4)>; /* I2C5_SDA */ |
| 384 | bias-disable; |
| 385 | drive-open-drain; |
| 386 | slew-rate = <0>; |
| 387 | }; |
| 388 | }; |
| 389 | |
Patrick Delaunay | a370530 | 2019-07-11 11:15:28 +0200 | [diff] [blame] | 390 | i2c5_pins_sleep_a: i2c5-1 { |
| 391 | pins { |
| 392 | pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* I2C5_SCL */ |
| 393 | <STM32_PINMUX('A', 12, ANALOG)>; /* I2C5_SDA */ |
| 394 | |
| 395 | }; |
| 396 | }; |
| 397 | |
Patrick Delaunay | 708cae7 | 2019-07-30 19:16:12 +0200 | [diff] [blame] | 398 | i2s2_pins_a: i2s2-0 { |
| 399 | pins { |
| 400 | pinmux = <STM32_PINMUX('I', 3, AF5)>, /* I2S2_SDO */ |
| 401 | <STM32_PINMUX('B', 9, AF5)>, /* I2S2_WS */ |
| 402 | <STM32_PINMUX('A', 9, AF5)>; /* I2S2_CK */ |
| 403 | slew-rate = <1>; |
| 404 | drive-push-pull; |
| 405 | bias-disable; |
| 406 | }; |
| 407 | }; |
| 408 | |
| 409 | i2s2_pins_sleep_a: i2s2-1 { |
| 410 | pins { |
| 411 | pinmux = <STM32_PINMUX('I', 3, ANALOG)>, /* I2S2_SDO */ |
| 412 | <STM32_PINMUX('B', 9, ANALOG)>, /* I2S2_WS */ |
| 413 | <STM32_PINMUX('A', 9, ANALOG)>; /* I2S2_CK */ |
| 414 | }; |
| 415 | }; |
| 416 | |
Patrick Delaunay | a370530 | 2019-07-11 11:15:28 +0200 | [diff] [blame] | 417 | ltdc_pins_a: ltdc-a-0 { |
| 418 | pins { |
| 419 | pinmux = <STM32_PINMUX('G', 7, AF14)>, /* LCD_CLK */ |
| 420 | <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */ |
| 421 | <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */ |
| 422 | <STM32_PINMUX('F', 10, AF14)>, /* LCD_DE */ |
| 423 | <STM32_PINMUX('H', 2, AF14)>, /* LCD_R0 */ |
| 424 | <STM32_PINMUX('H', 3, AF14)>, /* LCD_R1 */ |
| 425 | <STM32_PINMUX('H', 8, AF14)>, /* LCD_R2 */ |
| 426 | <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */ |
| 427 | <STM32_PINMUX('H', 10, AF14)>, /* LCD_R4 */ |
| 428 | <STM32_PINMUX('C', 0, AF14)>, /* LCD_R5 */ |
| 429 | <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */ |
| 430 | <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */ |
| 431 | <STM32_PINMUX('E', 5, AF14)>, /* LCD_G0 */ |
| 432 | <STM32_PINMUX('E', 6, AF14)>, /* LCD_G1 */ |
| 433 | <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */ |
| 434 | <STM32_PINMUX('H', 14, AF14)>, /* LCD_G3 */ |
| 435 | <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */ |
| 436 | <STM32_PINMUX('I', 0, AF14)>, /* LCD_G5 */ |
| 437 | <STM32_PINMUX('I', 1, AF14)>, /* LCD_G6 */ |
| 438 | <STM32_PINMUX('I', 2, AF14)>, /* LCD_G7 */ |
| 439 | <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */ |
| 440 | <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */ |
| 441 | <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */ |
| 442 | <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */ |
| 443 | <STM32_PINMUX('I', 4, AF14)>, /* LCD_B4 */ |
| 444 | <STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */ |
| 445 | <STM32_PINMUX('B', 8, AF14)>, /* LCD_B6 */ |
| 446 | <STM32_PINMUX('D', 8, AF14)>; /* LCD_B7 */ |
| 447 | bias-disable; |
| 448 | drive-push-pull; |
| 449 | slew-rate = <1>; |
| 450 | }; |
| 451 | }; |
| 452 | |
| 453 | ltdc_pins_sleep_a: ltdc-a-1 { |
| 454 | pins { |
| 455 | pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */ |
| 456 | <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */ |
| 457 | <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */ |
| 458 | <STM32_PINMUX('F', 10, ANALOG)>, /* LCD_DE */ |
| 459 | <STM32_PINMUX('H', 2, ANALOG)>, /* LCD_R0 */ |
| 460 | <STM32_PINMUX('H', 3, ANALOG)>, /* LCD_R1 */ |
| 461 | <STM32_PINMUX('H', 8, ANALOG)>, /* LCD_R2 */ |
| 462 | <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */ |
| 463 | <STM32_PINMUX('H', 10, ANALOG)>, /* LCD_R4 */ |
| 464 | <STM32_PINMUX('C', 0, ANALOG)>, /* LCD_R5 */ |
| 465 | <STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */ |
| 466 | <STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */ |
| 467 | <STM32_PINMUX('E', 5, ANALOG)>, /* LCD_G0 */ |
| 468 | <STM32_PINMUX('E', 6, ANALOG)>, /* LCD_G1 */ |
| 469 | <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */ |
| 470 | <STM32_PINMUX('H', 14, ANALOG)>, /* LCD_G3 */ |
| 471 | <STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */ |
| 472 | <STM32_PINMUX('I', 0, ANALOG)>, /* LCD_G5 */ |
| 473 | <STM32_PINMUX('I', 1, ANALOG)>, /* LCD_G6 */ |
| 474 | <STM32_PINMUX('I', 2, ANALOG)>, /* LCD_G7 */ |
| 475 | <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */ |
| 476 | <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */ |
| 477 | <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */ |
| 478 | <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */ |
| 479 | <STM32_PINMUX('I', 4, ANALOG)>, /* LCD_B4 */ |
| 480 | <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */ |
| 481 | <STM32_PINMUX('B', 8, ANALOG)>, /* LCD_B6 */ |
| 482 | <STM32_PINMUX('D', 8, ANALOG)>; /* LCD_B7 */ |
| 483 | }; |
| 484 | }; |
| 485 | |
| 486 | ltdc_pins_b: ltdc-b-0 { |
| 487 | pins { |
| 488 | pinmux = <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */ |
| 489 | <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */ |
| 490 | <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */ |
| 491 | <STM32_PINMUX('K', 7, AF14)>, /* LCD_DE */ |
| 492 | <STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */ |
| 493 | <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */ |
| 494 | <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */ |
| 495 | <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */ |
| 496 | <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */ |
| 497 | <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */ |
| 498 | <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6 */ |
| 499 | <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */ |
| 500 | <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */ |
| 501 | <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */ |
| 502 | <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */ |
| 503 | <STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */ |
| 504 | <STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */ |
| 505 | <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */ |
| 506 | <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */ |
| 507 | <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */ |
| 508 | <STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */ |
| 509 | <STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */ |
| 510 | <STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */ |
| 511 | <STM32_PINMUX('J', 15, AF14)>, /* LCD_B3 */ |
| 512 | <STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */ |
| 513 | <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */ |
| 514 | <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */ |
| 515 | <STM32_PINMUX('K', 6, AF14)>; /* LCD_B7 */ |
| 516 | bias-disable; |
| 517 | drive-push-pull; |
| 518 | slew-rate = <1>; |
| 519 | }; |
| 520 | }; |
| 521 | |
| 522 | ltdc_pins_sleep_b: ltdc-b-1 { |
| 523 | pins { |
| 524 | pinmux = <STM32_PINMUX('I', 14, ANALOG)>, /* LCD_CLK */ |
| 525 | <STM32_PINMUX('I', 12, ANALOG)>, /* LCD_HSYNC */ |
| 526 | <STM32_PINMUX('I', 13, ANALOG)>, /* LCD_VSYNC */ |
| 527 | <STM32_PINMUX('K', 7, ANALOG)>, /* LCD_DE */ |
| 528 | <STM32_PINMUX('I', 15, ANALOG)>, /* LCD_R0 */ |
| 529 | <STM32_PINMUX('J', 0, ANALOG)>, /* LCD_R1 */ |
| 530 | <STM32_PINMUX('J', 1, ANALOG)>, /* LCD_R2 */ |
| 531 | <STM32_PINMUX('J', 2, ANALOG)>, /* LCD_R3 */ |
| 532 | <STM32_PINMUX('J', 3, ANALOG)>, /* LCD_R4 */ |
| 533 | <STM32_PINMUX('J', 4, ANALOG)>, /* LCD_R5 */ |
| 534 | <STM32_PINMUX('J', 5, ANALOG)>, /* LCD_R6 */ |
| 535 | <STM32_PINMUX('J', 6, ANALOG)>, /* LCD_R7 */ |
| 536 | <STM32_PINMUX('J', 7, ANALOG)>, /* LCD_G0 */ |
| 537 | <STM32_PINMUX('J', 8, ANALOG)>, /* LCD_G1 */ |
| 538 | <STM32_PINMUX('J', 9, ANALOG)>, /* LCD_G2 */ |
| 539 | <STM32_PINMUX('J', 10, ANALOG)>, /* LCD_G3 */ |
| 540 | <STM32_PINMUX('J', 11, ANALOG)>, /* LCD_G4 */ |
| 541 | <STM32_PINMUX('K', 0, ANALOG)>, /* LCD_G5 */ |
| 542 | <STM32_PINMUX('K', 1, ANALOG)>, /* LCD_G6 */ |
| 543 | <STM32_PINMUX('K', 2, ANALOG)>, /* LCD_G7 */ |
| 544 | <STM32_PINMUX('J', 12, ANALOG)>, /* LCD_B0 */ |
| 545 | <STM32_PINMUX('J', 13, ANALOG)>, /* LCD_B1 */ |
| 546 | <STM32_PINMUX('J', 14, ANALOG)>, /* LCD_B2 */ |
| 547 | <STM32_PINMUX('J', 15, ANALOG)>, /* LCD_B3 */ |
| 548 | <STM32_PINMUX('K', 3, ANALOG)>, /* LCD_B4 */ |
| 549 | <STM32_PINMUX('K', 4, ANALOG)>, /* LCD_B5 */ |
| 550 | <STM32_PINMUX('K', 5, ANALOG)>, /* LCD_B6 */ |
| 551 | <STM32_PINMUX('K', 6, ANALOG)>; /* LCD_B7 */ |
| 552 | }; |
| 553 | }; |
| 554 | |
Patrice Chotard | 00442d0 | 2019-02-12 16:50:38 +0100 | [diff] [blame] | 555 | m_can1_pins_a: m-can1-0 { |
| 556 | pins1 { |
| 557 | pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */ |
| 558 | slew-rate = <1>; |
| 559 | drive-push-pull; |
| 560 | bias-disable; |
| 561 | }; |
| 562 | pins2 { |
| 563 | pinmux = <STM32_PINMUX('I', 9, AF9)>; /* CAN1_RX */ |
| 564 | bias-disable; |
| 565 | }; |
| 566 | }; |
| 567 | |
Patrick Delaunay | a370530 | 2019-07-11 11:15:28 +0200 | [diff] [blame] | 568 | m_can1_sleep_pins_a: m_can1-sleep@0 { |
| 569 | pins { |
| 570 | pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */ |
| 571 | <STM32_PINMUX('I', 9, ANALOG)>; /* CAN1_RX */ |
| 572 | }; |
| 573 | }; |
| 574 | |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 575 | pwm2_pins_a: pwm2-0 { |
| 576 | pins { |
| 577 | pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */ |
| 578 | bias-pull-down; |
| 579 | drive-push-pull; |
| 580 | slew-rate = <0>; |
| 581 | }; |
| 582 | }; |
| 583 | |
| 584 | pwm8_pins_a: pwm8-0 { |
| 585 | pins { |
| 586 | pinmux = <STM32_PINMUX('I', 2, AF3)>; /* TIM8_CH4 */ |
| 587 | bias-pull-down; |
| 588 | drive-push-pull; |
| 589 | slew-rate = <0>; |
| 590 | }; |
| 591 | }; |
| 592 | |
| 593 | pwm12_pins_a: pwm12-0 { |
| 594 | pins { |
| 595 | pinmux = <STM32_PINMUX('H', 6, AF2)>; /* TIM12_CH1 */ |
| 596 | bias-pull-down; |
| 597 | drive-push-pull; |
| 598 | slew-rate = <0>; |
| 599 | }; |
| 600 | }; |
| 601 | |
| 602 | qspi_clk_pins_a: qspi-clk-0 { |
| 603 | pins { |
| 604 | pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */ |
| 605 | bias-disable; |
| 606 | drive-push-pull; |
| 607 | slew-rate = <3>; |
| 608 | }; |
| 609 | }; |
| 610 | |
Patrick Delaunay | 708cae7 | 2019-07-30 19:16:12 +0200 | [diff] [blame] | 611 | qspi_clk_sleep_pins_a: qspi-clk-sleep-0 { |
| 612 | pins { |
| 613 | pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */ |
| 614 | }; |
| 615 | }; |
| 616 | |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 617 | qspi_bk1_pins_a: qspi-bk1-0 { |
| 618 | pins1 { |
| 619 | pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */ |
| 620 | <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */ |
| 621 | <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */ |
| 622 | <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */ |
| 623 | bias-disable; |
| 624 | drive-push-pull; |
| 625 | slew-rate = <3>; |
| 626 | }; |
| 627 | pins2 { |
| 628 | pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */ |
| 629 | bias-pull-up; |
| 630 | drive-push-pull; |
| 631 | slew-rate = <3>; |
| 632 | }; |
| 633 | }; |
| 634 | |
Patrick Delaunay | 708cae7 | 2019-07-30 19:16:12 +0200 | [diff] [blame] | 635 | qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 { |
| 636 | pins { |
| 637 | pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */ |
| 638 | <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */ |
| 639 | <STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */ |
| 640 | <STM32_PINMUX('F', 6, ANALOG)>, /* QSPI_BK1_IO3 */ |
| 641 | <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */ |
| 642 | }; |
| 643 | }; |
| 644 | |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 645 | qspi_bk2_pins_a: qspi-bk2-0 { |
| 646 | pins1 { |
| 647 | pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */ |
| 648 | <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */ |
| 649 | <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */ |
| 650 | <STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */ |
| 651 | bias-disable; |
| 652 | drive-push-pull; |
| 653 | slew-rate = <3>; |
| 654 | }; |
| 655 | pins2 { |
| 656 | pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */ |
| 657 | bias-pull-up; |
| 658 | drive-push-pull; |
| 659 | slew-rate = <3>; |
| 660 | }; |
| 661 | }; |
Patrick Delaunay | a370530 | 2019-07-11 11:15:28 +0200 | [diff] [blame] | 662 | |
Patrick Delaunay | 708cae7 | 2019-07-30 19:16:12 +0200 | [diff] [blame] | 663 | qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 { |
| 664 | pins { |
| 665 | pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */ |
| 666 | <STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */ |
| 667 | <STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */ |
| 668 | <STM32_PINMUX('G', 7, ANALOG)>, /* QSPI_BK2_IO3 */ |
| 669 | <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */ |
| 670 | }; |
| 671 | }; |
| 672 | |
| 673 | sai2a_pins_a: sai2a-0 { |
| 674 | pins { |
| 675 | pinmux = <STM32_PINMUX('I', 5, AF10)>, /* SAI2_SCK_A */ |
| 676 | <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */ |
| 677 | <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */ |
| 678 | <STM32_PINMUX('E', 0, AF10)>; /* SAI2_MCLK_A */ |
| 679 | slew-rate = <0>; |
| 680 | drive-push-pull; |
| 681 | bias-disable; |
| 682 | }; |
| 683 | }; |
| 684 | |
| 685 | sai2a_sleep_pins_a: sai2a-1 { |
| 686 | pins { |
| 687 | pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* SAI2_SCK_A */ |
| 688 | <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */ |
| 689 | <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */ |
| 690 | <STM32_PINMUX('E', 0, ANALOG)>; /* SAI2_MCLK_A */ |
| 691 | }; |
| 692 | }; |
| 693 | |
| 694 | sai2b_pins_a: sai2b-0 { |
| 695 | pins1 { |
| 696 | pinmux = <STM32_PINMUX('E', 12, AF10)>, /* SAI2_SCK_B */ |
| 697 | <STM32_PINMUX('E', 13, AF10)>, /* SAI2_FS_B */ |
| 698 | <STM32_PINMUX('E', 14, AF10)>; /* SAI2_MCLK_B */ |
| 699 | slew-rate = <0>; |
| 700 | drive-push-pull; |
| 701 | bias-disable; |
| 702 | }; |
| 703 | pins2 { |
| 704 | pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */ |
| 705 | bias-disable; |
| 706 | }; |
| 707 | }; |
| 708 | |
| 709 | sai2b_sleep_pins_a: sai2b-1 { |
| 710 | pins { |
| 711 | pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* SAI2_SD_B */ |
| 712 | <STM32_PINMUX('E', 12, ANALOG)>, /* SAI2_SCK_B */ |
| 713 | <STM32_PINMUX('E', 13, ANALOG)>, /* SAI2_FS_B */ |
| 714 | <STM32_PINMUX('E', 14, ANALOG)>; /* SAI2_MCLK_B */ |
| 715 | }; |
| 716 | }; |
| 717 | |
| 718 | sai2b_pins_b: sai2b-2 { |
| 719 | pins { |
| 720 | pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */ |
| 721 | bias-disable; |
| 722 | }; |
| 723 | }; |
| 724 | |
| 725 | sai2b_sleep_pins_b: sai2b-3 { |
| 726 | pins { |
| 727 | pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */ |
| 728 | }; |
| 729 | }; |
| 730 | |
| 731 | sai4a_pins_a: sai4a-0 { |
| 732 | pins { |
| 733 | pinmux = <STM32_PINMUX('B', 5, AF10)>; /* SAI4_SD_A */ |
| 734 | slew-rate = <0>; |
| 735 | drive-push-pull; |
| 736 | bias-disable; |
| 737 | }; |
| 738 | }; |
| 739 | |
| 740 | sai4a_sleep_pins_a: sai4a-1 { |
| 741 | pins { |
| 742 | pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* SAI4_SD_A */ |
| 743 | }; |
| 744 | }; |
| 745 | |
Patrick Delaunay | a370530 | 2019-07-11 11:15:28 +0200 | [diff] [blame] | 746 | sdmmc1_b4_pins_a: sdmmc1-b4-0 { |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 747 | pins { |
| 748 | pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ |
| 749 | <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ |
| 750 | <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ |
| 751 | <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */ |
| 752 | <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */ |
| 753 | <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ |
| 754 | slew-rate = <3>; |
| 755 | drive-push-pull; |
| 756 | bias-disable; |
| 757 | }; |
Patrick Delaunay | a370530 | 2019-07-11 11:15:28 +0200 | [diff] [blame] | 758 | }; |
| 759 | |
| 760 | sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { |
| 761 | pins1 { |
| 762 | pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ |
| 763 | <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ |
| 764 | <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ |
| 765 | <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */ |
| 766 | <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */ |
| 767 | slew-rate = <3>; |
| 768 | drive-push-pull; |
| 769 | bias-disable; |
| 770 | }; |
| 771 | pins2{ |
| 772 | pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ |
| 773 | slew-rate = <3>; |
| 774 | drive-open-drain; |
| 775 | bias-disable; |
| 776 | }; |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 777 | }; |
| 778 | |
Patrick Delaunay | a370530 | 2019-07-11 11:15:28 +0200 | [diff] [blame] | 779 | sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 780 | pins { |
Patrick Delaunay | a370530 | 2019-07-11 11:15:28 +0200 | [diff] [blame] | 781 | pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */ |
| 782 | <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */ |
| 783 | <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */ |
| 784 | <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */ |
| 785 | <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */ |
| 786 | <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */ |
| 787 | }; |
| 788 | }; |
| 789 | |
| 790 | sdmmc1_dir_pins_a: sdmmc1-dir-0 { |
| 791 | pins1 { |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 792 | pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */ |
| 793 | <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */ |
Patrick Delaunay | a370530 | 2019-07-11 11:15:28 +0200 | [diff] [blame] | 794 | <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */ |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 795 | slew-rate = <3>; |
| 796 | drive-push-pull; |
| 797 | bias-pull-up; |
| 798 | }; |
Patrick Delaunay | a370530 | 2019-07-11 11:15:28 +0200 | [diff] [blame] | 799 | pins2{ |
| 800 | pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */ |
| 801 | bias-pull-up; |
| 802 | }; |
| 803 | }; |
| 804 | |
| 805 | sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 { |
| 806 | pins { |
| 807 | pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */ |
| 808 | <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */ |
| 809 | <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */ |
| 810 | <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */ |
| 811 | }; |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 812 | }; |
Patrick Delaunay | a370530 | 2019-07-11 11:15:28 +0200 | [diff] [blame] | 813 | |
| 814 | sdmmc2_b4_pins_a: sdmmc2-b4-0 { |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 815 | pins { |
| 816 | pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ |
| 817 | <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ |
| 818 | <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ |
| 819 | <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */ |
| 820 | <STM32_PINMUX('E', 3, AF9)>, /* SDMMC2_CK */ |
| 821 | <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ |
| 822 | slew-rate = <3>; |
| 823 | drive-push-pull; |
| 824 | bias-pull-up; |
| 825 | }; |
| 826 | }; |
| 827 | |
Patrick Delaunay | a370530 | 2019-07-11 11:15:28 +0200 | [diff] [blame] | 828 | sdmmc2_d47_pins_a: sdmmc2-d47-0 { |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 829 | pins { |
| 830 | pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ |
| 831 | <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ |
| 832 | <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */ |
| 833 | <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */ |
| 834 | slew-rate = <3>; |
| 835 | drive-push-pull; |
| 836 | bias-pull-up; |
| 837 | }; |
| 838 | }; |
| 839 | |
Patrick Delaunay | a370530 | 2019-07-11 11:15:28 +0200 | [diff] [blame] | 840 | spdifrx_pins_a: spdifrx-0 { |
| 841 | pins { |
| 842 | pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */ |
| 843 | bias-disable; |
| 844 | }; |
| 845 | }; |
| 846 | |
| 847 | spdifrx_sleep_pins_a: spdifrx-1 { |
| 848 | pins { |
| 849 | pinmux = <STM32_PINMUX('G', 12, ANALOG)>; /* SPDIF_IN1 */ |
| 850 | }; |
| 851 | }; |
| 852 | |
Manivannan Sadhasivam | c70ef69 | 2019-05-02 13:26:43 +0530 | [diff] [blame] | 853 | spi2_pins_a: spi2-0 { |
| 854 | pins1 { |
| 855 | pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI2_SCK */ |
| 856 | <STM32_PINMUX('I', 0, AF5)>, /* SPI2_NSS */ |
| 857 | <STM32_PINMUX('I', 3, AF5)>; /* SPI2_MOSI */ |
| 858 | bias-disable; |
| 859 | drive-push-pull; |
| 860 | slew-rate = <3>; |
| 861 | }; |
| 862 | pins2 { |
| 863 | pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI2_MISO */ |
| 864 | bias-disable; |
| 865 | }; |
| 866 | }; |
| 867 | |
Patrick Delaunay | 7f3384d | 2019-03-29 15:42:24 +0100 | [diff] [blame] | 868 | stusb1600_pins_a: stusb1600-0 { |
| 869 | pins { |
| 870 | pinmux = <STM32_PINMUX('I', 11, ANALOG)>; |
| 871 | bias-pull-up; |
| 872 | }; |
| 873 | }; |
| 874 | |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 875 | uart4_pins_a: uart4-0 { |
| 876 | pins1 { |
| 877 | pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */ |
| 878 | bias-disable; |
| 879 | drive-push-pull; |
| 880 | slew-rate = <0>; |
| 881 | }; |
| 882 | pins2 { |
| 883 | pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ |
| 884 | bias-disable; |
| 885 | }; |
| 886 | }; |
Patrice Chotard | 18cb6f5 | 2018-08-10 17:12:11 +0200 | [diff] [blame] | 887 | |
Manivannan Sadhasivam | c70ef69 | 2019-05-02 13:26:43 +0530 | [diff] [blame] | 888 | uart4_pins_b: uart4-1 { |
| 889 | pins1 { |
| 890 | pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */ |
| 891 | bias-disable; |
| 892 | drive-push-pull; |
| 893 | slew-rate = <0>; |
| 894 | }; |
| 895 | pins2 { |
| 896 | pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ |
| 897 | bias-disable; |
| 898 | }; |
| 899 | }; |
| 900 | |
| 901 | uart7_pins_a: uart7-0 { |
| 902 | pins1 { |
| 903 | pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART4_TX */ |
| 904 | bias-disable; |
| 905 | drive-push-pull; |
| 906 | slew-rate = <0>; |
| 907 | }; |
| 908 | pins2 { |
| 909 | pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART4_RX */ |
| 910 | <STM32_PINMUX('E', 10, AF7)>, /* UART4_CTS */ |
| 911 | <STM32_PINMUX('E', 9, AF7)>; /* UART4_RTS */ |
| 912 | bias-disable; |
| 913 | }; |
| 914 | }; |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 915 | }; |
| 916 | |
| 917 | pinctrl_z: pin-controller-z@54004000 { |
| 918 | #address-cells = <1>; |
| 919 | #size-cells = <1>; |
| 920 | compatible = "st,stm32mp157-z-pinctrl"; |
| 921 | ranges = <0 0x54004000 0x400>; |
| 922 | pins-are-numbered; |
| 923 | interrupt-parent = <&exti>; |
| 924 | st,syscfg = <&exti 0x60 0xff>; |
Patrick Delaunay | a370530 | 2019-07-11 11:15:28 +0200 | [diff] [blame] | 925 | hwlocks = <&hwspinlock 0>; |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 926 | |
| 927 | gpioz: gpio@54004000 { |
| 928 | gpio-controller; |
| 929 | #gpio-cells = <2>; |
| 930 | interrupt-controller; |
| 931 | #interrupt-cells = <2>; |
| 932 | reg = <0 0x400>; |
| 933 | clocks = <&rcc GPIOZ>; |
| 934 | st,bank-name = "GPIOZ"; |
| 935 | st,bank-ioport = <11>; |
Patrick Delaunay | 708cae7 | 2019-07-30 19:16:12 +0200 | [diff] [blame] | 936 | status = "disabled"; |
| 937 | }; |
| 938 | |
| 939 | i2c2_pins_b2: i2c2-0 { |
| 940 | pins { |
| 941 | pinmux = <STM32_PINMUX('Z', 0, AF3)>; /* I2C2_SCL */ |
| 942 | bias-disable; |
| 943 | drive-open-drain; |
| 944 | slew-rate = <0>; |
| 945 | }; |
| 946 | }; |
| 947 | |
| 948 | i2c2_pins_sleep_b2: i2c2-1 { |
| 949 | pins { |
| 950 | pinmux = <STM32_PINMUX('Z', 0, ANALOG)>; /* I2C2_SCL */ |
| 951 | }; |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 952 | }; |
| 953 | |
| 954 | i2c4_pins_a: i2c4-0 { |
| 955 | pins { |
| 956 | pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */ |
| 957 | <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */ |
| 958 | bias-disable; |
| 959 | drive-open-drain; |
| 960 | slew-rate = <0>; |
| 961 | }; |
| 962 | }; |
Patrice Chotard | 00442d0 | 2019-02-12 16:50:38 +0100 | [diff] [blame] | 963 | |
Patrick Delaunay | a370530 | 2019-07-11 11:15:28 +0200 | [diff] [blame] | 964 | i2c4_pins_sleep_a: i2c4-1 { |
| 965 | pins { |
| 966 | pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C4_SCL */ |
| 967 | <STM32_PINMUX('Z', 5, ANALOG)>; /* I2C4_SDA */ |
| 968 | }; |
| 969 | }; |
| 970 | |
Patrice Chotard | 00442d0 | 2019-02-12 16:50:38 +0100 | [diff] [blame] | 971 | spi1_pins_a: spi1-0 { |
| 972 | pins1 { |
| 973 | pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */ |
| 974 | <STM32_PINMUX('Z', 2, AF5)>; /* SPI1_MOSI */ |
| 975 | bias-disable; |
| 976 | drive-push-pull; |
| 977 | slew-rate = <1>; |
| 978 | }; |
| 979 | |
| 980 | pins2 { |
| 981 | pinmux = <STM32_PINMUX('Z', 1, AF5)>; /* SPI1_MISO */ |
| 982 | bias-disable; |
| 983 | }; |
| 984 | }; |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 985 | }; |
| 986 | }; |
| 987 | }; |