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git01.mediatek.com / filogic / uboot / e0188acfdf931b13ca1eb7457a38d9521c5d4a83 / . / arch / arm / dts / stm32mp157-pinctrl.dtsi
blob: b41c2b480da666cd793a731bc356c5d2f823f702 [file] [log] [blame]
Patrick Delaunay50599142018-07-09 15:17:19 +0200[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5 */
6#include <dt-bindings/pinctrl/stm32-pinfunc.h>
7
8/ {
9 soc {
10 pinctrl: pin-controller@50002000 {
11 #address-cells = <1>;
12 #size-cells = <1>;
13 compatible = "st,stm32mp157-pinctrl";
14 ranges = <0 0x50002000 0xa400>;
15 interrupt-parent = <&exti>;
16 st,syscfg = <&exti 0x60 0xff>;
17 pins-are-numbered;
18
19 gpioa: gpio@50002000 {
20 gpio-controller;
21 #gpio-cells = <2>;
22 interrupt-controller;
23 #interrupt-cells = <2>;
24 reg = <0x0 0x400>;
25 clocks = <&rcc GPIOA>;
26 st,bank-name = "GPIOA";
27 ngpios = <16>;
28 gpio-ranges = <&pinctrl 0 0 16>;
29 };
30
31 gpiob: gpio@50003000 {
32 gpio-controller;
33 #gpio-cells = <2>;
34 interrupt-controller;
35 #interrupt-cells = <2>;
36 reg = <0x1000 0x400>;
37 clocks = <&rcc GPIOB>;
38 st,bank-name = "GPIOB";
39 ngpios = <16>;
40 gpio-ranges = <&pinctrl 0 16 16>;
41 };
42
43 gpioc: gpio@50004000 {
44 gpio-controller;
45 #gpio-cells = <2>;
46 interrupt-controller;
47 #interrupt-cells = <2>;
48 reg = <0x2000 0x400>;
49 clocks = <&rcc GPIOC>;
50 st,bank-name = "GPIOC";
51 ngpios = <16>;
52 gpio-ranges = <&pinctrl 0 32 16>;
53 };
54
55 gpiod: gpio@50005000 {
56 gpio-controller;
57 #gpio-cells = <2>;
58 interrupt-controller;
59 #interrupt-cells = <2>;
60 reg = <0x3000 0x400>;
61 clocks = <&rcc GPIOD>;
62 st,bank-name = "GPIOD";
63 ngpios = <16>;
64 gpio-ranges = <&pinctrl 0 48 16>;
65 };
66
67 gpioe: gpio@50006000 {
68 gpio-controller;
69 #gpio-cells = <2>;
70 interrupt-controller;
71 #interrupt-cells = <2>;
72 reg = <0x4000 0x400>;
73 clocks = <&rcc GPIOE>;
74 st,bank-name = "GPIOE";
75 ngpios = <16>;
76 gpio-ranges = <&pinctrl 0 64 16>;
77 };
78
79 gpiof: gpio@50007000 {
80 gpio-controller;
81 #gpio-cells = <2>;
82 interrupt-controller;
83 #interrupt-cells = <2>;
84 reg = <0x5000 0x400>;
85 clocks = <&rcc GPIOF>;
86 st,bank-name = "GPIOF";
87 ngpios = <16>;
88 gpio-ranges = <&pinctrl 0 80 16>;
89 };
90
91 gpiog: gpio@50008000 {
92 gpio-controller;
93 #gpio-cells = <2>;
94 interrupt-controller;
95 #interrupt-cells = <2>;
96 reg = <0x6000 0x400>;
97 clocks = <&rcc GPIOG>;
98 st,bank-name = "GPIOG";
99 ngpios = <16>;
100 gpio-ranges = <&pinctrl 0 96 16>;
101 };
102
103 gpioh: gpio@50009000 {
104 gpio-controller;
105 #gpio-cells = <2>;
106 interrupt-controller;
107 #interrupt-cells = <2>;
108 reg = <0x7000 0x400>;
109 clocks = <&rcc GPIOH>;
110 st,bank-name = "GPIOH";
111 ngpios = <16>;
112 gpio-ranges = <&pinctrl 0 112 16>;
113 };
114
115 gpioi: gpio@5000a000 {
116 gpio-controller;
117 #gpio-cells = <2>;
118 interrupt-controller;
119 #interrupt-cells = <2>;
120 reg = <0x8000 0x400>;
121 clocks = <&rcc GPIOI>;
122 st,bank-name = "GPIOI";
123 ngpios = <16>;
124 gpio-ranges = <&pinctrl 0 128 16>;
125 };
126
127 gpioj: gpio@5000b000 {
128 gpio-controller;
129 #gpio-cells = <2>;
130 interrupt-controller;
131 #interrupt-cells = <2>;
132 reg = <0x9000 0x400>;
133 clocks = <&rcc GPIOJ>;
134 st,bank-name = "GPIOJ";
135 ngpios = <16>;
136 gpio-ranges = <&pinctrl 0 144 16>;
137 };
138
139 gpiok: gpio@5000c000 {
140 gpio-controller;
141 #gpio-cells = <2>;
142 interrupt-controller;
143 #interrupt-cells = <2>;
144 reg = <0xa000 0x400>;
145 clocks = <&rcc GPIOK>;
146 st,bank-name = "GPIOK";
147 ngpios = <8>;
148 gpio-ranges = <&pinctrl 0 160 8>;
149 };
150
Patrice Chotarde861c202019-02-12 16:50:41 +0100[diff] [blame]151 adc12_usb_pwr_pins_a: adc12-usb-pwr-pins-0 {
152 pins {
153 pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* ADC12 in18 */
154 <STM32_PINMUX('A', 5, ANALOG)>; /* ADC12 in19 */
155 };
156 };
157
Patrick Delaunay50599142018-07-09 15:17:19 +0200[diff] [blame]158 cec_pins_a: cec-0 {
159 pins {
160 pinmux = <STM32_PINMUX('A', 15, AF4)>;
161 bias-disable;
162 drive-open-drain;
163 slew-rate = <0>;
164 };
165 };
166
Patrice Chotard00442d02019-02-12 16:50:38 +0100[diff] [blame]167 ethernet0_rgmii_pins_a: rgmii-0 {
168 pins1 {
169 pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
170 <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
171 <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
172 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
173 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
174 <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
175 <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
176 <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
177 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
178 bias-disable;
179 drive-push-pull;
180 slew-rate = <3>;
181 };
182 pins2 {
183 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
184 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
185 <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */
186 <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
187 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
188 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
189 bias-disable;
190 };
191 };
192
193 ethernet0_rgmii_pins_sleep_a: rgmii-sleep-0 {
194 pins1 {
195 pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
196 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
197 <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
198 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
199 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
200 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
201 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
202 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
203 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
204 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
205 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
206 <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD2 */
207 <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
208 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
209 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
210 };
211 };
212
Patrick Delaunaye0188ac2019-04-08 15:30:52 +0200[diff] [blame^]213 fmc_pins_a: fmc-0 {
214 pins1 {
215 pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
216 <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
217 <STM32_PINMUX('D', 11, AF12)>, /* FMC_A16_FMC_CLE */
218 <STM32_PINMUX('D', 12, AF12)>, /* FMC_A17_FMC_ALE */
219 <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
220 <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
221 <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
222 <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
223 <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */
224 <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */
225 <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
226 <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */
227 <STM32_PINMUX('G', 9, AF12)>; /* FMC_NE2_FMC_NCE */
228 bias-disable;
229 drive-push-pull;
230 slew-rate = <1>;
231 };
232 pins2 {
233 pinmux = <STM32_PINMUX('D', 6, AF12)>; /* FMC_NWAIT */
234 bias-pull-up;
235 };
236 };
237
238 fmc_sleep_pins_a: fmc-sleep-0 {
239 pins {
240 pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */
241 <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */
242 <STM32_PINMUX('D', 11, ANALOG)>, /* FMC_A16_FMC_CLE */
243 <STM32_PINMUX('D', 12, ANALOG)>, /* FMC_A17_FMC_ALE */
244 <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */
245 <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */
246 <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */
247 <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */
248 <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */
249 <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */
250 <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */
251 <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */
252 <STM32_PINMUX('D', 6, ANALOG)>, /* FMC_NWAIT */
253 <STM32_PINMUX('G', 9, ANALOG)>; /* FMC_NE2_FMC_NCE */
254 };
255 };
256
Patrick Delaunay50599142018-07-09 15:17:19 +0200[diff] [blame]257 i2c1_pins_a: i2c1-0 {
258 pins {
259 pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
260 <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
261 bias-disable;
262 drive-open-drain;
263 slew-rate = <0>;
264 };
265 };
266
Manivannan Sadhasivamc70ef692019-05-02 13:26:43 +0530[diff] [blame]267 i2c1_pins_b: i2c1-1 {
268 pins {
269 pinmux = <STM32_PINMUX('F', 14, AF5)>, /* I2C1_SCL */
270 <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
271 bias-disable;
272 drive-open-drain;
273 slew-rate = <0>;
274 };
275 };
276
Patrick Delaunay50599142018-07-09 15:17:19 +0200[diff] [blame]277 i2c2_pins_a: i2c2-0 {
278 pins {
279 pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */
280 <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
281 bias-disable;
282 drive-open-drain;
283 slew-rate = <0>;
284 };
285 };
286
Manivannan Sadhasivamc70ef692019-05-02 13:26:43 +0530[diff] [blame]287 i2c2_pins_b: i2c2-1 {
288 pins {
289 pinmux = <STM32_PINMUX('Z', 0, AF3)>, /* I2C2_SCL */
290 <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
291 bias-disable;
292 drive-open-drain;
293 slew-rate = <0>;
294 };
295 };
296
Patrick Delaunay50599142018-07-09 15:17:19 +0200[diff] [blame]297 i2c5_pins_a: i2c5-0 {
298 pins {
299 pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */
300 <STM32_PINMUX('A', 12, AF4)>; /* I2C5_SDA */
301 bias-disable;
302 drive-open-drain;
303 slew-rate = <0>;
304 };
305 };
306
Patrice Chotard00442d02019-02-12 16:50:38 +0100[diff] [blame]307 m_can1_pins_a: m-can1-0 {
308 pins1 {
309 pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
310 slew-rate = <1>;
311 drive-push-pull;
312 bias-disable;
313 };
314 pins2 {
315 pinmux = <STM32_PINMUX('I', 9, AF9)>; /* CAN1_RX */
316 bias-disable;
317 };
318 };
319
Patrick Delaunay50599142018-07-09 15:17:19 +0200[diff] [blame]320 pwm2_pins_a: pwm2-0 {
321 pins {
322 pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
323 bias-pull-down;
324 drive-push-pull;
325 slew-rate = <0>;
326 };
327 };
328
329 pwm8_pins_a: pwm8-0 {
330 pins {
331 pinmux = <STM32_PINMUX('I', 2, AF3)>; /* TIM8_CH4 */
332 bias-pull-down;
333 drive-push-pull;
334 slew-rate = <0>;
335 };
336 };
337
338 pwm12_pins_a: pwm12-0 {
339 pins {
340 pinmux = <STM32_PINMUX('H', 6, AF2)>; /* TIM12_CH1 */
341 bias-pull-down;
342 drive-push-pull;
343 slew-rate = <0>;
344 };
345 };
346
347 qspi_clk_pins_a: qspi-clk-0 {
348 pins {
349 pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
350 bias-disable;
351 drive-push-pull;
352 slew-rate = <3>;
353 };
354 };
355
356 qspi_bk1_pins_a: qspi-bk1-0 {
357 pins1 {
358 pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
359 <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
360 <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
361 <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
362 bias-disable;
363 drive-push-pull;
364 slew-rate = <3>;
365 };
366 pins2 {
367 pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
368 bias-pull-up;
369 drive-push-pull;
370 slew-rate = <3>;
371 };
372 };
373
374 qspi_bk2_pins_a: qspi-bk2-0 {
375 pins1 {
376 pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
377 <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
378 <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
379 <STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
380 bias-disable;
381 drive-push-pull;
382 slew-rate = <3>;
383 };
384 pins2 {
385 pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
386 bias-pull-up;
387 drive-push-pull;
388 slew-rate = <3>;
389 };
390 };
391 sdmmc1_b4_pins_a: sdmmc1-b4@0 {
392 pins {
393 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
394 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
395 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
396 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
397 <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
398 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
399 slew-rate = <3>;
400 drive-push-pull;
401 bias-disable;
402 };
403 };
404
405 sdmmc1_dir_pins_a: sdmmc1-dir@0 {
406 pins {
407 pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
408 <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
409 <STM32_PINMUX('B', 9, AF11)>, /* SDMMC1_CDIR */
410 <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
411 slew-rate = <3>;
412 drive-push-pull;
413 bias-pull-up;
414 };
415 };
416 sdmmc2_b4_pins_a: sdmmc2-b4@0 {
417 pins {
418 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
419 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
420 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
421 <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
422 <STM32_PINMUX('E', 3, AF9)>, /* SDMMC2_CK */
423 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
424 slew-rate = <3>;
425 drive-push-pull;
426 bias-pull-up;
427 };
428 };
429
430 sdmmc2_d47_pins_a: sdmmc2-d47@0 {
431 pins {
432 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
433 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
434 <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
435 <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */
436 slew-rate = <3>;
437 drive-push-pull;
438 bias-pull-up;
439 };
440 };
441
Manivannan Sadhasivamc70ef692019-05-02 13:26:43 +0530[diff] [blame]442 spi2_pins_a: spi2-0 {
443 pins1 {
444 pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI2_SCK */
445 <STM32_PINMUX('I', 0, AF5)>, /* SPI2_NSS */
446 <STM32_PINMUX('I', 3, AF5)>; /* SPI2_MOSI */
447 bias-disable;
448 drive-push-pull;
449 slew-rate = <3>;
450 };
451 pins2 {
452 pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI2_MISO */
453 bias-disable;
454 };
455 };
456
Patrick Delaunay7f3384d2019-03-29 15:42:24 +0100[diff] [blame]457 stusb1600_pins_a: stusb1600-0 {
458 pins {
459 pinmux = <STM32_PINMUX('I', 11, ANALOG)>;
460 bias-pull-up;
461 };
462 };
463
Patrick Delaunay50599142018-07-09 15:17:19 +0200[diff] [blame]464 uart4_pins_a: uart4-0 {
465 pins1 {
466 pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
467 bias-disable;
468 drive-push-pull;
469 slew-rate = <0>;
470 };
471 pins2 {
472 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
473 bias-disable;
474 };
475 };
Patrice Chotard18cb6f52018-08-10 17:12:11 +0200[diff] [blame]476
Manivannan Sadhasivamc70ef692019-05-02 13:26:43 +0530[diff] [blame]477 uart4_pins_b: uart4-1 {
478 pins1 {
479 pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */
480 bias-disable;
481 drive-push-pull;
482 slew-rate = <0>;
483 };
484 pins2 {
485 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
486 bias-disable;
487 };
488 };
489
490 uart7_pins_a: uart7-0 {
491 pins1 {
492 pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART4_TX */
493 bias-disable;
494 drive-push-pull;
495 slew-rate = <0>;
496 };
497 pins2 {
498 pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART4_RX */
499 <STM32_PINMUX('E', 10, AF7)>, /* UART4_CTS */
500 <STM32_PINMUX('E', 9, AF7)>; /* UART4_RTS */
501 bias-disable;
502 };
503 };
504
Patrice Chotard18cb6f52018-08-10 17:12:11 +0200[diff] [blame]505 usbotg_hs_pins_a: usbotg_hs-0 {
506 pins {
507 pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */
508 };
509 };
Patrick Delaunay50599142018-07-09 15:17:19 +0200[diff] [blame]510 };
511
512 pinctrl_z: pin-controller-z@54004000 {
513 #address-cells = <1>;
514 #size-cells = <1>;
515 compatible = "st,stm32mp157-z-pinctrl";
516 ranges = <0 0x54004000 0x400>;
517 pins-are-numbered;
518 interrupt-parent = <&exti>;
519 st,syscfg = <&exti 0x60 0xff>;
520
521 gpioz: gpio@54004000 {
522 gpio-controller;
523 #gpio-cells = <2>;
524 interrupt-controller;
525 #interrupt-cells = <2>;
526 reg = <0 0x400>;
527 clocks = <&rcc GPIOZ>;
528 st,bank-name = "GPIOZ";
529 st,bank-ioport = <11>;
530 ngpios = <8>;
531 gpio-ranges = <&pinctrl_z 0 400 8>;
532 };
533
534 i2c4_pins_a: i2c4-0 {
535 pins {
536 pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
537 <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
538 bias-disable;
539 drive-open-drain;
540 slew-rate = <0>;
541 };
542 };
Patrice Chotard00442d02019-02-12 16:50:38 +0100[diff] [blame]543
544 spi1_pins_a: spi1-0 {
545 pins1 {
546 pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */
547 <STM32_PINMUX('Z', 2, AF5)>; /* SPI1_MOSI */
548 bias-disable;
549 drive-push-pull;
550 slew-rate = <1>;
551 };
552
553 pins2 {
554 pinmux = <STM32_PINMUX('Z', 1, AF5)>; /* SPI1_MISO */
555 bias-disable;
556 };
557 };
Patrick Delaunay50599142018-07-09 15:17:19 +0200[diff] [blame]558 };
559 };
560};