Jean-Christophe PLAGNIOL-VILLARD | 9053b5a | 2009-04-05 13:02:43 +0200 | [diff] [blame] | 1 | #ifndef __ASM_ARM_SYSTEM_H |
| 2 | #define __ASM_ARM_SYSTEM_H |
| 3 | |
Sergey Temerkhanov | 064949c | 2015-10-14 09:55:46 -0700 | [diff] [blame] | 4 | #include <common.h> |
| 5 | #include <linux/compiler.h> |
Tom Rini | 3b787ef | 2016-08-01 18:54:53 -0400 | [diff] [blame] | 6 | #include <asm/barriers.h> |
Sergey Temerkhanov | 064949c | 2015-10-14 09:55:46 -0700 | [diff] [blame] | 7 | |
David Feng | 85fd5f1 | 2013-12-14 11:47:35 +0800 | [diff] [blame] | 8 | #ifdef CONFIG_ARM64 |
| 9 | |
| 10 | /* |
| 11 | * SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions |
| 12 | */ |
| 13 | #define CR_M (1 << 0) /* MMU enable */ |
| 14 | #define CR_A (1 << 1) /* Alignment abort enable */ |
| 15 | #define CR_C (1 << 2) /* Dcache enable */ |
| 16 | #define CR_SA (1 << 3) /* Stack Alignment Check Enable */ |
| 17 | #define CR_I (1 << 12) /* Icache enable */ |
| 18 | #define CR_WXN (1 << 19) /* Write Permision Imply XN */ |
| 19 | #define CR_EE (1 << 25) /* Exception (Big) Endian */ |
| 20 | |
Alison Wang | 73818d5 | 2016-11-10 10:49:03 +0800 | [diff] [blame] | 21 | #define ES_TO_AARCH64 1 |
| 22 | #define ES_TO_AARCH32 0 |
| 23 | |
| 24 | /* |
| 25 | * SCR_EL3 bits definitions |
| 26 | */ |
| 27 | #define SCR_EL3_RW_AARCH64 (1 << 10) /* Next lower level is AArch64 */ |
| 28 | #define SCR_EL3_RW_AARCH32 (0 << 10) /* Lower lowers level are AArch32 */ |
| 29 | #define SCR_EL3_HCE_EN (1 << 8) /* Hypervisor Call enable */ |
| 30 | #define SCR_EL3_SMD_DIS (1 << 7) /* Secure Monitor Call disable */ |
| 31 | #define SCR_EL3_RES1 (3 << 4) /* Reserved, RES1 */ |
Chee Hong Ang | b07ac0c | 2018-08-20 10:57:34 -0700 | [diff] [blame] | 32 | #define SCR_EL3_EA_EN (1 << 3) /* External aborts taken to EL3 */ |
Alison Wang | 73818d5 | 2016-11-10 10:49:03 +0800 | [diff] [blame] | 33 | #define SCR_EL3_NS_EN (1 << 0) /* EL0 and EL1 in Non-scure state */ |
| 34 | |
| 35 | /* |
| 36 | * SPSR_EL3/SPSR_EL2 bits definitions |
| 37 | */ |
| 38 | #define SPSR_EL_END_LE (0 << 9) /* Exception Little-endian */ |
| 39 | #define SPSR_EL_DEBUG_MASK (1 << 9) /* Debug exception masked */ |
| 40 | #define SPSR_EL_ASYN_MASK (1 << 8) /* Asynchronous data abort masked */ |
| 41 | #define SPSR_EL_SERR_MASK (1 << 8) /* System Error exception masked */ |
| 42 | #define SPSR_EL_IRQ_MASK (1 << 7) /* IRQ exception masked */ |
| 43 | #define SPSR_EL_FIQ_MASK (1 << 6) /* FIQ exception masked */ |
| 44 | #define SPSR_EL_T_A32 (0 << 5) /* AArch32 instruction set A32 */ |
| 45 | #define SPSR_EL_M_AARCH64 (0 << 4) /* Exception taken from AArch64 */ |
| 46 | #define SPSR_EL_M_AARCH32 (1 << 4) /* Exception taken from AArch32 */ |
| 47 | #define SPSR_EL_M_SVC (0x3) /* Exception taken from SVC mode */ |
| 48 | #define SPSR_EL_M_HYP (0xa) /* Exception taken from HYP mode */ |
| 49 | #define SPSR_EL_M_EL1H (5) /* Exception taken from EL1h mode */ |
| 50 | #define SPSR_EL_M_EL2H (9) /* Exception taken from EL2h mode */ |
| 51 | |
| 52 | /* |
| 53 | * CPTR_EL2 bits definitions |
| 54 | */ |
| 55 | #define CPTR_EL2_RES1 (3 << 12 | 0x3ff) /* Reserved, RES1 */ |
| 56 | |
| 57 | /* |
| 58 | * SCTLR_EL2 bits definitions |
| 59 | */ |
| 60 | #define SCTLR_EL2_RES1 (3 << 28 | 3 << 22 | 1 << 18 | 1 << 16 |\ |
| 61 | 1 << 11 | 3 << 4) /* Reserved, RES1 */ |
| 62 | #define SCTLR_EL2_EE_LE (0 << 25) /* Exception Little-endian */ |
| 63 | #define SCTLR_EL2_WXN_DIS (0 << 19) /* Write permission is not XN */ |
| 64 | #define SCTLR_EL2_ICACHE_DIS (0 << 12) /* Instruction cache disabled */ |
| 65 | #define SCTLR_EL2_SA_DIS (0 << 3) /* Stack Alignment Check disabled */ |
| 66 | #define SCTLR_EL2_DCACHE_DIS (0 << 2) /* Data cache disabled */ |
| 67 | #define SCTLR_EL2_ALIGN_DIS (0 << 1) /* Alignment check disabled */ |
| 68 | #define SCTLR_EL2_MMU_DIS (0) /* MMU disabled */ |
| 69 | |
| 70 | /* |
| 71 | * CNTHCTL_EL2 bits definitions |
| 72 | */ |
| 73 | #define CNTHCTL_EL2_EL1PCEN_EN (1 << 1) /* Physical timer regs accessible */ |
| 74 | #define CNTHCTL_EL2_EL1PCTEN_EN (1 << 0) /* Physical counter accessible */ |
| 75 | |
| 76 | /* |
| 77 | * HCR_EL2 bits definitions |
| 78 | */ |
| 79 | #define HCR_EL2_RW_AARCH64 (1 << 31) /* EL1 is AArch64 */ |
| 80 | #define HCR_EL2_RW_AARCH32 (0 << 31) /* Lower levels are AArch32 */ |
| 81 | #define HCR_EL2_HCD_DIS (1 << 29) /* Hypervisor Call disabled */ |
| 82 | |
| 83 | /* |
| 84 | * CPACR_EL1 bits definitions |
| 85 | */ |
| 86 | #define CPACR_EL1_FPEN_EN (3 << 20) /* SIMD and FP instruction enabled */ |
| 87 | |
| 88 | /* |
| 89 | * SCTLR_EL1 bits definitions |
| 90 | */ |
| 91 | #define SCTLR_EL1_RES1 (3 << 28 | 3 << 22 | 1 << 20 |\ |
| 92 | 1 << 11) /* Reserved, RES1 */ |
| 93 | #define SCTLR_EL1_UCI_DIS (0 << 26) /* Cache instruction disabled */ |
| 94 | #define SCTLR_EL1_EE_LE (0 << 25) /* Exception Little-endian */ |
| 95 | #define SCTLR_EL1_WXN_DIS (0 << 19) /* Write permission is not XN */ |
| 96 | #define SCTLR_EL1_NTWE_DIS (0 << 18) /* WFE instruction disabled */ |
| 97 | #define SCTLR_EL1_NTWI_DIS (0 << 16) /* WFI instruction disabled */ |
| 98 | #define SCTLR_EL1_UCT_DIS (0 << 15) /* CTR_EL0 access disabled */ |
| 99 | #define SCTLR_EL1_DZE_DIS (0 << 14) /* DC ZVA instruction disabled */ |
| 100 | #define SCTLR_EL1_ICACHE_DIS (0 << 12) /* Instruction cache disabled */ |
| 101 | #define SCTLR_EL1_UMA_DIS (0 << 9) /* User Mask Access disabled */ |
| 102 | #define SCTLR_EL1_SED_EN (0 << 8) /* SETEND instruction enabled */ |
| 103 | #define SCTLR_EL1_ITD_EN (0 << 7) /* IT instruction enabled */ |
| 104 | #define SCTLR_EL1_CP15BEN_DIS (0 << 5) /* CP15 barrier operation disabled */ |
| 105 | #define SCTLR_EL1_SA0_DIS (0 << 4) /* Stack Alignment EL0 disabled */ |
| 106 | #define SCTLR_EL1_SA_DIS (0 << 3) /* Stack Alignment EL1 disabled */ |
| 107 | #define SCTLR_EL1_DCACHE_DIS (0 << 2) /* Data cache disabled */ |
| 108 | #define SCTLR_EL1_ALIGN_DIS (0 << 1) /* Alignment check disabled */ |
| 109 | #define SCTLR_EL1_MMU_DIS (0) /* MMU disabled */ |
| 110 | |
David Feng | 85fd5f1 | 2013-12-14 11:47:35 +0800 | [diff] [blame] | 111 | #ifndef __ASSEMBLY__ |
| 112 | |
Alexander Graf | e317fe8 | 2016-03-04 01:09:47 +0100 | [diff] [blame] | 113 | u64 get_page_table_size(void); |
| 114 | #define PGTABLE_SIZE get_page_table_size() |
Alexander Graf | ce0a64e | 2016-03-04 01:09:54 +0100 | [diff] [blame] | 115 | |
| 116 | /* 2MB granularity */ |
| 117 | #define MMU_SECTION_SHIFT 21 |
| 118 | #define MMU_SECTION_SIZE (1 << MMU_SECTION_SHIFT) |
Alexander Graf | e317fe8 | 2016-03-04 01:09:47 +0100 | [diff] [blame] | 119 | |
Alexander Graf | 188c8ff | 2016-03-16 15:41:20 +0100 | [diff] [blame] | 120 | /* These constants need to be synced to the MT_ types in asm/armv8/mmu.h */ |
Siva Durga Prasad Paladugu | ba2432a | 2015-06-26 18:05:07 +0530 | [diff] [blame] | 121 | enum dcache_option { |
Alexander Graf | 188c8ff | 2016-03-16 15:41:20 +0100 | [diff] [blame] | 122 | DCACHE_OFF = 0 << 2, |
| 123 | DCACHE_WRITETHROUGH = 3 << 2, |
| 124 | DCACHE_WRITEBACK = 4 << 2, |
| 125 | DCACHE_WRITEALLOC = 4 << 2, |
Siva Durga Prasad Paladugu | ba2432a | 2015-06-26 18:05:07 +0530 | [diff] [blame] | 126 | }; |
| 127 | |
David Feng | 85fd5f1 | 2013-12-14 11:47:35 +0800 | [diff] [blame] | 128 | #define wfi() \ |
| 129 | ({asm volatile( \ |
| 130 | "wfi" : : : "memory"); \ |
| 131 | }) |
| 132 | |
| 133 | static inline unsigned int current_el(void) |
| 134 | { |
| 135 | unsigned int el; |
| 136 | asm volatile("mrs %0, CurrentEL" : "=r" (el) : : "cc"); |
| 137 | return el >> 2; |
| 138 | } |
| 139 | |
| 140 | static inline unsigned int get_sctlr(void) |
| 141 | { |
| 142 | unsigned int el, val; |
| 143 | |
| 144 | el = current_el(); |
| 145 | if (el == 1) |
| 146 | asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc"); |
| 147 | else if (el == 2) |
| 148 | asm volatile("mrs %0, sctlr_el2" : "=r" (val) : : "cc"); |
| 149 | else |
| 150 | asm volatile("mrs %0, sctlr_el3" : "=r" (val) : : "cc"); |
| 151 | |
| 152 | return val; |
| 153 | } |
| 154 | |
| 155 | static inline void set_sctlr(unsigned int val) |
| 156 | { |
| 157 | unsigned int el; |
| 158 | |
| 159 | el = current_el(); |
| 160 | if (el == 1) |
| 161 | asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc"); |
| 162 | else if (el == 2) |
| 163 | asm volatile("msr sctlr_el2, %0" : : "r" (val) : "cc"); |
| 164 | else |
| 165 | asm volatile("msr sctlr_el3, %0" : : "r" (val) : "cc"); |
| 166 | |
| 167 | asm volatile("isb"); |
| 168 | } |
| 169 | |
Sergey Temerkhanov | 6774e4e | 2015-10-14 09:55:44 -0700 | [diff] [blame] | 170 | static inline unsigned long read_mpidr(void) |
| 171 | { |
| 172 | unsigned long val; |
| 173 | |
| 174 | asm volatile("mrs %0, mpidr_el1" : "=r" (val)); |
| 175 | |
| 176 | return val; |
| 177 | } |
| 178 | |
| 179 | #define BSP_COREID 0 |
| 180 | |
David Feng | 85fd5f1 | 2013-12-14 11:47:35 +0800 | [diff] [blame] | 181 | void __asm_flush_dcache_all(void); |
York Sun | ef04201 | 2014-02-26 13:26:04 -0800 | [diff] [blame] | 182 | void __asm_invalidate_dcache_all(void); |
David Feng | 85fd5f1 | 2013-12-14 11:47:35 +0800 | [diff] [blame] | 183 | void __asm_flush_dcache_range(u64 start, u64 end); |
Simon Glass | 4415c3b | 2017-04-05 17:53:18 -0600 | [diff] [blame] | 184 | |
| 185 | /** |
| 186 | * __asm_invalidate_dcache_range() - Invalidate a range of virtual addresses |
| 187 | * |
| 188 | * This performance an invalidate from @start to @end - 1. Both addresses |
| 189 | * should be cache-aligned, otherwise this function will align the start |
| 190 | * address and may continue past the end address. |
| 191 | * |
| 192 | * Data in the address range is evicted from the cache and is not written back |
| 193 | * to memory. |
| 194 | * |
| 195 | * @start: Start address to invalidate |
| 196 | * @end: End address to invalidate up to (exclusive) |
| 197 | */ |
| 198 | void __asm_invalidate_dcache_range(u64 start, u64 end); |
David Feng | 85fd5f1 | 2013-12-14 11:47:35 +0800 | [diff] [blame] | 199 | void __asm_invalidate_tlb_all(void); |
| 200 | void __asm_invalidate_icache_all(void); |
Stephen Warren | ddb0f63 | 2016-10-19 15:18:46 -0600 | [diff] [blame] | 201 | int __asm_invalidate_l3_dcache(void); |
| 202 | int __asm_flush_l3_dcache(void); |
| 203 | int __asm_invalidate_l3_icache(void); |
Alexander Graf | e317fe8 | 2016-03-04 01:09:47 +0100 | [diff] [blame] | 204 | void __asm_switch_ttbr(u64 new_ttbr); |
David Feng | 85fd5f1 | 2013-12-14 11:47:35 +0800 | [diff] [blame] | 205 | |
Alison Wang | 73818d5 | 2016-11-10 10:49:03 +0800 | [diff] [blame] | 206 | /* |
| 207 | * Switch from EL3 to EL2 for ARMv8 |
| 208 | * |
| 209 | * @args: For loading 64-bit OS, fdt address. |
| 210 | * For loading 32-bit OS, zero. |
| 211 | * @mach_nr: For loading 64-bit OS, zero. |
| 212 | * For loading 32-bit OS, machine nr |
| 213 | * @fdt_addr: For loading 64-bit OS, zero. |
| 214 | * For loading 32-bit OS, fdt address. |
Alison Wang | eb2088d | 2017-01-17 09:39:17 +0800 | [diff] [blame] | 215 | * @arg4: Input argument. |
Alison Wang | 73818d5 | 2016-11-10 10:49:03 +0800 | [diff] [blame] | 216 | * @entry_point: kernel entry point |
| 217 | * @es_flag: execution state flag, ES_TO_AARCH64 or ES_TO_AARCH32 |
| 218 | */ |
York Sun | ffea3e6 | 2017-09-28 08:42:14 -0700 | [diff] [blame] | 219 | void __noreturn armv8_switch_to_el2(u64 args, u64 mach_nr, u64 fdt_addr, |
| 220 | u64 arg4, u64 entry_point, u64 es_flag); |
Alison Wang | 73818d5 | 2016-11-10 10:49:03 +0800 | [diff] [blame] | 221 | /* |
| 222 | * Switch from EL2 to EL1 for ARMv8 |
| 223 | * |
| 224 | * @args: For loading 64-bit OS, fdt address. |
| 225 | * For loading 32-bit OS, zero. |
| 226 | * @mach_nr: For loading 64-bit OS, zero. |
| 227 | * For loading 32-bit OS, machine nr |
| 228 | * @fdt_addr: For loading 64-bit OS, zero. |
| 229 | * For loading 32-bit OS, fdt address. |
Alison Wang | eb2088d | 2017-01-17 09:39:17 +0800 | [diff] [blame] | 230 | * @arg4: Input argument. |
Alison Wang | 73818d5 | 2016-11-10 10:49:03 +0800 | [diff] [blame] | 231 | * @entry_point: kernel entry point |
| 232 | * @es_flag: execution state flag, ES_TO_AARCH64 or ES_TO_AARCH32 |
| 233 | */ |
| 234 | void armv8_switch_to_el1(u64 args, u64 mach_nr, u64 fdt_addr, |
Alison Wang | eb2088d | 2017-01-17 09:39:17 +0800 | [diff] [blame] | 235 | u64 arg4, u64 entry_point, u64 es_flag); |
Alison Wang | f547fca | 2016-11-10 10:49:05 +0800 | [diff] [blame] | 236 | void armv8_el2_to_aarch32(u64 args, u64 mach_nr, u64 fdt_addr, |
Alison Wang | eb2088d | 2017-01-17 09:39:17 +0800 | [diff] [blame] | 237 | u64 arg4, u64 entry_point); |
David Feng | 85fd5f1 | 2013-12-14 11:47:35 +0800 | [diff] [blame] | 238 | void gic_init(void); |
| 239 | void gic_send_sgi(unsigned long sgino); |
| 240 | void wait_for_wakeup(void); |
Ian Campbell | d07e7b0 | 2015-04-21 07:18:36 +0200 | [diff] [blame] | 241 | void protect_secure_region(void); |
David Feng | 85fd5f1 | 2013-12-14 11:47:35 +0800 | [diff] [blame] | 242 | void smp_kick_all_cpus(void); |
| 243 | |
York Sun | a84cd72 | 2014-06-23 15:15:54 -0700 | [diff] [blame] | 244 | void flush_l3_cache(void); |
York Sun | 5bb14e0 | 2017-03-06 09:02:33 -0800 | [diff] [blame] | 245 | void mmu_change_region_attr(phys_addr_t start, size_t size, u64 attrs); |
York Sun | a84cd72 | 2014-06-23 15:15:54 -0700 | [diff] [blame] | 246 | |
Sergey Temerkhanov | 064949c | 2015-10-14 09:55:46 -0700 | [diff] [blame] | 247 | /* |
Sergey Temerkhanov | 064949c | 2015-10-14 09:55:46 -0700 | [diff] [blame] | 248 | *Issue a secure monitor call in accordance with ARM "SMC Calling convention", |
| 249 | * DEN0028A |
| 250 | * |
| 251 | * @args: input and output arguments |
| 252 | * |
| 253 | */ |
| 254 | void smc_call(struct pt_regs *args); |
| 255 | |
Alexander Graf | a5b1832 | 2016-08-16 21:08:46 +0200 | [diff] [blame] | 256 | void __noreturn psci_system_reset(void); |
Alexander Graf | 467c83e | 2016-08-16 21:08:47 +0200 | [diff] [blame] | 257 | void __noreturn psci_system_off(void); |
Beniamino Galvani | b8845e1 | 2016-05-08 08:30:14 +0200 | [diff] [blame] | 258 | |
macro.wave.z@gmail.com | 05725ed | 2016-12-08 11:58:25 +0800 | [diff] [blame] | 259 | #ifdef CONFIG_ARMV8_PSCI |
| 260 | extern char __secure_start[]; |
| 261 | extern char __secure_end[]; |
| 262 | extern char __secure_stack_start[]; |
| 263 | extern char __secure_stack_end[]; |
| 264 | |
| 265 | void armv8_setup_psci(void); |
| 266 | void psci_setup_vectors(void); |
| 267 | void psci_arch_init(void); |
| 268 | #endif |
| 269 | |
David Feng | 85fd5f1 | 2013-12-14 11:47:35 +0800 | [diff] [blame] | 270 | #endif /* __ASSEMBLY__ */ |
| 271 | |
| 272 | #else /* CONFIG_ARM64 */ |
| 273 | |
Jean-Christophe PLAGNIOL-VILLARD | 9053b5a | 2009-04-05 13:02:43 +0200 | [diff] [blame] | 274 | #ifdef __KERNEL__ |
| 275 | |
| 276 | #define CPU_ARCH_UNKNOWN 0 |
| 277 | #define CPU_ARCH_ARMv3 1 |
| 278 | #define CPU_ARCH_ARMv4 2 |
| 279 | #define CPU_ARCH_ARMv4T 3 |
| 280 | #define CPU_ARCH_ARMv5 4 |
| 281 | #define CPU_ARCH_ARMv5T 5 |
| 282 | #define CPU_ARCH_ARMv5TE 6 |
| 283 | #define CPU_ARCH_ARMv5TEJ 7 |
| 284 | #define CPU_ARCH_ARMv6 8 |
| 285 | #define CPU_ARCH_ARMv7 9 |
| 286 | |
| 287 | /* |
| 288 | * CR1 bits (CP#15 CR1) |
| 289 | */ |
| 290 | #define CR_M (1 << 0) /* MMU enable */ |
| 291 | #define CR_A (1 << 1) /* Alignment abort enable */ |
| 292 | #define CR_C (1 << 2) /* Dcache enable */ |
| 293 | #define CR_W (1 << 3) /* Write buffer enable */ |
| 294 | #define CR_P (1 << 4) /* 32-bit exception handler */ |
| 295 | #define CR_D (1 << 5) /* 32-bit data address range */ |
| 296 | #define CR_L (1 << 6) /* Implementation defined */ |
| 297 | #define CR_B (1 << 7) /* Big endian */ |
| 298 | #define CR_S (1 << 8) /* System MMU protection */ |
| 299 | #define CR_R (1 << 9) /* ROM MMU protection */ |
| 300 | #define CR_F (1 << 10) /* Implementation defined */ |
| 301 | #define CR_Z (1 << 11) /* Implementation defined */ |
| 302 | #define CR_I (1 << 12) /* Icache enable */ |
| 303 | #define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */ |
| 304 | #define CR_RR (1 << 14) /* Round Robin cache replacement */ |
| 305 | #define CR_L4 (1 << 15) /* LDR pc can set T bit */ |
| 306 | #define CR_DT (1 << 16) |
| 307 | #define CR_IT (1 << 18) |
| 308 | #define CR_ST (1 << 19) |
| 309 | #define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */ |
| 310 | #define CR_U (1 << 22) /* Unaligned access operation */ |
| 311 | #define CR_XP (1 << 23) /* Extended page tables */ |
| 312 | #define CR_VE (1 << 24) /* Vectored interrupts */ |
| 313 | #define CR_EE (1 << 25) /* Exception (Big) Endian */ |
| 314 | #define CR_TRE (1 << 28) /* TEX remap enable */ |
| 315 | #define CR_AFE (1 << 29) /* Access flag enable */ |
| 316 | #define CR_TE (1 << 30) /* Thumb exception enable */ |
| 317 | |
Alexander Graf | ae6c2bc | 2016-03-16 15:41:21 +0100 | [diff] [blame] | 318 | #if defined(CONFIG_ARMV7_LPAE) && !defined(PGTABLE_SIZE) |
| 319 | #define PGTABLE_SIZE (4096 * 5) |
| 320 | #elif !defined(PGTABLE_SIZE) |
David Feng | 85fd5f1 | 2013-12-14 11:47:35 +0800 | [diff] [blame] | 321 | #define PGTABLE_SIZE (4096 * 4) |
Sergey Temerkhanov | 78eaa49 | 2015-10-14 09:55:45 -0700 | [diff] [blame] | 322 | #endif |
David Feng | 85fd5f1 | 2013-12-14 11:47:35 +0800 | [diff] [blame] | 323 | |
Jean-Christophe PLAGNIOL-VILLARD | 9053b5a | 2009-04-05 13:02:43 +0200 | [diff] [blame] | 324 | /* |
| 325 | * This is used to ensure the compiler did actually allocate the register we |
| 326 | * asked it for some inline assembly sequences. Apparently we can't trust |
| 327 | * the compiler from one version to another so a bit of paranoia won't hurt. |
| 328 | * This string is meant to be concatenated with the inline asm string and |
| 329 | * will cause compilation to stop on mismatch. |
| 330 | * (for details, see gcc PR 15089) |
| 331 | */ |
| 332 | #define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t" |
| 333 | |
| 334 | #ifndef __ASSEMBLY__ |
| 335 | |
Keerthy | 61488c1 | 2016-09-14 10:43:32 +0530 | [diff] [blame] | 336 | #ifdef CONFIG_ARMV7_LPAE |
| 337 | void switch_to_hypervisor_ret(void); |
| 338 | #endif |
| 339 | |
Jean-Christophe PLAGNIOL-VILLARD | 9053b5a | 2009-04-05 13:02:43 +0200 | [diff] [blame] | 340 | #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t"); |
| 341 | |
Rob Herring | aa47030 | 2012-12-02 17:06:21 +0000 | [diff] [blame] | 342 | #ifdef __ARM_ARCH_7A__ |
| 343 | #define wfi() __asm__ __volatile__ ("wfi" : : : "memory") |
| 344 | #else |
| 345 | #define wfi() |
| 346 | #endif |
| 347 | |
Alexander Graf | ae6c2bc | 2016-03-16 15:41:21 +0100 | [diff] [blame] | 348 | static inline unsigned long get_cpsr(void) |
| 349 | { |
| 350 | unsigned long cpsr; |
| 351 | |
| 352 | asm volatile("mrs %0, cpsr" : "=r"(cpsr): ); |
| 353 | return cpsr; |
| 354 | } |
| 355 | |
| 356 | static inline int is_hyp(void) |
| 357 | { |
| 358 | #ifdef CONFIG_ARMV7_LPAE |
| 359 | /* HYP mode requires LPAE ... */ |
| 360 | return ((get_cpsr() & 0x1f) == 0x1a); |
| 361 | #else |
| 362 | /* ... so without LPAE support we can optimize all hyp code away */ |
| 363 | return 0; |
| 364 | #endif |
| 365 | } |
| 366 | |
Jean-Christophe PLAGNIOL-VILLARD | 9053b5a | 2009-04-05 13:02:43 +0200 | [diff] [blame] | 367 | static inline unsigned int get_cr(void) |
| 368 | { |
| 369 | unsigned int val; |
Alexander Graf | ae6c2bc | 2016-03-16 15:41:21 +0100 | [diff] [blame] | 370 | |
| 371 | if (is_hyp()) |
| 372 | asm volatile("mrc p15, 4, %0, c1, c0, 0 @ get CR" : "=r" (val) |
| 373 | : |
| 374 | : "cc"); |
| 375 | else |
| 376 | asm volatile("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) |
| 377 | : |
| 378 | : "cc"); |
Jean-Christophe PLAGNIOL-VILLARD | 9053b5a | 2009-04-05 13:02:43 +0200 | [diff] [blame] | 379 | return val; |
| 380 | } |
| 381 | |
| 382 | static inline void set_cr(unsigned int val) |
| 383 | { |
Alexander Graf | ae6c2bc | 2016-03-16 15:41:21 +0100 | [diff] [blame] | 384 | if (is_hyp()) |
| 385 | asm volatile("mcr p15, 4, %0, c1, c0, 0 @ set CR" : |
| 386 | : "r" (val) |
| 387 | : "cc"); |
| 388 | else |
| 389 | asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR" : |
| 390 | : "r" (val) |
| 391 | : "cc"); |
Jean-Christophe PLAGNIOL-VILLARD | 9053b5a | 2009-04-05 13:02:43 +0200 | [diff] [blame] | 392 | isb(); |
| 393 | } |
| 394 | |
R Sricharan | 06396c1 | 2013-03-04 20:04:45 +0000 | [diff] [blame] | 395 | static inline unsigned int get_dacr(void) |
| 396 | { |
| 397 | unsigned int val; |
| 398 | asm("mrc p15, 0, %0, c3, c0, 0 @ get DACR" : "=r" (val) : : "cc"); |
| 399 | return val; |
| 400 | } |
| 401 | |
| 402 | static inline void set_dacr(unsigned int val) |
| 403 | { |
| 404 | asm volatile("mcr p15, 0, %0, c3, c0, 0 @ set DACR" |
| 405 | : : "r" (val) : "cc"); |
| 406 | isb(); |
| 407 | } |
| 408 | |
Alexander Graf | ae6c2bc | 2016-03-16 15:41:21 +0100 | [diff] [blame] | 409 | #ifdef CONFIG_ARMV7_LPAE |
| 410 | /* Long-Descriptor Translation Table Level 1/2 Bits */ |
| 411 | #define TTB_SECT_XN_MASK (1ULL << 54) |
| 412 | #define TTB_SECT_NG_MASK (1 << 11) |
| 413 | #define TTB_SECT_AF (1 << 10) |
| 414 | #define TTB_SECT_SH_MASK (3 << 8) |
| 415 | #define TTB_SECT_NS_MASK (1 << 5) |
| 416 | #define TTB_SECT_AP (1 << 6) |
| 417 | /* Note: TTB AP bits are set elsewhere */ |
| 418 | #define TTB_SECT_MAIR(x) ((x & 0x7) << 2) /* Index into MAIR */ |
| 419 | #define TTB_SECT (1 << 0) |
| 420 | #define TTB_PAGETABLE (3 << 0) |
| 421 | |
| 422 | /* TTBCR flags */ |
| 423 | #define TTBCR_EAE (1 << 31) |
| 424 | #define TTBCR_T0SZ(x) ((x) << 0) |
| 425 | #define TTBCR_T1SZ(x) ((x) << 16) |
| 426 | #define TTBCR_USING_TTBR0 (TTBCR_T0SZ(0) | TTBCR_T1SZ(0)) |
| 427 | #define TTBCR_IRGN0_NC (0 << 8) |
| 428 | #define TTBCR_IRGN0_WBWA (1 << 8) |
| 429 | #define TTBCR_IRGN0_WT (2 << 8) |
| 430 | #define TTBCR_IRGN0_WBNWA (3 << 8) |
| 431 | #define TTBCR_IRGN0_MASK (3 << 8) |
| 432 | #define TTBCR_ORGN0_NC (0 << 10) |
| 433 | #define TTBCR_ORGN0_WBWA (1 << 10) |
| 434 | #define TTBCR_ORGN0_WT (2 << 10) |
| 435 | #define TTBCR_ORGN0_WBNWA (3 << 10) |
| 436 | #define TTBCR_ORGN0_MASK (3 << 10) |
| 437 | #define TTBCR_SHARED_NON (0 << 12) |
| 438 | #define TTBCR_SHARED_OUTER (2 << 12) |
| 439 | #define TTBCR_SHARED_INNER (3 << 12) |
| 440 | #define TTBCR_EPD0 (0 << 7) |
| 441 | |
| 442 | /* |
| 443 | * Memory types |
| 444 | */ |
| 445 | #define MEMORY_ATTRIBUTES ((0x00 << (0 * 8)) | (0x88 << (1 * 8)) | \ |
| 446 | (0xcc << (2 * 8)) | (0xff << (3 * 8))) |
| 447 | |
| 448 | /* options available for data cache on each page */ |
| 449 | enum dcache_option { |
Keerthy | 266c8c1 | 2016-10-29 15:19:10 +0530 | [diff] [blame] | 450 | DCACHE_OFF = TTB_SECT | TTB_SECT_MAIR(0) | TTB_SECT_XN_MASK, |
Alexander Graf | ae6c2bc | 2016-03-16 15:41:21 +0100 | [diff] [blame] | 451 | DCACHE_WRITETHROUGH = TTB_SECT | TTB_SECT_MAIR(1), |
| 452 | DCACHE_WRITEBACK = TTB_SECT | TTB_SECT_MAIR(2), |
| 453 | DCACHE_WRITEALLOC = TTB_SECT | TTB_SECT_MAIR(3), |
| 454 | }; |
Lokesh Vutla | 81b1a67 | 2018-04-26 18:21:26 +0530 | [diff] [blame] | 455 | #elif defined(CONFIG_CPU_V7A) |
Bryan Brinsko | 29d23ec | 2015-03-24 11:25:12 -0500 | [diff] [blame] | 456 | /* Short-Descriptor Translation Table Level 1 Bits */ |
| 457 | #define TTB_SECT_NS_MASK (1 << 19) |
| 458 | #define TTB_SECT_NG_MASK (1 << 17) |
| 459 | #define TTB_SECT_S_MASK (1 << 16) |
| 460 | /* Note: TTB AP bits are set elsewhere */ |
Alexander Graf | ae6c2bc | 2016-03-16 15:41:21 +0100 | [diff] [blame] | 461 | #define TTB_SECT_AP (3 << 10) |
Bryan Brinsko | 29d23ec | 2015-03-24 11:25:12 -0500 | [diff] [blame] | 462 | #define TTB_SECT_TEX(x) ((x & 0x7) << 12) |
| 463 | #define TTB_SECT_DOMAIN(x) ((x & 0xf) << 5) |
| 464 | #define TTB_SECT_XN_MASK (1 << 4) |
| 465 | #define TTB_SECT_C_MASK (1 << 3) |
| 466 | #define TTB_SECT_B_MASK (1 << 2) |
| 467 | #define TTB_SECT (2 << 0) |
| 468 | |
Simon Glass | a4f2079 | 2012-10-17 13:24:53 +0000 | [diff] [blame] | 469 | /* options available for data cache on each page */ |
| 470 | enum dcache_option { |
Marek Vasut | d6e436e | 2015-12-29 19:44:02 +0100 | [diff] [blame] | 471 | DCACHE_OFF = TTB_SECT_DOMAIN(0) | TTB_SECT_XN_MASK | TTB_SECT, |
Bryan Brinsko | 29d23ec | 2015-03-24 11:25:12 -0500 | [diff] [blame] | 472 | DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK, |
| 473 | DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK, |
| 474 | DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1), |
| 475 | }; |
| 476 | #else |
Alexander Graf | ae6c2bc | 2016-03-16 15:41:21 +0100 | [diff] [blame] | 477 | #define TTB_SECT_AP (3 << 10) |
Bryan Brinsko | 29d23ec | 2015-03-24 11:25:12 -0500 | [diff] [blame] | 478 | /* options available for data cache on each page */ |
| 479 | enum dcache_option { |
Simon Glass | a4f2079 | 2012-10-17 13:24:53 +0000 | [diff] [blame] | 480 | DCACHE_OFF = 0x12, |
| 481 | DCACHE_WRITETHROUGH = 0x1a, |
| 482 | DCACHE_WRITEBACK = 0x1e, |
Marek Vasut | 79b9072 | 2014-09-15 02:44:36 +0200 | [diff] [blame] | 483 | DCACHE_WRITEALLOC = 0x16, |
Simon Glass | a4f2079 | 2012-10-17 13:24:53 +0000 | [diff] [blame] | 484 | }; |
Bryan Brinsko | 29d23ec | 2015-03-24 11:25:12 -0500 | [diff] [blame] | 485 | #endif |
Simon Glass | a4f2079 | 2012-10-17 13:24:53 +0000 | [diff] [blame] | 486 | |
| 487 | /* Size of an MMU section */ |
| 488 | enum { |
Alexander Graf | ae6c2bc | 2016-03-16 15:41:21 +0100 | [diff] [blame] | 489 | #ifdef CONFIG_ARMV7_LPAE |
| 490 | MMU_SECTION_SHIFT = 21, /* 2MB */ |
| 491 | #else |
| 492 | MMU_SECTION_SHIFT = 20, /* 1MB */ |
| 493 | #endif |
Simon Glass | a4f2079 | 2012-10-17 13:24:53 +0000 | [diff] [blame] | 494 | MMU_SECTION_SIZE = 1 << MMU_SECTION_SHIFT, |
| 495 | }; |
| 496 | |
Lokesh Vutla | 81b1a67 | 2018-04-26 18:21:26 +0530 | [diff] [blame] | 497 | #ifdef CONFIG_CPU_V7A |
Bryan Brinsko | 29d23ec | 2015-03-24 11:25:12 -0500 | [diff] [blame] | 498 | /* TTBR0 bits */ |
| 499 | #define TTBR0_BASE_ADDR_MASK 0xFFFFC000 |
| 500 | #define TTBR0_RGN_NC (0 << 3) |
| 501 | #define TTBR0_RGN_WBWA (1 << 3) |
| 502 | #define TTBR0_RGN_WT (2 << 3) |
| 503 | #define TTBR0_RGN_WB (3 << 3) |
| 504 | /* TTBR0[6] is IRGN[0] and TTBR[0] is IRGN[1] */ |
| 505 | #define TTBR0_IRGN_NC (0 << 0 | 0 << 6) |
| 506 | #define TTBR0_IRGN_WBWA (0 << 0 | 1 << 6) |
| 507 | #define TTBR0_IRGN_WT (1 << 0 | 0 << 6) |
| 508 | #define TTBR0_IRGN_WB (1 << 0 | 1 << 6) |
| 509 | #endif |
| 510 | |
Simon Glass | a4f2079 | 2012-10-17 13:24:53 +0000 | [diff] [blame] | 511 | /** |
Simon Glass | a4f2079 | 2012-10-17 13:24:53 +0000 | [diff] [blame] | 512 | * Register an update to the page tables, and flush the TLB |
| 513 | * |
| 514 | * \param start start address of update in page table |
| 515 | * \param stop stop address of update in page table |
| 516 | */ |
| 517 | void mmu_page_table_flush(unsigned long start, unsigned long stop); |
| 518 | |
Jean-Christophe PLAGNIOL-VILLARD | 9053b5a | 2009-04-05 13:02:43 +0200 | [diff] [blame] | 519 | #endif /* __ASSEMBLY__ */ |
| 520 | |
| 521 | #define arch_align_stack(x) (x) |
| 522 | |
| 523 | #endif /* __KERNEL__ */ |
| 524 | |
David Feng | 85fd5f1 | 2013-12-14 11:47:35 +0800 | [diff] [blame] | 525 | #endif /* CONFIG_ARM64 */ |
| 526 | |
Siva Durga Prasad Paladugu | ba2432a | 2015-06-26 18:05:07 +0530 | [diff] [blame] | 527 | #ifndef __ASSEMBLY__ |
| 528 | /** |
Philipp Tomsich | cd36d45 | 2017-10-10 16:21:11 +0200 | [diff] [blame] | 529 | * save_boot_params() - Save boot parameters before starting reset sequence |
| 530 | * |
| 531 | * If you provide this function it will be called immediately U-Boot starts, |
| 532 | * both for SPL and U-Boot proper. |
| 533 | * |
| 534 | * All registers are unchanged from U-Boot entry. No registers need be |
| 535 | * preserved. |
| 536 | * |
| 537 | * This is not a normal C function. There is no stack. Return by branching to |
| 538 | * save_boot_params_ret. |
| 539 | * |
| 540 | * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3); |
| 541 | */ |
| 542 | |
| 543 | /** |
| 544 | * save_boot_params_ret() - Return from save_boot_params() |
| 545 | * |
| 546 | * If you provide save_boot_params(), then you should jump back to this |
| 547 | * function when done. Try to preserve all registers. |
| 548 | * |
| 549 | * If your implementation of save_boot_params() is in C then it is acceptable |
| 550 | * to simply call save_boot_params_ret() at the end of your function. Since |
| 551 | * there is no link register set up, you cannot just exit the function. U-Boot |
| 552 | * will return to the (initialised) value of lr, and likely crash/hang. |
| 553 | * |
| 554 | * If your implementation of save_boot_params() is in assembler then you |
| 555 | * should use 'b' or 'bx' to return to save_boot_params_ret. |
| 556 | */ |
| 557 | void save_boot_params_ret(void); |
| 558 | |
| 559 | /** |
Siva Durga Prasad Paladugu | ba2432a | 2015-06-26 18:05:07 +0530 | [diff] [blame] | 560 | * Change the cache settings for a region. |
| 561 | * |
| 562 | * \param start start address of memory region to change |
| 563 | * \param size size of memory region to change |
| 564 | * \param option dcache option to select |
| 565 | */ |
| 566 | void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, |
| 567 | enum dcache_option option); |
| 568 | |
Stephen Warren | fbdcd22 | 2015-10-05 12:08:59 -0600 | [diff] [blame] | 569 | #ifdef CONFIG_SYS_NONCACHED_MEMORY |
| 570 | void noncached_init(void); |
| 571 | phys_addr_t noncached_alloc(size_t size, size_t align); |
| 572 | #endif /* CONFIG_SYS_NONCACHED_MEMORY */ |
| 573 | |
Siva Durga Prasad Paladugu | ba2432a | 2015-06-26 18:05:07 +0530 | [diff] [blame] | 574 | #endif /* __ASSEMBLY__ */ |
| 575 | |
Jean-Christophe PLAGNIOL-VILLARD | 9053b5a | 2009-04-05 13:02:43 +0200 | [diff] [blame] | 576 | #endif |