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git01.mediatek.com / filogic / uboot / e0c84c8af2ac0db03972235d3b6f5fa4c951e696 / . / drivers / pinctrl / renesas / pfc-r8a77965.c
blob: 2852ae64ec07bdb42648a6884cd86b11417bae1e [file] [log] [blame]
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * R8A77965 processor support - PFC hardware block.
4 *
5 * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]6 * Copyright (C) 2016-2019 Renesas Electronics Corp.
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]7 *
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]8 * This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]9 *
10 * R-Car Gen3 processor support - PFC hardware block.
11 *
12 * Copyright (C) 2015 Renesas Electronics Corporation
13 */
14
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]15#include <dm.h>
16#include <errno.h>
17#include <dm/pinctrl.h>
18#include <linux/kernel.h>
19
20#include "sh_pfc.h"
21
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]22#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]23
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]24#define CPU_ALL_GP(fn, sfx) \
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]25 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
26 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
Marek Vasutb8227b32023-09-17 16:08:42 +0200[diff] [blame]28 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]29 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
31 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
Marek Vasutb8227b32023-09-17 16:08:42 +0200[diff] [blame]33 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]34 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
35 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
36 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]37
38#define CPU_ALL_NOGP(fn) \
39 PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \
40 PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \
41 PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \
42 PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \
43 PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \
44 PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \
45 PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \
46 PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \
47 PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \
48 PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \
49 PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \
50 PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \
51 PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \
52 PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \
53 PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \
54 PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \
55 PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \
56 PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS), \
57 PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
58 PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, CFG_FLAGS), \
59 PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
60 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \
61 PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \
62 PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \
63 PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \
64 PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \
65 PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \
66 PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \
67 PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \
68 PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \
69 PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \
70 PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \
71 PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \
72 PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \
73 PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \
74 PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \
75 PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \
76 PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
77 PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
78 PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
79 PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \
80 PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
81
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]82/*
83 * F_() : just information
84 * FM() : macro for FN_xxx / xxx_MARK
85 */
86
87/* GPSR0 */
88#define GPSR0_15 F_(D15, IP7_11_8)
89#define GPSR0_14 F_(D14, IP7_7_4)
90#define GPSR0_13 F_(D13, IP7_3_0)
91#define GPSR0_12 F_(D12, IP6_31_28)
92#define GPSR0_11 F_(D11, IP6_27_24)
93#define GPSR0_10 F_(D10, IP6_23_20)
94#define GPSR0_9 F_(D9, IP6_19_16)
95#define GPSR0_8 F_(D8, IP6_15_12)
96#define GPSR0_7 F_(D7, IP6_11_8)
97#define GPSR0_6 F_(D6, IP6_7_4)
98#define GPSR0_5 F_(D5, IP6_3_0)
99#define GPSR0_4 F_(D4, IP5_31_28)
100#define GPSR0_3 F_(D3, IP5_27_24)
101#define GPSR0_2 F_(D2, IP5_23_20)
102#define GPSR0_1 F_(D1, IP5_19_16)
103#define GPSR0_0 F_(D0, IP5_15_12)
104
105/* GPSR1 */
106#define GPSR1_28 FM(CLKOUT)
107#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
108#define GPSR1_26 F_(WE1_N, IP5_7_4)
109#define GPSR1_25 F_(WE0_N, IP5_3_0)
110#define GPSR1_24 F_(RD_WR_N, IP4_31_28)
111#define GPSR1_23 F_(RD_N, IP4_27_24)
112#define GPSR1_22 F_(BS_N, IP4_23_20)
113#define GPSR1_21 F_(CS1_N, IP4_19_16)
114#define GPSR1_20 F_(CS0_N, IP4_15_12)
115#define GPSR1_19 F_(A19, IP4_11_8)
116#define GPSR1_18 F_(A18, IP4_7_4)
117#define GPSR1_17 F_(A17, IP4_3_0)
118#define GPSR1_16 F_(A16, IP3_31_28)
119#define GPSR1_15 F_(A15, IP3_27_24)
120#define GPSR1_14 F_(A14, IP3_23_20)
121#define GPSR1_13 F_(A13, IP3_19_16)
122#define GPSR1_12 F_(A12, IP3_15_12)
123#define GPSR1_11 F_(A11, IP3_11_8)
124#define GPSR1_10 F_(A10, IP3_7_4)
125#define GPSR1_9 F_(A9, IP3_3_0)
126#define GPSR1_8 F_(A8, IP2_31_28)
127#define GPSR1_7 F_(A7, IP2_27_24)
128#define GPSR1_6 F_(A6, IP2_23_20)
129#define GPSR1_5 F_(A5, IP2_19_16)
130#define GPSR1_4 F_(A4, IP2_15_12)
131#define GPSR1_3 F_(A3, IP2_11_8)
132#define GPSR1_2 F_(A2, IP2_7_4)
133#define GPSR1_1 F_(A1, IP2_3_0)
134#define GPSR1_0 F_(A0, IP1_31_28)
135
136/* GPSR2 */
137#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
138#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
139#define GPSR2_12 F_(AVB_LINK, IP0_15_12)
140#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
141#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
142#define GPSR2_9 F_(AVB_MDC, IP0_3_0)
143#define GPSR2_8 F_(PWM2_A, IP1_27_24)
144#define GPSR2_7 F_(PWM1_A, IP1_23_20)
145#define GPSR2_6 F_(PWM0, IP1_19_16)
146#define GPSR2_5 F_(IRQ5, IP1_15_12)
147#define GPSR2_4 F_(IRQ4, IP1_11_8)
148#define GPSR2_3 F_(IRQ3, IP1_7_4)
149#define GPSR2_2 F_(IRQ2, IP1_3_0)
150#define GPSR2_1 F_(IRQ1, IP0_31_28)
151#define GPSR2_0 F_(IRQ0, IP0_27_24)
152
153/* GPSR3 */
154#define GPSR3_15 F_(SD1_WP, IP11_23_20)
155#define GPSR3_14 F_(SD1_CD, IP11_19_16)
156#define GPSR3_13 F_(SD0_WP, IP11_15_12)
157#define GPSR3_12 F_(SD0_CD, IP11_11_8)
158#define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
159#define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
160#define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
161#define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
162#define GPSR3_7 F_(SD1_CMD, IP8_15_12)
163#define GPSR3_6 F_(SD1_CLK, IP8_11_8)
164#define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
165#define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
166#define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
167#define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
168#define GPSR3_1 F_(SD0_CMD, IP7_23_20)
169#define GPSR3_0 F_(SD0_CLK, IP7_19_16)
170
171/* GPSR4 */
172#define GPSR4_17 F_(SD3_DS, IP11_7_4)
173#define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
174#define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
175#define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
176#define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
177#define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
178#define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
179#define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
180#define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
181#define GPSR4_8 F_(SD3_CMD, IP10_3_0)
182#define GPSR4_7 F_(SD3_CLK, IP9_31_28)
183#define GPSR4_6 F_(SD2_DS, IP9_27_24)
184#define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
185#define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
186#define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
187#define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
188#define GPSR4_1 F_(SD2_CMD, IP9_7_4)
189#define GPSR4_0 F_(SD2_CLK, IP9_3_0)
190
191/* GPSR5 */
192#define GPSR5_25 F_(MLB_DAT, IP14_19_16)
193#define GPSR5_24 F_(MLB_SIG, IP14_15_12)
194#define GPSR5_23 F_(MLB_CLK, IP14_11_8)
195#define GPSR5_22 FM(MSIOF0_RXD)
196#define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
197#define GPSR5_20 FM(MSIOF0_TXD)
198#define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
199#define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
200#define GPSR5_17 FM(MSIOF0_SCK)
201#define GPSR5_16 F_(HRTS0_N, IP13_27_24)
202#define GPSR5_15 F_(HCTS0_N, IP13_23_20)
203#define GPSR5_14 F_(HTX0, IP13_19_16)
204#define GPSR5_13 F_(HRX0, IP13_15_12)
205#define GPSR5_12 F_(HSCK0, IP13_11_8)
206#define GPSR5_11 F_(RX2_A, IP13_7_4)
207#define GPSR5_10 F_(TX2_A, IP13_3_0)
208#define GPSR5_9 F_(SCK2, IP12_31_28)
209#define GPSR5_8 F_(RTS1_N, IP12_27_24)
210#define GPSR5_7 F_(CTS1_N, IP12_23_20)
211#define GPSR5_6 F_(TX1_A, IP12_19_16)
212#define GPSR5_5 F_(RX1_A, IP12_15_12)
213#define GPSR5_4 F_(RTS0_N, IP12_11_8)
214#define GPSR5_3 F_(CTS0_N, IP12_7_4)
215#define GPSR5_2 F_(TX0, IP12_3_0)
216#define GPSR5_1 F_(RX0, IP11_31_28)
217#define GPSR5_0 F_(SCK0, IP11_27_24)
218
219/* GPSR6 */
220#define GPSR6_31 F_(GP6_31, IP18_7_4)
221#define GPSR6_30 F_(GP6_30, IP18_3_0)
222#define GPSR6_29 F_(USB30_OVC, IP17_31_28)
223#define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
224#define GPSR6_27 F_(USB1_OVC, IP17_23_20)
225#define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
226#define GPSR6_25 F_(USB0_OVC, IP17_15_12)
227#define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
228#define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
229#define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
230#define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
231#define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
232#define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
233#define GPSR6_18 F_(SSI_WS78, IP16_19_16)
234#define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
235#define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
236#define GPSR6_15 F_(SSI_WS6, IP16_7_4)
237#define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
238#define GPSR6_13 FM(SSI_SDATA5)
239#define GPSR6_12 FM(SSI_WS5)
240#define GPSR6_11 FM(SSI_SCK5)
241#define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
242#define GPSR6_9 F_(SSI_WS4, IP15_27_24)
243#define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
244#define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
245#define GPSR6_6 F_(SSI_WS349, IP15_15_12)
246#define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
247#define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
248#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
249#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
250#define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
251#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
252
253/* GPSR7 */
254#define GPSR7_3 FM(GP7_03)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]255#define GPSR7_2 FM(GP7_02)
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]256#define GPSR7_1 FM(AVS2)
257#define GPSR7_0 FM(AVS1)
258
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]259/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
260#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273#define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274#define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287
288/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
289#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298#define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318
319/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
320#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335#define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336#define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341#define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342#define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343#define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352#define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354
355/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
356#define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357#define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358#define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359#define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
361#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
362#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
363#define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
364#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
365#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
366#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
367#define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
368#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
369#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
370#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
371#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
372#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
373#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
374#define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
375#define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
376#define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
377#define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
378#define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
379#define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
380#define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
381#define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
382#define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
383#define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
384
385/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
386#define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
387#define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
388#define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
389#define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
390#define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
391#define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
392#define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
393#define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
394#define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
395#define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
396#define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
397#define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
398#define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
399#define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
400#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
401#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
402#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]403#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]404#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
405#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
406#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
407#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
408#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
409#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
410#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
411#define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
412#define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
413
414#define PINMUX_GPSR \
415\
416 GPSR6_31 \
417 GPSR6_30 \
418 GPSR6_29 \
419 GPSR1_28 GPSR6_28 \
420 GPSR1_27 GPSR6_27 \
421 GPSR1_26 GPSR6_26 \
422 GPSR1_25 GPSR5_25 GPSR6_25 \
423 GPSR1_24 GPSR5_24 GPSR6_24 \
424 GPSR1_23 GPSR5_23 GPSR6_23 \
425 GPSR1_22 GPSR5_22 GPSR6_22 \
426 GPSR1_21 GPSR5_21 GPSR6_21 \
427 GPSR1_20 GPSR5_20 GPSR6_20 \
428 GPSR1_19 GPSR5_19 GPSR6_19 \
429 GPSR1_18 GPSR5_18 GPSR6_18 \
430 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
431 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
432GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
433GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
434GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
435GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
436GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
437GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
438GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
439GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
440GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
441GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
442GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
443GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
444GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
445GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
446GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
447GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
448
449#define PINMUX_IPSR \
450\
451FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
452FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
453FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
454FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
455FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
456FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
457FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
458FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
459\
460FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
461FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
462FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
463FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
464FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
465FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
466FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
467FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
468\
469FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
470FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
471FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
472FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
473FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
474FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
475FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
476FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
477\
478FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
479FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
480FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
481FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
482FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
483FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
484FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
485FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
486\
487FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
488FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
489FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
490FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
491FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
492FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
493FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
494FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
495
496/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
497#define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
498#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
499#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
500#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
501#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
502#define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
503#define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
504#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
505#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
506#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
507#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
508#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
509#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
510#define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
511#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
512#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
513#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]514#define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3)
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]515
516/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
517#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
518#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
519#define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
520#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
521#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
522#define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
523#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
524#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
525#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
526#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
527#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
528#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
529#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
530#define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
531#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
532#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
533#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
534#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
535#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
536#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
537#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
538#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
539
540/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
541#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
542#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
543#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
544#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
545#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
546#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]547#define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1)
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]548#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
549#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
550#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]551#define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1)
552#define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1)
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]553#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
554
555#define PINMUX_MOD_SELS \
556\
557MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
558 MOD_SEL2_30 \
559 MOD_SEL1_29_28_27 MOD_SEL2_29 \
560MOD_SEL0_28_27 MOD_SEL2_28_27 \
561MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
562 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
563MOD_SEL0_23 MOD_SEL1_23_22_21 \
564MOD_SEL0_22 MOD_SEL2_22 \
565MOD_SEL0_21 MOD_SEL2_21 \
566MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
567MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
568MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
569 MOD_SEL2_17 \
570MOD_SEL0_16 MOD_SEL1_16 \
571 MOD_SEL1_15_14 \
572MOD_SEL0_14_13 \
573 MOD_SEL1_13 \
574MOD_SEL0_12 MOD_SEL1_12 \
575MOD_SEL0_11 MOD_SEL1_11 \
576MOD_SEL0_10 MOD_SEL1_10 \
577MOD_SEL0_9_8 MOD_SEL1_9 \
578MOD_SEL0_7_6 \
579 MOD_SEL1_6 \
580MOD_SEL0_5 MOD_SEL1_5 \
581MOD_SEL0_4_3 MOD_SEL1_4 \
582 MOD_SEL1_3 \
583 MOD_SEL1_2 \
584 MOD_SEL1_1 \
585 MOD_SEL1_0 MOD_SEL2_0
586
587/*
588 * These pins are not able to be muxed but have other properties
589 * that can be set, such as drive-strength or pull-up/pull-down enable.
590 */
591#define PINMUX_STATIC \
592 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
593 FM(QSPI0_IO2) FM(QSPI0_IO3) \
594 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
595 FM(QSPI1_IO2) FM(QSPI1_IO3) \
596 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
597 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
598 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
599 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
600 FM(PRESETOUT) \
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]601 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN3) \
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]602 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
603
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]604#define PINMUX_PHYS \
605 FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
606
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]607enum {
608 PINMUX_RESERVED = 0,
609
610 PINMUX_DATA_BEGIN,
611 GP_ALL(DATA),
612 PINMUX_DATA_END,
613
614#define F_(x, y)
615#define FM(x) FN_##x,
616 PINMUX_FUNCTION_BEGIN,
617 GP_ALL(FN),
618 PINMUX_GPSR
619 PINMUX_IPSR
620 PINMUX_MOD_SELS
621 PINMUX_FUNCTION_END,
622#undef F_
623#undef FM
624
625#define F_(x, y)
626#define FM(x) x##_MARK,
627 PINMUX_MARK_BEGIN,
628 PINMUX_GPSR
629 PINMUX_IPSR
630 PINMUX_MOD_SELS
631 PINMUX_STATIC
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]632 PINMUX_PHYS
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]633 PINMUX_MARK_END,
634#undef F_
635#undef FM
636};
637
638static const u16 pinmux_data[] = {
639 PINMUX_DATA_GP_ALL(),
640
641 PINMUX_SINGLE(AVS1),
642 PINMUX_SINGLE(AVS2),
643 PINMUX_SINGLE(CLKOUT),
644 PINMUX_SINGLE(GP7_03),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]645 PINMUX_SINGLE(GP7_02),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]646 PINMUX_SINGLE(MSIOF0_RXD),
647 PINMUX_SINGLE(MSIOF0_SCK),
648 PINMUX_SINGLE(MSIOF0_TXD),
649 PINMUX_SINGLE(SSI_SCK5),
650 PINMUX_SINGLE(SSI_SDATA5),
651 PINMUX_SINGLE(SSI_WS5),
652
653 /* IPSR0 */
654 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
655 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
656
657 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
658 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
659 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
660
661 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
662 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
663 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
664
665 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
666 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
667 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
668 PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A),
669
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]670 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
671 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
672 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]673 PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]674
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]675 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
676 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
677 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]678 PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]679
680 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
681 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
682 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
683 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
684 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
685 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
686 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
687
688 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
689 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
690 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
691 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
692 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
693 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
694 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
695
696 /* IPSR1 */
697 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
698 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
699 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
700 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
701 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
702 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
703
704 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
705 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
706 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
707 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
708 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
709 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
710
711 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
712 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
713 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
714 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
715 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
716 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
717
718 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
719 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
720 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
721 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
722 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
723 PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B),
724 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
725
726 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
727 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
728 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
729 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
730
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]731 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
732 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
733 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
734 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
735 PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]736
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]737 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
738 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
739 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
740 PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]741
742 PINMUX_IPSR_GPSR(IP1_31_28, A0),
743 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
744 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
745 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
746 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
747 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
748
749 /* IPSR2 */
750 PINMUX_IPSR_GPSR(IP2_3_0, A1),
751 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
752 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
753 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
754 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
755 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
756
757 PINMUX_IPSR_GPSR(IP2_7_4, A2),
758 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
759 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
760 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
761 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
762 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
763
764 PINMUX_IPSR_GPSR(IP2_11_8, A3),
765 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
766 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
767 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
768 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
769 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
770
771 PINMUX_IPSR_GPSR(IP2_15_12, A4),
772 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
773 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
774 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
775 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
776 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
777
778 PINMUX_IPSR_GPSR(IP2_19_16, A5),
779 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
780 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
781 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
782 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
783 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
784 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
785
786 PINMUX_IPSR_GPSR(IP2_23_20, A6),
787 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
788 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
789 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
790 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
791 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
792 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
793
794 PINMUX_IPSR_GPSR(IP2_27_24, A7),
795 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
796 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
797 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
798 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
799 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
800 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
801
802 PINMUX_IPSR_GPSR(IP2_31_28, A8),
803 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
804 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
805 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
806 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
807 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
808 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
809
810 /* IPSR3 */
811 PINMUX_IPSR_GPSR(IP3_3_0, A9),
812 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
813 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
814 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
815
816 PINMUX_IPSR_GPSR(IP3_7_4, A10),
817 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
818 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
819 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
820
821 PINMUX_IPSR_GPSR(IP3_11_8, A11),
822 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
823 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
824 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
825 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
826 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
827 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
828 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
829 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
830
831 PINMUX_IPSR_GPSR(IP3_15_12, A12),
832 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
833 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
834 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
835 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
836 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
837
838 PINMUX_IPSR_GPSR(IP3_19_16, A13),
839 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
840 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
841 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
842 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
843 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
844
845 PINMUX_IPSR_GPSR(IP3_23_20, A14),
846 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
847 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
848 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
849 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
850 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
851
852 PINMUX_IPSR_GPSR(IP3_27_24, A15),
853 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
854 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
855 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
856 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
857 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
858
859 PINMUX_IPSR_GPSR(IP3_31_28, A16),
860 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
861 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
862 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
863
864 /* IPSR4 */
865 PINMUX_IPSR_GPSR(IP4_3_0, A17),
866 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
867 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
868 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
869
870 PINMUX_IPSR_GPSR(IP4_7_4, A18),
871 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
872 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
873 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
874
875 PINMUX_IPSR_GPSR(IP4_11_8, A19),
876 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
877 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
878 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
879
880 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
881 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
882
883 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
884 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
885 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
886
887 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
888 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
889 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
890 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
891 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
892 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
893 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
894 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
895
896 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
897 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
898 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
899 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
900 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
901 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
902
903 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
904 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
905 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
906 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
907 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
908 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
909
910 /* IPSR5 */
911 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
912 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
913 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
914 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
915 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
916 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
917 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
918
919 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
920 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
921 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
922 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
923 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
924 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
925 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
926 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
927
928 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
929 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
930 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
931 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
932
933 PINMUX_IPSR_GPSR(IP5_15_12, D0),
934 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
935 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
936 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
937 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
938
939 PINMUX_IPSR_GPSR(IP5_19_16, D1),
940 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
941 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
942 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
943 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
944
945 PINMUX_IPSR_GPSR(IP5_23_20, D2),
946 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
947 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
948 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
949
950 PINMUX_IPSR_GPSR(IP5_27_24, D3),
951 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
952 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
953 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
954
955 PINMUX_IPSR_GPSR(IP5_31_28, D4),
956 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
957 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
958 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
959
960 /* IPSR6 */
961 PINMUX_IPSR_GPSR(IP6_3_0, D5),
962 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
963 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
964 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
965
966 PINMUX_IPSR_GPSR(IP6_7_4, D6),
967 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
968 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
969 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
970
971 PINMUX_IPSR_GPSR(IP6_11_8, D7),
972 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
973 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
974 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
975
976 PINMUX_IPSR_GPSR(IP6_15_12, D8),
977 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
978 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
979 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
980 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
981 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
982
983 PINMUX_IPSR_GPSR(IP6_19_16, D9),
984 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
985 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
986 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
987 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
988
989 PINMUX_IPSR_GPSR(IP6_23_20, D10),
990 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
991 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
992 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
993 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
994 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
995 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
996
997 PINMUX_IPSR_GPSR(IP6_27_24, D11),
998 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
999 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
1000 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
1001 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
1002 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
1003 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
1004
1005 PINMUX_IPSR_GPSR(IP6_31_28, D12),
1006 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
1007 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
1008 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
1009 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
1010 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
1011
1012 /* IPSR7 */
1013 PINMUX_IPSR_GPSR(IP7_3_0, D13),
1014 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
1015 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
1016 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
1017 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
1018 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
1019
1020 PINMUX_IPSR_GPSR(IP7_7_4, D14),
1021 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
1022 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
1023 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
1024 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
1025 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
1026 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
1027
1028 PINMUX_IPSR_GPSR(IP7_11_8, D15),
1029 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
1030 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
1031 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
1032 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
1033 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
1034 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
1035
1036 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
1037 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
1038 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
1039
1040 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
1041 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
1042 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
1043
1044 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
1045 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
1046 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
1047 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
1048
1049 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
1050 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
1051 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
1052 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
1053
1054 /* IPSR8 */
1055 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
1056 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1057 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1058 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
1059
1060 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1061 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1062 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1063 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
1064
1065 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1066 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1067 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
1068
1069 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1070 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1071 PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1072 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1073 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
1074
1075 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1076 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1077 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1078 PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1079 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1080 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1081
1082 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1083 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1084 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1085 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1086 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1087 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1088
1089 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1090 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1091 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1092 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1093 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1094 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1095
1096 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1097 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1098 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1099 PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1100 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1101 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1102
1103 /* IPSR9 */
1104 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1105 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
1106
1107 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
1108 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
1109
1110 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
1111 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
1112
1113 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1114 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
1115
1116 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1117 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
1118
1119 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1120 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
1121
1122 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1123 PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1124 PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B),
1125
1126 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1127 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
1128
1129 /* IPSR10 */
1130 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
1131 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
1132
1133 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
1134 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
1135
1136 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1137 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
1138
1139 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
1140 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
1141
1142 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
1143 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
1144
1145 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
1146 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
1147 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
1148
1149 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
1150 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
1151 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
1152
1153 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
1154 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
1155 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
1156
1157 /* IPSR11 */
1158 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
1159 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
1160 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
1161
1162 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
1163 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1164
1165 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1166 PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDF_0),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1167 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1168 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1169
1170 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1171 PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDF_0),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1172 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1173
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1174 PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0),
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]1175 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0),
1176 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1177 PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1178
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1179 PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0),
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]1180 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0),
1181 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1182 PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1183
1184 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1185 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1186 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1187 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1188 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1189 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1190 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1191 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1192 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
1193 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
1194
1195 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
1196 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
1197 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
1198 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1199 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
1200
1201 /* IPSR12 */
1202 PINMUX_IPSR_GPSR(IP12_3_0, TX0),
1203 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
1204 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1205 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1206 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
1207
1208 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
1209 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1210 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1211 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1212 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1213 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1214 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1215 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1216
1217 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
1218 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1219 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1220 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1221 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1222 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1223 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1224 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1225
1226 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
1227 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
1228 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1229 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1230 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1231
1232 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
1233 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
1234 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1235 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1236 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
1237
1238 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
1239 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1240 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1241 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1242 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1243 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1244 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1245
1246 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N),
1247 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1248 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1249 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1250 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1251 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
1252 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1253
1254 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
1255 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
1256 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1257 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1258 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1259 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1260 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
1261
1262 /* IPSR13 */
1263 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
1264 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
1265 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1266 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1267 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
1268 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
1269
1270 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1271 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1272 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1273 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1274 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1275 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
1276
1277 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1278 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1279 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1280 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
1281 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1282 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1283 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1284 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
1285
1286 PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
1287 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
1288 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1),
1289 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1290 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1291 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
1292
1293 PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
1294 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
1295 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1),
1296 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1297 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1298 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
1299
1300 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
1301 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
1302 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
1303 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0),
1304 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1305 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1306 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1307 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
1308
1309 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
1310 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
1311 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
1312 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0),
1313 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1314 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
1315 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
1316
1317 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
1318 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
1319 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
1320 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
1321
1322 /* IPSR14 */
1323 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1324 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1325 PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0),
1326 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1327 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
1328 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1329 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
1330 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1),
1331
1332 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1333 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1334 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1335 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1336 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
1337 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1338 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
1339 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1340
1341 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1342 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1343 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
1344
1345 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
1346 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
1347 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1348 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
1349
1350 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
1351 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
1352 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1353
1354 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
1355 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1356
1357 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
1358 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1359
1360 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
1361 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1362
1363 /* IPSR15 */
1364 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0),
1365
1366 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0),
1367 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1),
1368
1369 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
1370 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1371 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1372
1373 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
1374 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1375 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1376 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1377
1378 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
1379 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1380 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1381 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
1382 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1383 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
1384 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
1385
1386 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
1387 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
1388 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1389 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1390 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1391 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1392 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1393
1394 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
1395 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
1396 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1397 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1398 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1399 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1400 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1401
1402 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
1403 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
1404 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1405 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1406 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1407 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
1408 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
1409
1410 /* IPSR16 */
1411 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
1412 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1413
1414 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
1415 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
1416
1417 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1418 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1419 PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A),
1420
1421 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
1422 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
1423 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1424 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
1425 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1426 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1427 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1428
1429 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
1430 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
1431 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1432 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1433 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1434 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1435 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1436
1437 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
1438 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1439 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1440 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1441 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1442 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1443 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
1444 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
1445
1446 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1447 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1448 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1449 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1450 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1451 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
1452 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
1453
1454 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0),
1455 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
1456 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1457 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
1458 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1),
1459 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1460 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1461 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
1462
1463 /* IPSR17 */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1464 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1465
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1466 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1467 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
1468 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1469 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
1470 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0),
1471
1472 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1473 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1474 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
1475 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1476 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
1477 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1478 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
1479
1480 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
1481 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
1482 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
1483 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
1484 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
1485 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
1486
1487 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
1488 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
1489 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0),
1490 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
1491 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1492 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
1493 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1494 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1495 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
1496
1497 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
1498 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
1499 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0),
1500 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1501 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1502 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
1503 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1504 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
1505 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
1506
1507 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
1508 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
1509 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1),
1510 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1511 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
1512 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1513 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
1514 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
1515 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1516 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1517 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
1518
1519 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
1520 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
1521 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1),
1522 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1523 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1524 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1525 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
1526 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
1527 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1528
1529 /* IPSR18 */
1530 PINMUX_IPSR_GPSR(IP18_3_0, GP6_30),
1531 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
1532 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1),
1533 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1534 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1535 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1536 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
1537 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1538 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1539
1540 PINMUX_IPSR_GPSR(IP18_7_4, GP6_31),
1541 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
1542 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1),
1543 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1544 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1545 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1546 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
1547 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1548 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
1549
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1550/*
1551 * Static pins can not be muxed between different functions but
1552 * still need mark entries in the pinmux list. Add each static
1553 * pin to the list without an associated function. The sh-pfc
1554 * core will do the right thing and skip trying to mux the pin
1555 * while still applying configuration to it.
1556 */
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]1557#define FM(x) PINMUX_DATA(x##_MARK, 0),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1558 PINMUX_STATIC
1559#undef FM
1560};
1561
1562/*
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]1563 * Pins not associated with a GPIO port.
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1564 */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]1565enum {
1566 GP_ASSIGN_LAST(),
1567 NOGP_ALL(),
1568};
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1569
1570static const struct sh_pfc_pin pinmux_pins[] = {
1571 PINMUX_GPIO_GP_ALL(),
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]1572 PINMUX_NOGP_ALL(),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1573};
1574
1575/* - AUDIO CLOCK ------------------------------------------------------------ */
1576static const unsigned int audio_clk_a_a_pins[] = {
1577 /* CLK A */
1578 RCAR_GP_PIN(6, 22),
1579};
1580static const unsigned int audio_clk_a_a_mux[] = {
1581 AUDIO_CLKA_A_MARK,
1582};
1583static const unsigned int audio_clk_a_b_pins[] = {
1584 /* CLK A */
1585 RCAR_GP_PIN(5, 4),
1586};
1587static const unsigned int audio_clk_a_b_mux[] = {
1588 AUDIO_CLKA_B_MARK,
1589};
1590static const unsigned int audio_clk_a_c_pins[] = {
1591 /* CLK A */
1592 RCAR_GP_PIN(5, 19),
1593};
1594static const unsigned int audio_clk_a_c_mux[] = {
1595 AUDIO_CLKA_C_MARK,
1596};
1597static const unsigned int audio_clk_b_a_pins[] = {
1598 /* CLK B */
1599 RCAR_GP_PIN(5, 12),
1600};
1601static const unsigned int audio_clk_b_a_mux[] = {
1602 AUDIO_CLKB_A_MARK,
1603};
1604static const unsigned int audio_clk_b_b_pins[] = {
1605 /* CLK B */
1606 RCAR_GP_PIN(6, 23),
1607};
1608static const unsigned int audio_clk_b_b_mux[] = {
1609 AUDIO_CLKB_B_MARK,
1610};
1611static const unsigned int audio_clk_c_a_pins[] = {
1612 /* CLK C */
1613 RCAR_GP_PIN(5, 21),
1614};
1615static const unsigned int audio_clk_c_a_mux[] = {
1616 AUDIO_CLKC_A_MARK,
1617};
1618static const unsigned int audio_clk_c_b_pins[] = {
1619 /* CLK C */
1620 RCAR_GP_PIN(5, 0),
1621};
1622static const unsigned int audio_clk_c_b_mux[] = {
1623 AUDIO_CLKC_B_MARK,
1624};
1625static const unsigned int audio_clkout_a_pins[] = {
1626 /* CLKOUT */
1627 RCAR_GP_PIN(5, 18),
1628};
1629static const unsigned int audio_clkout_a_mux[] = {
1630 AUDIO_CLKOUT_A_MARK,
1631};
1632static const unsigned int audio_clkout_b_pins[] = {
1633 /* CLKOUT */
1634 RCAR_GP_PIN(6, 28),
1635};
1636static const unsigned int audio_clkout_b_mux[] = {
1637 AUDIO_CLKOUT_B_MARK,
1638};
1639static const unsigned int audio_clkout_c_pins[] = {
1640 /* CLKOUT */
1641 RCAR_GP_PIN(5, 3),
1642};
1643static const unsigned int audio_clkout_c_mux[] = {
1644 AUDIO_CLKOUT_C_MARK,
1645};
1646static const unsigned int audio_clkout_d_pins[] = {
1647 /* CLKOUT */
1648 RCAR_GP_PIN(5, 21),
1649};
1650static const unsigned int audio_clkout_d_mux[] = {
1651 AUDIO_CLKOUT_D_MARK,
1652};
1653static const unsigned int audio_clkout1_a_pins[] = {
1654 /* CLKOUT1 */
1655 RCAR_GP_PIN(5, 15),
1656};
1657static const unsigned int audio_clkout1_a_mux[] = {
1658 AUDIO_CLKOUT1_A_MARK,
1659};
1660static const unsigned int audio_clkout1_b_pins[] = {
1661 /* CLKOUT1 */
1662 RCAR_GP_PIN(6, 29),
1663};
1664static const unsigned int audio_clkout1_b_mux[] = {
1665 AUDIO_CLKOUT1_B_MARK,
1666};
1667static const unsigned int audio_clkout2_a_pins[] = {
1668 /* CLKOUT2 */
1669 RCAR_GP_PIN(5, 16),
1670};
1671static const unsigned int audio_clkout2_a_mux[] = {
1672 AUDIO_CLKOUT2_A_MARK,
1673};
1674static const unsigned int audio_clkout2_b_pins[] = {
1675 /* CLKOUT2 */
1676 RCAR_GP_PIN(6, 30),
1677};
1678static const unsigned int audio_clkout2_b_mux[] = {
1679 AUDIO_CLKOUT2_B_MARK,
1680};
1681
1682static const unsigned int audio_clkout3_a_pins[] = {
1683 /* CLKOUT3 */
1684 RCAR_GP_PIN(5, 19),
1685};
1686static const unsigned int audio_clkout3_a_mux[] = {
1687 AUDIO_CLKOUT3_A_MARK,
1688};
1689static const unsigned int audio_clkout3_b_pins[] = {
1690 /* CLKOUT3 */
1691 RCAR_GP_PIN(6, 31),
1692};
1693static const unsigned int audio_clkout3_b_mux[] = {
1694 AUDIO_CLKOUT3_B_MARK,
1695};
1696
1697/* - EtherAVB --------------------------------------------------------------- */
1698static const unsigned int avb_link_pins[] = {
1699 /* AVB_LINK */
1700 RCAR_GP_PIN(2, 12),
1701};
1702static const unsigned int avb_link_mux[] = {
1703 AVB_LINK_MARK,
1704};
1705static const unsigned int avb_magic_pins[] = {
1706 /* AVB_MAGIC_ */
1707 RCAR_GP_PIN(2, 10),
1708};
1709static const unsigned int avb_magic_mux[] = {
1710 AVB_MAGIC_MARK,
1711};
1712static const unsigned int avb_phy_int_pins[] = {
1713 /* AVB_PHY_INT */
1714 RCAR_GP_PIN(2, 11),
1715};
1716static const unsigned int avb_phy_int_mux[] = {
1717 AVB_PHY_INT_MARK,
1718};
1719static const unsigned int avb_mdio_pins[] = {
1720 /* AVB_MDC, AVB_MDIO */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]1721 RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1722};
1723static const unsigned int avb_mdio_mux[] = {
1724 AVB_MDC_MARK, AVB_MDIO_MARK,
1725};
1726static const unsigned int avb_mii_pins[] = {
1727 /*
1728 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1729 * AVB_TD1, AVB_TD2, AVB_TD3,
1730 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1731 * AVB_RD1, AVB_RD2, AVB_RD3,
1732 * AVB_TXCREFCLK
1733 */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]1734 PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,
1735 PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,
1736 PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
1737 PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
1738 PIN_AVB_TXCREFCLK,
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1739};
1740static const unsigned int avb_mii_mux[] = {
1741 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1742 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1743 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1744 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1745 AVB_TXCREFCLK_MARK,
1746};
1747static const unsigned int avb_avtp_pps_pins[] = {
1748 /* AVB_AVTP_PPS */
1749 RCAR_GP_PIN(2, 6),
1750};
1751static const unsigned int avb_avtp_pps_mux[] = {
1752 AVB_AVTP_PPS_MARK,
1753};
1754static const unsigned int avb_avtp_match_a_pins[] = {
1755 /* AVB_AVTP_MATCH_A */
1756 RCAR_GP_PIN(2, 13),
1757};
1758static const unsigned int avb_avtp_match_a_mux[] = {
1759 AVB_AVTP_MATCH_A_MARK,
1760};
1761static const unsigned int avb_avtp_capture_a_pins[] = {
1762 /* AVB_AVTP_CAPTURE_A */
1763 RCAR_GP_PIN(2, 14),
1764};
1765static const unsigned int avb_avtp_capture_a_mux[] = {
1766 AVB_AVTP_CAPTURE_A_MARK,
1767};
1768static const unsigned int avb_avtp_match_b_pins[] = {
1769 /* AVB_AVTP_MATCH_B */
1770 RCAR_GP_PIN(1, 8),
1771};
1772static const unsigned int avb_avtp_match_b_mux[] = {
1773 AVB_AVTP_MATCH_B_MARK,
1774};
1775static const unsigned int avb_avtp_capture_b_pins[] = {
1776 /* AVB_AVTP_CAPTURE_B */
1777 RCAR_GP_PIN(1, 11),
1778};
1779static const unsigned int avb_avtp_capture_b_mux[] = {
1780 AVB_AVTP_CAPTURE_B_MARK,
1781};
1782
1783/* - CAN ------------------------------------------------------------------ */
1784static const unsigned int can0_data_a_pins[] = {
1785 /* TX, RX */
1786 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1787};
1788
1789static const unsigned int can0_data_a_mux[] = {
1790 CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1791};
1792
1793static const unsigned int can0_data_b_pins[] = {
1794 /* TX, RX */
1795 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1796};
1797
1798static const unsigned int can0_data_b_mux[] = {
1799 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1800};
1801
1802static const unsigned int can1_data_pins[] = {
1803 /* TX, RX */
1804 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1805};
1806
1807static const unsigned int can1_data_mux[] = {
1808 CAN1_TX_MARK, CAN1_RX_MARK,
1809};
1810
1811/* - CAN Clock -------------------------------------------------------------- */
1812static const unsigned int can_clk_pins[] = {
1813 /* CLK */
1814 RCAR_GP_PIN(1, 25),
1815};
1816
1817static const unsigned int can_clk_mux[] = {
1818 CAN_CLK_MARK,
1819};
1820
1821/* - CAN FD --------------------------------------------------------------- */
1822static const unsigned int canfd0_data_a_pins[] = {
1823 /* TX, RX */
1824 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1825};
1826
1827static const unsigned int canfd0_data_a_mux[] = {
1828 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
1829};
1830
1831static const unsigned int canfd0_data_b_pins[] = {
1832 /* TX, RX */
1833 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1834};
1835
1836static const unsigned int canfd0_data_b_mux[] = {
1837 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
1838};
1839
1840static const unsigned int canfd1_data_pins[] = {
1841 /* TX, RX */
1842 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1843};
1844
1845static const unsigned int canfd1_data_mux[] = {
1846 CANFD1_TX_MARK, CANFD1_RX_MARK,
1847};
1848
Biju Das0a362702020-10-28 10:34:24 +0000[diff] [blame]1849#ifdef CONFIG_PINCTRL_PFC_R8A77965
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1850/* - DRIF0 --------------------------------------------------------------- */
1851static const unsigned int drif0_ctrl_a_pins[] = {
1852 /* CLK, SYNC */
1853 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1854};
1855
1856static const unsigned int drif0_ctrl_a_mux[] = {
1857 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1858};
1859
1860static const unsigned int drif0_data0_a_pins[] = {
1861 /* D0 */
1862 RCAR_GP_PIN(6, 10),
1863};
1864
1865static const unsigned int drif0_data0_a_mux[] = {
1866 RIF0_D0_A_MARK,
1867};
1868
1869static const unsigned int drif0_data1_a_pins[] = {
1870 /* D1 */
1871 RCAR_GP_PIN(6, 7),
1872};
1873
1874static const unsigned int drif0_data1_a_mux[] = {
1875 RIF0_D1_A_MARK,
1876};
1877
1878static const unsigned int drif0_ctrl_b_pins[] = {
1879 /* CLK, SYNC */
1880 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1881};
1882
1883static const unsigned int drif0_ctrl_b_mux[] = {
1884 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1885};
1886
1887static const unsigned int drif0_data0_b_pins[] = {
1888 /* D0 */
1889 RCAR_GP_PIN(5, 1),
1890};
1891
1892static const unsigned int drif0_data0_b_mux[] = {
1893 RIF0_D0_B_MARK,
1894};
1895
1896static const unsigned int drif0_data1_b_pins[] = {
1897 /* D1 */
1898 RCAR_GP_PIN(5, 2),
1899};
1900
1901static const unsigned int drif0_data1_b_mux[] = {
1902 RIF0_D1_B_MARK,
1903};
1904
1905static const unsigned int drif0_ctrl_c_pins[] = {
1906 /* CLK, SYNC */
1907 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1908};
1909
1910static const unsigned int drif0_ctrl_c_mux[] = {
1911 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1912};
1913
1914static const unsigned int drif0_data0_c_pins[] = {
1915 /* D0 */
1916 RCAR_GP_PIN(5, 13),
1917};
1918
1919static const unsigned int drif0_data0_c_mux[] = {
1920 RIF0_D0_C_MARK,
1921};
1922
1923static const unsigned int drif0_data1_c_pins[] = {
1924 /* D1 */
1925 RCAR_GP_PIN(5, 14),
1926};
1927
1928static const unsigned int drif0_data1_c_mux[] = {
1929 RIF0_D1_C_MARK,
1930};
1931
1932/* - DRIF1 --------------------------------------------------------------- */
1933static const unsigned int drif1_ctrl_a_pins[] = {
1934 /* CLK, SYNC */
1935 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1936};
1937
1938static const unsigned int drif1_ctrl_a_mux[] = {
1939 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1940};
1941
1942static const unsigned int drif1_data0_a_pins[] = {
1943 /* D0 */
1944 RCAR_GP_PIN(6, 19),
1945};
1946
1947static const unsigned int drif1_data0_a_mux[] = {
1948 RIF1_D0_A_MARK,
1949};
1950
1951static const unsigned int drif1_data1_a_pins[] = {
1952 /* D1 */
1953 RCAR_GP_PIN(6, 20),
1954};
1955
1956static const unsigned int drif1_data1_a_mux[] = {
1957 RIF1_D1_A_MARK,
1958};
1959
1960static const unsigned int drif1_ctrl_b_pins[] = {
1961 /* CLK, SYNC */
1962 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1963};
1964
1965static const unsigned int drif1_ctrl_b_mux[] = {
1966 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1967};
1968
1969static const unsigned int drif1_data0_b_pins[] = {
1970 /* D0 */
1971 RCAR_GP_PIN(5, 7),
1972};
1973
1974static const unsigned int drif1_data0_b_mux[] = {
1975 RIF1_D0_B_MARK,
1976};
1977
1978static const unsigned int drif1_data1_b_pins[] = {
1979 /* D1 */
1980 RCAR_GP_PIN(5, 8),
1981};
1982
1983static const unsigned int drif1_data1_b_mux[] = {
1984 RIF1_D1_B_MARK,
1985};
1986
1987static const unsigned int drif1_ctrl_c_pins[] = {
1988 /* CLK, SYNC */
1989 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1990};
1991
1992static const unsigned int drif1_ctrl_c_mux[] = {
1993 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1994};
1995
1996static const unsigned int drif1_data0_c_pins[] = {
1997 /* D0 */
1998 RCAR_GP_PIN(5, 6),
1999};
2000
2001static const unsigned int drif1_data0_c_mux[] = {
2002 RIF1_D0_C_MARK,
2003};
2004
2005static const unsigned int drif1_data1_c_pins[] = {
2006 /* D1 */
2007 RCAR_GP_PIN(5, 10),
2008};
2009
2010static const unsigned int drif1_data1_c_mux[] = {
2011 RIF1_D1_C_MARK,
2012};
2013
2014/* - DRIF2 --------------------------------------------------------------- */
2015static const unsigned int drif2_ctrl_a_pins[] = {
2016 /* CLK, SYNC */
2017 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2018};
2019
2020static const unsigned int drif2_ctrl_a_mux[] = {
2021 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
2022};
2023
2024static const unsigned int drif2_data0_a_pins[] = {
2025 /* D0 */
2026 RCAR_GP_PIN(6, 7),
2027};
2028
2029static const unsigned int drif2_data0_a_mux[] = {
2030 RIF2_D0_A_MARK,
2031};
2032
2033static const unsigned int drif2_data1_a_pins[] = {
2034 /* D1 */
2035 RCAR_GP_PIN(6, 10),
2036};
2037
2038static const unsigned int drif2_data1_a_mux[] = {
2039 RIF2_D1_A_MARK,
2040};
2041
2042static const unsigned int drif2_ctrl_b_pins[] = {
2043 /* CLK, SYNC */
2044 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
2045};
2046
2047static const unsigned int drif2_ctrl_b_mux[] = {
2048 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
2049};
2050
2051static const unsigned int drif2_data0_b_pins[] = {
2052 /* D0 */
2053 RCAR_GP_PIN(6, 30),
2054};
2055
2056static const unsigned int drif2_data0_b_mux[] = {
2057 RIF2_D0_B_MARK,
2058};
2059
2060static const unsigned int drif2_data1_b_pins[] = {
2061 /* D1 */
2062 RCAR_GP_PIN(6, 31),
2063};
2064
2065static const unsigned int drif2_data1_b_mux[] = {
2066 RIF2_D1_B_MARK,
2067};
2068
2069/* - DRIF3 --------------------------------------------------------------- */
2070static const unsigned int drif3_ctrl_a_pins[] = {
2071 /* CLK, SYNC */
2072 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2073};
2074
2075static const unsigned int drif3_ctrl_a_mux[] = {
2076 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
2077};
2078
2079static const unsigned int drif3_data0_a_pins[] = {
2080 /* D0 */
2081 RCAR_GP_PIN(6, 19),
2082};
2083
2084static const unsigned int drif3_data0_a_mux[] = {
2085 RIF3_D0_A_MARK,
2086};
2087
2088static const unsigned int drif3_data1_a_pins[] = {
2089 /* D1 */
2090 RCAR_GP_PIN(6, 20),
2091};
2092
2093static const unsigned int drif3_data1_a_mux[] = {
2094 RIF3_D1_A_MARK,
2095};
2096
2097static const unsigned int drif3_ctrl_b_pins[] = {
2098 /* CLK, SYNC */
2099 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2100};
2101
2102static const unsigned int drif3_ctrl_b_mux[] = {
2103 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
2104};
2105
2106static const unsigned int drif3_data0_b_pins[] = {
2107 /* D0 */
2108 RCAR_GP_PIN(6, 28),
2109};
2110
2111static const unsigned int drif3_data0_b_mux[] = {
2112 RIF3_D0_B_MARK,
2113};
2114
2115static const unsigned int drif3_data1_b_pins[] = {
2116 /* D1 */
2117 RCAR_GP_PIN(6, 29),
2118};
2119
2120static const unsigned int drif3_data1_b_mux[] = {
2121 RIF3_D1_B_MARK,
2122};
Biju Das0a362702020-10-28 10:34:24 +0000[diff] [blame]2123#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]2124
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2125/* - DU --------------------------------------------------------------------- */
2126static const unsigned int du_rgb666_pins[] = {
2127 /* R[7:2], G[7:2], B[7:2] */
2128 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2129 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2130 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2131 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2132 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2133 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2134};
2135
2136static const unsigned int du_rgb666_mux[] = {
2137 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2138 DU_DR3_MARK, DU_DR2_MARK,
2139 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2140 DU_DG3_MARK, DU_DG2_MARK,
2141 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2142 DU_DB3_MARK, DU_DB2_MARK,
2143};
2144
2145static const unsigned int du_rgb888_pins[] = {
2146 /* R[7:0], G[7:0], B[7:0] */
2147 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2148 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2149 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
2150 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2151 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2152 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2153 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2154 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2155 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2156};
2157
2158static const unsigned int du_rgb888_mux[] = {
2159 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2160 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2161 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2162 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2163 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2164 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2165};
2166
2167static const unsigned int du_clk_out_0_pins[] = {
2168 /* CLKOUT */
2169 RCAR_GP_PIN(1, 27),
2170};
2171
2172static const unsigned int du_clk_out_0_mux[] = {
2173 DU_DOTCLKOUT0_MARK
2174};
2175
2176static const unsigned int du_clk_out_1_pins[] = {
2177 /* CLKOUT */
2178 RCAR_GP_PIN(2, 3),
2179};
2180
2181static const unsigned int du_clk_out_1_mux[] = {
2182 DU_DOTCLKOUT1_MARK
2183};
2184
2185static const unsigned int du_sync_pins[] = {
2186 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2187 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2188};
2189
2190static const unsigned int du_sync_mux[] = {
2191 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2192};
2193
2194static const unsigned int du_oddf_pins[] = {
2195 /* EXDISP/EXODDF/EXCDE */
2196 RCAR_GP_PIN(2, 2),
2197};
2198
2199static const unsigned int du_oddf_mux[] = {
2200 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2201};
2202
2203static const unsigned int du_cde_pins[] = {
2204 /* CDE */
2205 RCAR_GP_PIN(2, 0),
2206};
2207
2208static const unsigned int du_cde_mux[] = {
2209 DU_CDE_MARK,
2210};
2211
2212static const unsigned int du_disp_pins[] = {
2213 /* DISP */
2214 RCAR_GP_PIN(2, 1),
2215};
2216
2217static const unsigned int du_disp_mux[] = {
2218 DU_DISP_MARK,
2219};
2220
2221/* - HSCIF0 ----------------------------------------------------------------- */
2222static const unsigned int hscif0_data_pins[] = {
2223 /* RX, TX */
2224 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2225};
2226
2227static const unsigned int hscif0_data_mux[] = {
2228 HRX0_MARK, HTX0_MARK,
2229};
2230
2231static const unsigned int hscif0_clk_pins[] = {
2232 /* SCK */
2233 RCAR_GP_PIN(5, 12),
2234};
2235
2236static const unsigned int hscif0_clk_mux[] = {
2237 HSCK0_MARK,
2238};
2239
2240static const unsigned int hscif0_ctrl_pins[] = {
2241 /* RTS, CTS */
2242 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2243};
2244
2245static const unsigned int hscif0_ctrl_mux[] = {
2246 HRTS0_N_MARK, HCTS0_N_MARK,
2247};
2248
2249/* - HSCIF1 ----------------------------------------------------------------- */
2250static const unsigned int hscif1_data_a_pins[] = {
2251 /* RX, TX */
2252 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2253};
2254
2255static const unsigned int hscif1_data_a_mux[] = {
2256 HRX1_A_MARK, HTX1_A_MARK,
2257};
2258
2259static const unsigned int hscif1_clk_a_pins[] = {
2260 /* SCK */
2261 RCAR_GP_PIN(6, 21),
2262};
2263
2264static const unsigned int hscif1_clk_a_mux[] = {
2265 HSCK1_A_MARK,
2266};
2267
2268static const unsigned int hscif1_ctrl_a_pins[] = {
2269 /* RTS, CTS */
2270 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2271};
2272
2273static const unsigned int hscif1_ctrl_a_mux[] = {
2274 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2275};
2276
2277static const unsigned int hscif1_data_b_pins[] = {
2278 /* RX, TX */
2279 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2280};
2281
2282static const unsigned int hscif1_data_b_mux[] = {
2283 HRX1_B_MARK, HTX1_B_MARK,
2284};
2285
2286static const unsigned int hscif1_clk_b_pins[] = {
2287 /* SCK */
2288 RCAR_GP_PIN(5, 0),
2289};
2290
2291static const unsigned int hscif1_clk_b_mux[] = {
2292 HSCK1_B_MARK,
2293};
2294
2295static const unsigned int hscif1_ctrl_b_pins[] = {
2296 /* RTS, CTS */
2297 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2298};
2299
2300static const unsigned int hscif1_ctrl_b_mux[] = {
2301 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2302};
2303
2304/* - HSCIF2 ----------------------------------------------------------------- */
2305static const unsigned int hscif2_data_a_pins[] = {
2306 /* RX, TX */
2307 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2308};
2309
2310static const unsigned int hscif2_data_a_mux[] = {
2311 HRX2_A_MARK, HTX2_A_MARK,
2312};
2313
2314static const unsigned int hscif2_clk_a_pins[] = {
2315 /* SCK */
2316 RCAR_GP_PIN(6, 10),
2317};
2318
2319static const unsigned int hscif2_clk_a_mux[] = {
2320 HSCK2_A_MARK,
2321};
2322
2323static const unsigned int hscif2_ctrl_a_pins[] = {
2324 /* RTS, CTS */
2325 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2326};
2327
2328static const unsigned int hscif2_ctrl_a_mux[] = {
2329 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2330};
2331
2332static const unsigned int hscif2_data_b_pins[] = {
2333 /* RX, TX */
2334 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2335};
2336
2337static const unsigned int hscif2_data_b_mux[] = {
2338 HRX2_B_MARK, HTX2_B_MARK,
2339};
2340
2341static const unsigned int hscif2_clk_b_pins[] = {
2342 /* SCK */
2343 RCAR_GP_PIN(6, 21),
2344};
2345
2346static const unsigned int hscif2_clk_b_mux[] = {
2347 HSCK2_B_MARK,
2348};
2349
2350static const unsigned int hscif2_ctrl_b_pins[] = {
2351 /* RTS, CTS */
2352 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2353};
2354
2355static const unsigned int hscif2_ctrl_b_mux[] = {
2356 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2357};
2358
2359static const unsigned int hscif2_data_c_pins[] = {
2360 /* RX, TX */
2361 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2362};
2363
2364static const unsigned int hscif2_data_c_mux[] = {
2365 HRX2_C_MARK, HTX2_C_MARK,
2366};
2367
2368static const unsigned int hscif2_clk_c_pins[] = {
2369 /* SCK */
2370 RCAR_GP_PIN(6, 24),
2371};
2372
2373static const unsigned int hscif2_clk_c_mux[] = {
2374 HSCK2_C_MARK,
2375};
2376
2377static const unsigned int hscif2_ctrl_c_pins[] = {
2378 /* RTS, CTS */
2379 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2380};
2381
2382static const unsigned int hscif2_ctrl_c_mux[] = {
2383 HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2384};
2385
2386/* - HSCIF3 ----------------------------------------------------------------- */
2387static const unsigned int hscif3_data_a_pins[] = {
2388 /* RX, TX */
2389 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2390};
2391
2392static const unsigned int hscif3_data_a_mux[] = {
2393 HRX3_A_MARK, HTX3_A_MARK,
2394};
2395
2396static const unsigned int hscif3_clk_pins[] = {
2397 /* SCK */
2398 RCAR_GP_PIN(1, 22),
2399};
2400
2401static const unsigned int hscif3_clk_mux[] = {
2402 HSCK3_MARK,
2403};
2404
2405static const unsigned int hscif3_ctrl_pins[] = {
2406 /* RTS, CTS */
2407 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2408};
2409
2410static const unsigned int hscif3_ctrl_mux[] = {
2411 HRTS3_N_MARK, HCTS3_N_MARK,
2412};
2413
2414static const unsigned int hscif3_data_b_pins[] = {
2415 /* RX, TX */
2416 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2417};
2418
2419static const unsigned int hscif3_data_b_mux[] = {
2420 HRX3_B_MARK, HTX3_B_MARK,
2421};
2422
2423static const unsigned int hscif3_data_c_pins[] = {
2424 /* RX, TX */
2425 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2426};
2427
2428static const unsigned int hscif3_data_c_mux[] = {
2429 HRX3_C_MARK, HTX3_C_MARK,
2430};
2431
2432static const unsigned int hscif3_data_d_pins[] = {
2433 /* RX, TX */
2434 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2435};
2436
2437static const unsigned int hscif3_data_d_mux[] = {
2438 HRX3_D_MARK, HTX3_D_MARK,
2439};
2440
2441/* - HSCIF4 ----------------------------------------------------------------- */
2442static const unsigned int hscif4_data_a_pins[] = {
2443 /* RX, TX */
2444 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2445};
2446
2447static const unsigned int hscif4_data_a_mux[] = {
2448 HRX4_A_MARK, HTX4_A_MARK,
2449};
2450
2451static const unsigned int hscif4_clk_pins[] = {
2452 /* SCK */
2453 RCAR_GP_PIN(1, 11),
2454};
2455
2456static const unsigned int hscif4_clk_mux[] = {
2457 HSCK4_MARK,
2458};
2459
2460static const unsigned int hscif4_ctrl_pins[] = {
2461 /* RTS, CTS */
2462 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2463};
2464
2465static const unsigned int hscif4_ctrl_mux[] = {
2466 HRTS4_N_MARK, HCTS4_N_MARK,
2467};
2468
2469static const unsigned int hscif4_data_b_pins[] = {
2470 /* RX, TX */
2471 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2472};
2473
2474static const unsigned int hscif4_data_b_mux[] = {
2475 HRX4_B_MARK, HTX4_B_MARK,
2476};
2477
2478/* - I2C -------------------------------------------------------------------- */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2479static const unsigned int i2c0_pins[] = {
2480 /* SCL, SDA */
2481 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2482};
2483
2484static const unsigned int i2c0_mux[] = {
2485 SCL0_MARK, SDA0_MARK,
2486};
2487
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2488static const unsigned int i2c1_a_pins[] = {
2489 /* SDA, SCL */
2490 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2491};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2492
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2493static const unsigned int i2c1_a_mux[] = {
2494 SDA1_A_MARK, SCL1_A_MARK,
2495};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2496
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2497static const unsigned int i2c1_b_pins[] = {
2498 /* SDA, SCL */
2499 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2500};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2501
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2502static const unsigned int i2c1_b_mux[] = {
2503 SDA1_B_MARK, SCL1_B_MARK,
2504};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2505
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2506static const unsigned int i2c2_a_pins[] = {
2507 /* SDA, SCL */
2508 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2509};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2510
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2511static const unsigned int i2c2_a_mux[] = {
2512 SDA2_A_MARK, SCL2_A_MARK,
2513};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2514
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2515static const unsigned int i2c2_b_pins[] = {
2516 /* SDA, SCL */
2517 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2518};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2519
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2520static const unsigned int i2c2_b_mux[] = {
2521 SDA2_B_MARK, SCL2_B_MARK,
2522};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2523
2524static const unsigned int i2c3_pins[] = {
2525 /* SCL, SDA */
2526 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2527};
2528
2529static const unsigned int i2c3_mux[] = {
2530 SCL3_MARK, SDA3_MARK,
2531};
2532
2533static const unsigned int i2c5_pins[] = {
2534 /* SCL, SDA */
2535 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
2536};
2537
2538static const unsigned int i2c5_mux[] = {
2539 SCL5_MARK, SDA5_MARK,
2540};
2541
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2542static const unsigned int i2c6_a_pins[] = {
2543 /* SDA, SCL */
2544 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2545};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2546
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2547static const unsigned int i2c6_a_mux[] = {
2548 SDA6_A_MARK, SCL6_A_MARK,
2549};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2550
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2551static const unsigned int i2c6_b_pins[] = {
2552 /* SDA, SCL */
2553 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2554};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2555
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2556static const unsigned int i2c6_b_mux[] = {
2557 SDA6_B_MARK, SCL6_B_MARK,
2558};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2559
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2560static const unsigned int i2c6_c_pins[] = {
2561 /* SDA, SCL */
2562 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2563};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2564
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2565static const unsigned int i2c6_c_mux[] = {
2566 SDA6_C_MARK, SCL6_C_MARK,
2567};
2568
2569/* - INTC-EX ---------------------------------------------------------------- */
2570static const unsigned int intc_ex_irq0_pins[] = {
2571 /* IRQ0 */
2572 RCAR_GP_PIN(2, 0),
2573};
2574static const unsigned int intc_ex_irq0_mux[] = {
2575 IRQ0_MARK,
2576};
2577static const unsigned int intc_ex_irq1_pins[] = {
2578 /* IRQ1 */
2579 RCAR_GP_PIN(2, 1),
2580};
2581static const unsigned int intc_ex_irq1_mux[] = {
2582 IRQ1_MARK,
2583};
2584static const unsigned int intc_ex_irq2_pins[] = {
2585 /* IRQ2 */
2586 RCAR_GP_PIN(2, 2),
2587};
2588static const unsigned int intc_ex_irq2_mux[] = {
2589 IRQ2_MARK,
2590};
2591static const unsigned int intc_ex_irq3_pins[] = {
2592 /* IRQ3 */
2593 RCAR_GP_PIN(2, 3),
2594};
2595static const unsigned int intc_ex_irq3_mux[] = {
2596 IRQ3_MARK,
2597};
2598static const unsigned int intc_ex_irq4_pins[] = {
2599 /* IRQ4 */
2600 RCAR_GP_PIN(2, 4),
2601};
2602static const unsigned int intc_ex_irq4_mux[] = {
2603 IRQ4_MARK,
2604};
2605static const unsigned int intc_ex_irq5_pins[] = {
2606 /* IRQ5 */
2607 RCAR_GP_PIN(2, 5),
2608};
2609static const unsigned int intc_ex_irq5_mux[] = {
2610 IRQ5_MARK,
2611};
2612
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]2613#ifdef CONFIG_PINCTRL_PFC_R8A77965
2614/* - MLB+ ------------------------------------------------------------------- */
2615static const unsigned int mlb_3pin_pins[] = {
2616 RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
2617};
2618static const unsigned int mlb_3pin_mux[] = {
2619 MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
2620};
2621#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
2622
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2623/* - MSIOF0 ----------------------------------------------------------------- */
2624static const unsigned int msiof0_clk_pins[] = {
2625 /* SCK */
2626 RCAR_GP_PIN(5, 17),
2627};
2628static const unsigned int msiof0_clk_mux[] = {
2629 MSIOF0_SCK_MARK,
2630};
2631static const unsigned int msiof0_sync_pins[] = {
2632 /* SYNC */
2633 RCAR_GP_PIN(5, 18),
2634};
2635static const unsigned int msiof0_sync_mux[] = {
2636 MSIOF0_SYNC_MARK,
2637};
2638static const unsigned int msiof0_ss1_pins[] = {
2639 /* SS1 */
2640 RCAR_GP_PIN(5, 19),
2641};
2642static const unsigned int msiof0_ss1_mux[] = {
2643 MSIOF0_SS1_MARK,
2644};
2645static const unsigned int msiof0_ss2_pins[] = {
2646 /* SS2 */
2647 RCAR_GP_PIN(5, 21),
2648};
2649static const unsigned int msiof0_ss2_mux[] = {
2650 MSIOF0_SS2_MARK,
2651};
2652static const unsigned int msiof0_txd_pins[] = {
2653 /* TXD */
2654 RCAR_GP_PIN(5, 20),
2655};
2656static const unsigned int msiof0_txd_mux[] = {
2657 MSIOF0_TXD_MARK,
2658};
2659static const unsigned int msiof0_rxd_pins[] = {
2660 /* RXD */
2661 RCAR_GP_PIN(5, 22),
2662};
2663static const unsigned int msiof0_rxd_mux[] = {
2664 MSIOF0_RXD_MARK,
2665};
2666/* - MSIOF1 ----------------------------------------------------------------- */
2667static const unsigned int msiof1_clk_a_pins[] = {
2668 /* SCK */
2669 RCAR_GP_PIN(6, 8),
2670};
2671static const unsigned int msiof1_clk_a_mux[] = {
2672 MSIOF1_SCK_A_MARK,
2673};
2674static const unsigned int msiof1_sync_a_pins[] = {
2675 /* SYNC */
2676 RCAR_GP_PIN(6, 9),
2677};
2678static const unsigned int msiof1_sync_a_mux[] = {
2679 MSIOF1_SYNC_A_MARK,
2680};
2681static const unsigned int msiof1_ss1_a_pins[] = {
2682 /* SS1 */
2683 RCAR_GP_PIN(6, 5),
2684};
2685static const unsigned int msiof1_ss1_a_mux[] = {
2686 MSIOF1_SS1_A_MARK,
2687};
2688static const unsigned int msiof1_ss2_a_pins[] = {
2689 /* SS2 */
2690 RCAR_GP_PIN(6, 6),
2691};
2692static const unsigned int msiof1_ss2_a_mux[] = {
2693 MSIOF1_SS2_A_MARK,
2694};
2695static const unsigned int msiof1_txd_a_pins[] = {
2696 /* TXD */
2697 RCAR_GP_PIN(6, 7),
2698};
2699static const unsigned int msiof1_txd_a_mux[] = {
2700 MSIOF1_TXD_A_MARK,
2701};
2702static const unsigned int msiof1_rxd_a_pins[] = {
2703 /* RXD */
2704 RCAR_GP_PIN(6, 10),
2705};
2706static const unsigned int msiof1_rxd_a_mux[] = {
2707 MSIOF1_RXD_A_MARK,
2708};
2709static const unsigned int msiof1_clk_b_pins[] = {
2710 /* SCK */
2711 RCAR_GP_PIN(5, 9),
2712};
2713static const unsigned int msiof1_clk_b_mux[] = {
2714 MSIOF1_SCK_B_MARK,
2715};
2716static const unsigned int msiof1_sync_b_pins[] = {
2717 /* SYNC */
2718 RCAR_GP_PIN(5, 3),
2719};
2720static const unsigned int msiof1_sync_b_mux[] = {
2721 MSIOF1_SYNC_B_MARK,
2722};
2723static const unsigned int msiof1_ss1_b_pins[] = {
2724 /* SS1 */
2725 RCAR_GP_PIN(5, 4),
2726};
2727static const unsigned int msiof1_ss1_b_mux[] = {
2728 MSIOF1_SS1_B_MARK,
2729};
2730static const unsigned int msiof1_ss2_b_pins[] = {
2731 /* SS2 */
2732 RCAR_GP_PIN(5, 0),
2733};
2734static const unsigned int msiof1_ss2_b_mux[] = {
2735 MSIOF1_SS2_B_MARK,
2736};
2737static const unsigned int msiof1_txd_b_pins[] = {
2738 /* TXD */
2739 RCAR_GP_PIN(5, 8),
2740};
2741static const unsigned int msiof1_txd_b_mux[] = {
2742 MSIOF1_TXD_B_MARK,
2743};
2744static const unsigned int msiof1_rxd_b_pins[] = {
2745 /* RXD */
2746 RCAR_GP_PIN(5, 7),
2747};
2748static const unsigned int msiof1_rxd_b_mux[] = {
2749 MSIOF1_RXD_B_MARK,
2750};
2751static const unsigned int msiof1_clk_c_pins[] = {
2752 /* SCK */
2753 RCAR_GP_PIN(6, 17),
2754};
2755static const unsigned int msiof1_clk_c_mux[] = {
2756 MSIOF1_SCK_C_MARK,
2757};
2758static const unsigned int msiof1_sync_c_pins[] = {
2759 /* SYNC */
2760 RCAR_GP_PIN(6, 18),
2761};
2762static const unsigned int msiof1_sync_c_mux[] = {
2763 MSIOF1_SYNC_C_MARK,
2764};
2765static const unsigned int msiof1_ss1_c_pins[] = {
2766 /* SS1 */
2767 RCAR_GP_PIN(6, 21),
2768};
2769static const unsigned int msiof1_ss1_c_mux[] = {
2770 MSIOF1_SS1_C_MARK,
2771};
2772static const unsigned int msiof1_ss2_c_pins[] = {
2773 /* SS2 */
2774 RCAR_GP_PIN(6, 27),
2775};
2776static const unsigned int msiof1_ss2_c_mux[] = {
2777 MSIOF1_SS2_C_MARK,
2778};
2779static const unsigned int msiof1_txd_c_pins[] = {
2780 /* TXD */
2781 RCAR_GP_PIN(6, 20),
2782};
2783static const unsigned int msiof1_txd_c_mux[] = {
2784 MSIOF1_TXD_C_MARK,
2785};
2786static const unsigned int msiof1_rxd_c_pins[] = {
2787 /* RXD */
2788 RCAR_GP_PIN(6, 19),
2789};
2790static const unsigned int msiof1_rxd_c_mux[] = {
2791 MSIOF1_RXD_C_MARK,
2792};
2793static const unsigned int msiof1_clk_d_pins[] = {
2794 /* SCK */
2795 RCAR_GP_PIN(5, 12),
2796};
2797static const unsigned int msiof1_clk_d_mux[] = {
2798 MSIOF1_SCK_D_MARK,
2799};
2800static const unsigned int msiof1_sync_d_pins[] = {
2801 /* SYNC */
2802 RCAR_GP_PIN(5, 15),
2803};
2804static const unsigned int msiof1_sync_d_mux[] = {
2805 MSIOF1_SYNC_D_MARK,
2806};
2807static const unsigned int msiof1_ss1_d_pins[] = {
2808 /* SS1 */
2809 RCAR_GP_PIN(5, 16),
2810};
2811static const unsigned int msiof1_ss1_d_mux[] = {
2812 MSIOF1_SS1_D_MARK,
2813};
2814static const unsigned int msiof1_ss2_d_pins[] = {
2815 /* SS2 */
2816 RCAR_GP_PIN(5, 21),
2817};
2818static const unsigned int msiof1_ss2_d_mux[] = {
2819 MSIOF1_SS2_D_MARK,
2820};
2821static const unsigned int msiof1_txd_d_pins[] = {
2822 /* TXD */
2823 RCAR_GP_PIN(5, 14),
2824};
2825static const unsigned int msiof1_txd_d_mux[] = {
2826 MSIOF1_TXD_D_MARK,
2827};
2828static const unsigned int msiof1_rxd_d_pins[] = {
2829 /* RXD */
2830 RCAR_GP_PIN(5, 13),
2831};
2832static const unsigned int msiof1_rxd_d_mux[] = {
2833 MSIOF1_RXD_D_MARK,
2834};
2835static const unsigned int msiof1_clk_e_pins[] = {
2836 /* SCK */
2837 RCAR_GP_PIN(3, 0),
2838};
2839static const unsigned int msiof1_clk_e_mux[] = {
2840 MSIOF1_SCK_E_MARK,
2841};
2842static const unsigned int msiof1_sync_e_pins[] = {
2843 /* SYNC */
2844 RCAR_GP_PIN(3, 1),
2845};
2846static const unsigned int msiof1_sync_e_mux[] = {
2847 MSIOF1_SYNC_E_MARK,
2848};
2849static const unsigned int msiof1_ss1_e_pins[] = {
2850 /* SS1 */
2851 RCAR_GP_PIN(3, 4),
2852};
2853static const unsigned int msiof1_ss1_e_mux[] = {
2854 MSIOF1_SS1_E_MARK,
2855};
2856static const unsigned int msiof1_ss2_e_pins[] = {
2857 /* SS2 */
2858 RCAR_GP_PIN(3, 5),
2859};
2860static const unsigned int msiof1_ss2_e_mux[] = {
2861 MSIOF1_SS2_E_MARK,
2862};
2863static const unsigned int msiof1_txd_e_pins[] = {
2864 /* TXD */
2865 RCAR_GP_PIN(3, 3),
2866};
2867static const unsigned int msiof1_txd_e_mux[] = {
2868 MSIOF1_TXD_E_MARK,
2869};
2870static const unsigned int msiof1_rxd_e_pins[] = {
2871 /* RXD */
2872 RCAR_GP_PIN(3, 2),
2873};
2874static const unsigned int msiof1_rxd_e_mux[] = {
2875 MSIOF1_RXD_E_MARK,
2876};
2877static const unsigned int msiof1_clk_f_pins[] = {
2878 /* SCK */
2879 RCAR_GP_PIN(5, 23),
2880};
2881static const unsigned int msiof1_clk_f_mux[] = {
2882 MSIOF1_SCK_F_MARK,
2883};
2884static const unsigned int msiof1_sync_f_pins[] = {
2885 /* SYNC */
2886 RCAR_GP_PIN(5, 24),
2887};
2888static const unsigned int msiof1_sync_f_mux[] = {
2889 MSIOF1_SYNC_F_MARK,
2890};
2891static const unsigned int msiof1_ss1_f_pins[] = {
2892 /* SS1 */
2893 RCAR_GP_PIN(6, 1),
2894};
2895static const unsigned int msiof1_ss1_f_mux[] = {
2896 MSIOF1_SS1_F_MARK,
2897};
2898static const unsigned int msiof1_ss2_f_pins[] = {
2899 /* SS2 */
2900 RCAR_GP_PIN(6, 2),
2901};
2902static const unsigned int msiof1_ss2_f_mux[] = {
2903 MSIOF1_SS2_F_MARK,
2904};
2905static const unsigned int msiof1_txd_f_pins[] = {
2906 /* TXD */
2907 RCAR_GP_PIN(6, 0),
2908};
2909static const unsigned int msiof1_txd_f_mux[] = {
2910 MSIOF1_TXD_F_MARK,
2911};
2912static const unsigned int msiof1_rxd_f_pins[] = {
2913 /* RXD */
2914 RCAR_GP_PIN(5, 25),
2915};
2916static const unsigned int msiof1_rxd_f_mux[] = {
2917 MSIOF1_RXD_F_MARK,
2918};
2919static const unsigned int msiof1_clk_g_pins[] = {
2920 /* SCK */
2921 RCAR_GP_PIN(3, 6),
2922};
2923static const unsigned int msiof1_clk_g_mux[] = {
2924 MSIOF1_SCK_G_MARK,
2925};
2926static const unsigned int msiof1_sync_g_pins[] = {
2927 /* SYNC */
2928 RCAR_GP_PIN(3, 7),
2929};
2930static const unsigned int msiof1_sync_g_mux[] = {
2931 MSIOF1_SYNC_G_MARK,
2932};
2933static const unsigned int msiof1_ss1_g_pins[] = {
2934 /* SS1 */
2935 RCAR_GP_PIN(3, 10),
2936};
2937static const unsigned int msiof1_ss1_g_mux[] = {
2938 MSIOF1_SS1_G_MARK,
2939};
2940static const unsigned int msiof1_ss2_g_pins[] = {
2941 /* SS2 */
2942 RCAR_GP_PIN(3, 11),
2943};
2944static const unsigned int msiof1_ss2_g_mux[] = {
2945 MSIOF1_SS2_G_MARK,
2946};
2947static const unsigned int msiof1_txd_g_pins[] = {
2948 /* TXD */
2949 RCAR_GP_PIN(3, 9),
2950};
2951static const unsigned int msiof1_txd_g_mux[] = {
2952 MSIOF1_TXD_G_MARK,
2953};
2954static const unsigned int msiof1_rxd_g_pins[] = {
2955 /* RXD */
2956 RCAR_GP_PIN(3, 8),
2957};
2958static const unsigned int msiof1_rxd_g_mux[] = {
2959 MSIOF1_RXD_G_MARK,
2960};
2961/* - MSIOF2 ----------------------------------------------------------------- */
2962static const unsigned int msiof2_clk_a_pins[] = {
2963 /* SCK */
2964 RCAR_GP_PIN(1, 9),
2965};
2966static const unsigned int msiof2_clk_a_mux[] = {
2967 MSIOF2_SCK_A_MARK,
2968};
2969static const unsigned int msiof2_sync_a_pins[] = {
2970 /* SYNC */
2971 RCAR_GP_PIN(1, 8),
2972};
2973static const unsigned int msiof2_sync_a_mux[] = {
2974 MSIOF2_SYNC_A_MARK,
2975};
2976static const unsigned int msiof2_ss1_a_pins[] = {
2977 /* SS1 */
2978 RCAR_GP_PIN(1, 6),
2979};
2980static const unsigned int msiof2_ss1_a_mux[] = {
2981 MSIOF2_SS1_A_MARK,
2982};
2983static const unsigned int msiof2_ss2_a_pins[] = {
2984 /* SS2 */
2985 RCAR_GP_PIN(1, 7),
2986};
2987static const unsigned int msiof2_ss2_a_mux[] = {
2988 MSIOF2_SS2_A_MARK,
2989};
2990static const unsigned int msiof2_txd_a_pins[] = {
2991 /* TXD */
2992 RCAR_GP_PIN(1, 11),
2993};
2994static const unsigned int msiof2_txd_a_mux[] = {
2995 MSIOF2_TXD_A_MARK,
2996};
2997static const unsigned int msiof2_rxd_a_pins[] = {
2998 /* RXD */
2999 RCAR_GP_PIN(1, 10),
3000};
3001static const unsigned int msiof2_rxd_a_mux[] = {
3002 MSIOF2_RXD_A_MARK,
3003};
3004static const unsigned int msiof2_clk_b_pins[] = {
3005 /* SCK */
3006 RCAR_GP_PIN(0, 4),
3007};
3008static const unsigned int msiof2_clk_b_mux[] = {
3009 MSIOF2_SCK_B_MARK,
3010};
3011static const unsigned int msiof2_sync_b_pins[] = {
3012 /* SYNC */
3013 RCAR_GP_PIN(0, 5),
3014};
3015static const unsigned int msiof2_sync_b_mux[] = {
3016 MSIOF2_SYNC_B_MARK,
3017};
3018static const unsigned int msiof2_ss1_b_pins[] = {
3019 /* SS1 */
3020 RCAR_GP_PIN(0, 0),
3021};
3022static const unsigned int msiof2_ss1_b_mux[] = {
3023 MSIOF2_SS1_B_MARK,
3024};
3025static const unsigned int msiof2_ss2_b_pins[] = {
3026 /* SS2 */
3027 RCAR_GP_PIN(0, 1),
3028};
3029static const unsigned int msiof2_ss2_b_mux[] = {
3030 MSIOF2_SS2_B_MARK,
3031};
3032static const unsigned int msiof2_txd_b_pins[] = {
3033 /* TXD */
3034 RCAR_GP_PIN(0, 7),
3035};
3036static const unsigned int msiof2_txd_b_mux[] = {
3037 MSIOF2_TXD_B_MARK,
3038};
3039static const unsigned int msiof2_rxd_b_pins[] = {
3040 /* RXD */
3041 RCAR_GP_PIN(0, 6),
3042};
3043static const unsigned int msiof2_rxd_b_mux[] = {
3044 MSIOF2_RXD_B_MARK,
3045};
3046static const unsigned int msiof2_clk_c_pins[] = {
3047 /* SCK */
3048 RCAR_GP_PIN(2, 12),
3049};
3050static const unsigned int msiof2_clk_c_mux[] = {
3051 MSIOF2_SCK_C_MARK,
3052};
3053static const unsigned int msiof2_sync_c_pins[] = {
3054 /* SYNC */
3055 RCAR_GP_PIN(2, 11),
3056};
3057static const unsigned int msiof2_sync_c_mux[] = {
3058 MSIOF2_SYNC_C_MARK,
3059};
3060static const unsigned int msiof2_ss1_c_pins[] = {
3061 /* SS1 */
3062 RCAR_GP_PIN(2, 10),
3063};
3064static const unsigned int msiof2_ss1_c_mux[] = {
3065 MSIOF2_SS1_C_MARK,
3066};
3067static const unsigned int msiof2_ss2_c_pins[] = {
3068 /* SS2 */
3069 RCAR_GP_PIN(2, 9),
3070};
3071static const unsigned int msiof2_ss2_c_mux[] = {
3072 MSIOF2_SS2_C_MARK,
3073};
3074static const unsigned int msiof2_txd_c_pins[] = {
3075 /* TXD */
3076 RCAR_GP_PIN(2, 14),
3077};
3078static const unsigned int msiof2_txd_c_mux[] = {
3079 MSIOF2_TXD_C_MARK,
3080};
3081static const unsigned int msiof2_rxd_c_pins[] = {
3082 /* RXD */
3083 RCAR_GP_PIN(2, 13),
3084};
3085static const unsigned int msiof2_rxd_c_mux[] = {
3086 MSIOF2_RXD_C_MARK,
3087};
3088static const unsigned int msiof2_clk_d_pins[] = {
3089 /* SCK */
3090 RCAR_GP_PIN(0, 8),
3091};
3092static const unsigned int msiof2_clk_d_mux[] = {
3093 MSIOF2_SCK_D_MARK,
3094};
3095static const unsigned int msiof2_sync_d_pins[] = {
3096 /* SYNC */
3097 RCAR_GP_PIN(0, 9),
3098};
3099static const unsigned int msiof2_sync_d_mux[] = {
3100 MSIOF2_SYNC_D_MARK,
3101};
3102static const unsigned int msiof2_ss1_d_pins[] = {
3103 /* SS1 */
3104 RCAR_GP_PIN(0, 12),
3105};
3106static const unsigned int msiof2_ss1_d_mux[] = {
3107 MSIOF2_SS1_D_MARK,
3108};
3109static const unsigned int msiof2_ss2_d_pins[] = {
3110 /* SS2 */
3111 RCAR_GP_PIN(0, 13),
3112};
3113static const unsigned int msiof2_ss2_d_mux[] = {
3114 MSIOF2_SS2_D_MARK,
3115};
3116static const unsigned int msiof2_txd_d_pins[] = {
3117 /* TXD */
3118 RCAR_GP_PIN(0, 11),
3119};
3120static const unsigned int msiof2_txd_d_mux[] = {
3121 MSIOF2_TXD_D_MARK,
3122};
3123static const unsigned int msiof2_rxd_d_pins[] = {
3124 /* RXD */
3125 RCAR_GP_PIN(0, 10),
3126};
3127static const unsigned int msiof2_rxd_d_mux[] = {
3128 MSIOF2_RXD_D_MARK,
3129};
3130/* - MSIOF3 ----------------------------------------------------------------- */
3131static const unsigned int msiof3_clk_a_pins[] = {
3132 /* SCK */
3133 RCAR_GP_PIN(0, 0),
3134};
3135static const unsigned int msiof3_clk_a_mux[] = {
3136 MSIOF3_SCK_A_MARK,
3137};
3138static const unsigned int msiof3_sync_a_pins[] = {
3139 /* SYNC */
3140 RCAR_GP_PIN(0, 1),
3141};
3142static const unsigned int msiof3_sync_a_mux[] = {
3143 MSIOF3_SYNC_A_MARK,
3144};
3145static const unsigned int msiof3_ss1_a_pins[] = {
3146 /* SS1 */
3147 RCAR_GP_PIN(0, 14),
3148};
3149static const unsigned int msiof3_ss1_a_mux[] = {
3150 MSIOF3_SS1_A_MARK,
3151};
3152static const unsigned int msiof3_ss2_a_pins[] = {
3153 /* SS2 */
3154 RCAR_GP_PIN(0, 15),
3155};
3156static const unsigned int msiof3_ss2_a_mux[] = {
3157 MSIOF3_SS2_A_MARK,
3158};
3159static const unsigned int msiof3_txd_a_pins[] = {
3160 /* TXD */
3161 RCAR_GP_PIN(0, 3),
3162};
3163static const unsigned int msiof3_txd_a_mux[] = {
3164 MSIOF3_TXD_A_MARK,
3165};
3166static const unsigned int msiof3_rxd_a_pins[] = {
3167 /* RXD */
3168 RCAR_GP_PIN(0, 2),
3169};
3170static const unsigned int msiof3_rxd_a_mux[] = {
3171 MSIOF3_RXD_A_MARK,
3172};
3173static const unsigned int msiof3_clk_b_pins[] = {
3174 /* SCK */
3175 RCAR_GP_PIN(1, 2),
3176};
3177static const unsigned int msiof3_clk_b_mux[] = {
3178 MSIOF3_SCK_B_MARK,
3179};
3180static const unsigned int msiof3_sync_b_pins[] = {
3181 /* SYNC */
3182 RCAR_GP_PIN(1, 0),
3183};
3184static const unsigned int msiof3_sync_b_mux[] = {
3185 MSIOF3_SYNC_B_MARK,
3186};
3187static const unsigned int msiof3_ss1_b_pins[] = {
3188 /* SS1 */
3189 RCAR_GP_PIN(1, 4),
3190};
3191static const unsigned int msiof3_ss1_b_mux[] = {
3192 MSIOF3_SS1_B_MARK,
3193};
3194static const unsigned int msiof3_ss2_b_pins[] = {
3195 /* SS2 */
3196 RCAR_GP_PIN(1, 5),
3197};
3198static const unsigned int msiof3_ss2_b_mux[] = {
3199 MSIOF3_SS2_B_MARK,
3200};
3201static const unsigned int msiof3_txd_b_pins[] = {
3202 /* TXD */
3203 RCAR_GP_PIN(1, 1),
3204};
3205static const unsigned int msiof3_txd_b_mux[] = {
3206 MSIOF3_TXD_B_MARK,
3207};
3208static const unsigned int msiof3_rxd_b_pins[] = {
3209 /* RXD */
3210 RCAR_GP_PIN(1, 3),
3211};
3212static const unsigned int msiof3_rxd_b_mux[] = {
3213 MSIOF3_RXD_B_MARK,
3214};
3215static const unsigned int msiof3_clk_c_pins[] = {
3216 /* SCK */
3217 RCAR_GP_PIN(1, 12),
3218};
3219static const unsigned int msiof3_clk_c_mux[] = {
3220 MSIOF3_SCK_C_MARK,
3221};
3222static const unsigned int msiof3_sync_c_pins[] = {
3223 /* SYNC */
3224 RCAR_GP_PIN(1, 13),
3225};
3226static const unsigned int msiof3_sync_c_mux[] = {
3227 MSIOF3_SYNC_C_MARK,
3228};
3229static const unsigned int msiof3_txd_c_pins[] = {
3230 /* TXD */
3231 RCAR_GP_PIN(1, 15),
3232};
3233static const unsigned int msiof3_txd_c_mux[] = {
3234 MSIOF3_TXD_C_MARK,
3235};
3236static const unsigned int msiof3_rxd_c_pins[] = {
3237 /* RXD */
3238 RCAR_GP_PIN(1, 14),
3239};
3240static const unsigned int msiof3_rxd_c_mux[] = {
3241 MSIOF3_RXD_C_MARK,
3242};
3243static const unsigned int msiof3_clk_d_pins[] = {
3244 /* SCK */
3245 RCAR_GP_PIN(1, 22),
3246};
3247static const unsigned int msiof3_clk_d_mux[] = {
3248 MSIOF3_SCK_D_MARK,
3249};
3250static const unsigned int msiof3_sync_d_pins[] = {
3251 /* SYNC */
3252 RCAR_GP_PIN(1, 23),
3253};
3254static const unsigned int msiof3_sync_d_mux[] = {
3255 MSIOF3_SYNC_D_MARK,
3256};
3257static const unsigned int msiof3_ss1_d_pins[] = {
3258 /* SS1 */
3259 RCAR_GP_PIN(1, 26),
3260};
3261static const unsigned int msiof3_ss1_d_mux[] = {
3262 MSIOF3_SS1_D_MARK,
3263};
3264static const unsigned int msiof3_txd_d_pins[] = {
3265 /* TXD */
3266 RCAR_GP_PIN(1, 25),
3267};
3268static const unsigned int msiof3_txd_d_mux[] = {
3269 MSIOF3_TXD_D_MARK,
3270};
3271static const unsigned int msiof3_rxd_d_pins[] = {
3272 /* RXD */
3273 RCAR_GP_PIN(1, 24),
3274};
3275static const unsigned int msiof3_rxd_d_mux[] = {
3276 MSIOF3_RXD_D_MARK,
3277};
3278static const unsigned int msiof3_clk_e_pins[] = {
3279 /* SCK */
3280 RCAR_GP_PIN(2, 3),
3281};
3282static const unsigned int msiof3_clk_e_mux[] = {
3283 MSIOF3_SCK_E_MARK,
3284};
3285static const unsigned int msiof3_sync_e_pins[] = {
3286 /* SYNC */
3287 RCAR_GP_PIN(2, 2),
3288};
3289static const unsigned int msiof3_sync_e_mux[] = {
3290 MSIOF3_SYNC_E_MARK,
3291};
3292static const unsigned int msiof3_ss1_e_pins[] = {
3293 /* SS1 */
3294 RCAR_GP_PIN(2, 1),
3295};
3296static const unsigned int msiof3_ss1_e_mux[] = {
3297 MSIOF3_SS1_E_MARK,
3298};
3299static const unsigned int msiof3_ss2_e_pins[] = {
3300 /* SS2 */
3301 RCAR_GP_PIN(2, 0),
3302};
3303static const unsigned int msiof3_ss2_e_mux[] = {
3304 MSIOF3_SS2_E_MARK,
3305};
3306static const unsigned int msiof3_txd_e_pins[] = {
3307 /* TXD */
3308 RCAR_GP_PIN(2, 5),
3309};
3310static const unsigned int msiof3_txd_e_mux[] = {
3311 MSIOF3_TXD_E_MARK,
3312};
3313static const unsigned int msiof3_rxd_e_pins[] = {
3314 /* RXD */
3315 RCAR_GP_PIN(2, 4),
3316};
3317static const unsigned int msiof3_rxd_e_mux[] = {
3318 MSIOF3_RXD_E_MARK,
3319};
3320
3321/* - PWM0 --------------------------------------------------------------------*/
3322static const unsigned int pwm0_pins[] = {
3323 /* PWM */
3324 RCAR_GP_PIN(2, 6),
3325};
3326static const unsigned int pwm0_mux[] = {
3327 PWM0_MARK,
3328};
3329/* - PWM1 --------------------------------------------------------------------*/
3330static const unsigned int pwm1_a_pins[] = {
3331 /* PWM */
3332 RCAR_GP_PIN(2, 7),
3333};
3334static const unsigned int pwm1_a_mux[] = {
3335 PWM1_A_MARK,
3336};
3337static const unsigned int pwm1_b_pins[] = {
3338 /* PWM */
3339 RCAR_GP_PIN(1, 8),
3340};
3341static const unsigned int pwm1_b_mux[] = {
3342 PWM1_B_MARK,
3343};
3344/* - PWM2 --------------------------------------------------------------------*/
3345static const unsigned int pwm2_a_pins[] = {
3346 /* PWM */
3347 RCAR_GP_PIN(2, 8),
3348};
3349static const unsigned int pwm2_a_mux[] = {
3350 PWM2_A_MARK,
3351};
3352static const unsigned int pwm2_b_pins[] = {
3353 /* PWM */
3354 RCAR_GP_PIN(1, 11),
3355};
3356static const unsigned int pwm2_b_mux[] = {
3357 PWM2_B_MARK,
3358};
3359/* - PWM3 --------------------------------------------------------------------*/
3360static const unsigned int pwm3_a_pins[] = {
3361 /* PWM */
3362 RCAR_GP_PIN(1, 0),
3363};
3364static const unsigned int pwm3_a_mux[] = {
3365 PWM3_A_MARK,
3366};
3367static const unsigned int pwm3_b_pins[] = {
3368 /* PWM */
3369 RCAR_GP_PIN(2, 2),
3370};
3371static const unsigned int pwm3_b_mux[] = {
3372 PWM3_B_MARK,
3373};
3374/* - PWM4 --------------------------------------------------------------------*/
3375static const unsigned int pwm4_a_pins[] = {
3376 /* PWM */
3377 RCAR_GP_PIN(1, 1),
3378};
3379static const unsigned int pwm4_a_mux[] = {
3380 PWM4_A_MARK,
3381};
3382static const unsigned int pwm4_b_pins[] = {
3383 /* PWM */
3384 RCAR_GP_PIN(2, 3),
3385};
3386static const unsigned int pwm4_b_mux[] = {
3387 PWM4_B_MARK,
3388};
3389/* - PWM5 --------------------------------------------------------------------*/
3390static const unsigned int pwm5_a_pins[] = {
3391 /* PWM */
3392 RCAR_GP_PIN(1, 2),
3393};
3394static const unsigned int pwm5_a_mux[] = {
3395 PWM5_A_MARK,
3396};
3397static const unsigned int pwm5_b_pins[] = {
3398 /* PWM */
3399 RCAR_GP_PIN(2, 4),
3400};
3401static const unsigned int pwm5_b_mux[] = {
3402 PWM5_B_MARK,
3403};
3404/* - PWM6 --------------------------------------------------------------------*/
3405static const unsigned int pwm6_a_pins[] = {
3406 /* PWM */
3407 RCAR_GP_PIN(1, 3),
3408};
3409static const unsigned int pwm6_a_mux[] = {
3410 PWM6_A_MARK,
3411};
3412static const unsigned int pwm6_b_pins[] = {
3413 /* PWM */
3414 RCAR_GP_PIN(2, 5),
3415};
3416static const unsigned int pwm6_b_mux[] = {
3417 PWM6_B_MARK,
3418};
3419
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]3420/* - QSPI0 ------------------------------------------------------------------ */
3421static const unsigned int qspi0_ctrl_pins[] = {
3422 /* QSPI0_SPCLK, QSPI0_SSL */
3423 PIN_QSPI0_SPCLK, PIN_QSPI0_SSL,
3424};
3425static const unsigned int qspi0_ctrl_mux[] = {
3426 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
3427};
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]3428static const unsigned int qspi0_data_pins[] = {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]3429 /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
3430 PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
3431 /* QSPI0_IO2, QSPI0_IO3 */
3432 PIN_QSPI0_IO2, PIN_QSPI0_IO3,
3433};
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]3434static const unsigned int qspi0_data_mux[] = {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]3435 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
3436 QSPI0_IO2_MARK, QSPI0_IO3_MARK,
3437};
3438/* - QSPI1 ------------------------------------------------------------------ */
3439static const unsigned int qspi1_ctrl_pins[] = {
3440 /* QSPI1_SPCLK, QSPI1_SSL */
3441 PIN_QSPI1_SPCLK, PIN_QSPI1_SSL,
3442};
3443static const unsigned int qspi1_ctrl_mux[] = {
3444 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
3445};
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]3446static const unsigned int qspi1_data_pins[] = {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]3447 /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
3448 PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
3449 /* QSPI1_IO2, QSPI1_IO3 */
3450 PIN_QSPI1_IO2, PIN_QSPI1_IO3,
3451};
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]3452static const unsigned int qspi1_data_mux[] = {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]3453 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
3454 QSPI1_IO2_MARK, QSPI1_IO3_MARK,
3455};
3456
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]3457/* - SATA --------------------------------------------------------------------*/
3458static const unsigned int sata0_devslp_a_pins[] = {
3459 /* DEVSLP */
3460 RCAR_GP_PIN(6, 16),
3461};
3462
3463static const unsigned int sata0_devslp_a_mux[] = {
3464 SATA_DEVSLP_A_MARK,
3465};
3466
3467static const unsigned int sata0_devslp_b_pins[] = {
3468 /* DEVSLP */
3469 RCAR_GP_PIN(4, 6),
3470};
3471
3472static const unsigned int sata0_devslp_b_mux[] = {
3473 SATA_DEVSLP_B_MARK,
3474};
3475
3476/* - SCIF0 ------------------------------------------------------------------ */
3477static const unsigned int scif0_data_pins[] = {
3478 /* RX, TX */
3479 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3480};
3481static const unsigned int scif0_data_mux[] = {
3482 RX0_MARK, TX0_MARK,
3483};
3484static const unsigned int scif0_clk_pins[] = {
3485 /* SCK */
3486 RCAR_GP_PIN(5, 0),
3487};
3488static const unsigned int scif0_clk_mux[] = {
3489 SCK0_MARK,
3490};
3491static const unsigned int scif0_ctrl_pins[] = {
3492 /* RTS, CTS */
3493 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3494};
3495static const unsigned int scif0_ctrl_mux[] = {
3496 RTS0_N_MARK, CTS0_N_MARK,
3497};
3498/* - SCIF1 ------------------------------------------------------------------ */
3499static const unsigned int scif1_data_a_pins[] = {
3500 /* RX, TX */
3501 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3502};
3503static const unsigned int scif1_data_a_mux[] = {
3504 RX1_A_MARK, TX1_A_MARK,
3505};
3506static const unsigned int scif1_clk_pins[] = {
3507 /* SCK */
3508 RCAR_GP_PIN(6, 21),
3509};
3510static const unsigned int scif1_clk_mux[] = {
3511 SCK1_MARK,
3512};
3513static const unsigned int scif1_ctrl_pins[] = {
3514 /* RTS, CTS */
3515 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3516};
3517static const unsigned int scif1_ctrl_mux[] = {
3518 RTS1_N_MARK, CTS1_N_MARK,
3519};
3520static const unsigned int scif1_data_b_pins[] = {
3521 /* RX, TX */
3522 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3523};
3524static const unsigned int scif1_data_b_mux[] = {
3525 RX1_B_MARK, TX1_B_MARK,
3526};
3527/* - SCIF2 ------------------------------------------------------------------ */
3528static const unsigned int scif2_data_a_pins[] = {
3529 /* RX, TX */
3530 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3531};
3532static const unsigned int scif2_data_a_mux[] = {
3533 RX2_A_MARK, TX2_A_MARK,
3534};
3535static const unsigned int scif2_clk_pins[] = {
3536 /* SCK */
3537 RCAR_GP_PIN(5, 9),
3538};
3539static const unsigned int scif2_clk_mux[] = {
3540 SCK2_MARK,
3541};
3542static const unsigned int scif2_data_b_pins[] = {
3543 /* RX, TX */
3544 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3545};
3546static const unsigned int scif2_data_b_mux[] = {
3547 RX2_B_MARK, TX2_B_MARK,
3548};
3549/* - SCIF3 ------------------------------------------------------------------ */
3550static const unsigned int scif3_data_a_pins[] = {
3551 /* RX, TX */
3552 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3553};
3554static const unsigned int scif3_data_a_mux[] = {
3555 RX3_A_MARK, TX3_A_MARK,
3556};
3557static const unsigned int scif3_clk_pins[] = {
3558 /* SCK */
3559 RCAR_GP_PIN(1, 22),
3560};
3561static const unsigned int scif3_clk_mux[] = {
3562 SCK3_MARK,
3563};
3564static const unsigned int scif3_ctrl_pins[] = {
3565 /* RTS, CTS */
3566 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3567};
3568static const unsigned int scif3_ctrl_mux[] = {
3569 RTS3_N_MARK, CTS3_N_MARK,
3570};
3571static const unsigned int scif3_data_b_pins[] = {
3572 /* RX, TX */
3573 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3574};
3575static const unsigned int scif3_data_b_mux[] = {
3576 RX3_B_MARK, TX3_B_MARK,
3577};
3578/* - SCIF4 ------------------------------------------------------------------ */
3579static const unsigned int scif4_data_a_pins[] = {
3580 /* RX, TX */
3581 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3582};
3583static const unsigned int scif4_data_a_mux[] = {
3584 RX4_A_MARK, TX4_A_MARK,
3585};
3586static const unsigned int scif4_clk_a_pins[] = {
3587 /* SCK */
3588 RCAR_GP_PIN(2, 10),
3589};
3590static const unsigned int scif4_clk_a_mux[] = {
3591 SCK4_A_MARK,
3592};
3593static const unsigned int scif4_ctrl_a_pins[] = {
3594 /* RTS, CTS */
3595 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3596};
3597static const unsigned int scif4_ctrl_a_mux[] = {
3598 RTS4_N_A_MARK, CTS4_N_A_MARK,
3599};
3600static const unsigned int scif4_data_b_pins[] = {
3601 /* RX, TX */
3602 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3603};
3604static const unsigned int scif4_data_b_mux[] = {
3605 RX4_B_MARK, TX4_B_MARK,
3606};
3607static const unsigned int scif4_clk_b_pins[] = {
3608 /* SCK */
3609 RCAR_GP_PIN(1, 5),
3610};
3611static const unsigned int scif4_clk_b_mux[] = {
3612 SCK4_B_MARK,
3613};
3614static const unsigned int scif4_ctrl_b_pins[] = {
3615 /* RTS, CTS */
3616 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3617};
3618static const unsigned int scif4_ctrl_b_mux[] = {
3619 RTS4_N_B_MARK, CTS4_N_B_MARK,
3620};
3621static const unsigned int scif4_data_c_pins[] = {
3622 /* RX, TX */
3623 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3624};
3625static const unsigned int scif4_data_c_mux[] = {
3626 RX4_C_MARK, TX4_C_MARK,
3627};
3628static const unsigned int scif4_clk_c_pins[] = {
3629 /* SCK */
3630 RCAR_GP_PIN(0, 8),
3631};
3632static const unsigned int scif4_clk_c_mux[] = {
3633 SCK4_C_MARK,
3634};
3635static const unsigned int scif4_ctrl_c_pins[] = {
3636 /* RTS, CTS */
3637 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3638};
3639static const unsigned int scif4_ctrl_c_mux[] = {
3640 RTS4_N_C_MARK, CTS4_N_C_MARK,
3641};
3642/* - SCIF5 ------------------------------------------------------------------ */
3643static const unsigned int scif5_data_a_pins[] = {
3644 /* RX, TX */
3645 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3646};
3647static const unsigned int scif5_data_a_mux[] = {
3648 RX5_A_MARK, TX5_A_MARK,
3649};
3650static const unsigned int scif5_clk_a_pins[] = {
3651 /* SCK */
3652 RCAR_GP_PIN(6, 21),
3653};
3654static const unsigned int scif5_clk_a_mux[] = {
3655 SCK5_A_MARK,
3656};
3657static const unsigned int scif5_data_b_pins[] = {
3658 /* RX, TX */
3659 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3660};
3661static const unsigned int scif5_data_b_mux[] = {
3662 RX5_B_MARK, TX5_B_MARK,
3663};
3664static const unsigned int scif5_clk_b_pins[] = {
3665 /* SCK */
3666 RCAR_GP_PIN(5, 0),
3667};
3668static const unsigned int scif5_clk_b_mux[] = {
3669 SCK5_B_MARK,
3670};
3671/* - SCIF Clock ------------------------------------------------------------- */
3672static const unsigned int scif_clk_a_pins[] = {
3673 /* SCIF_CLK */
3674 RCAR_GP_PIN(6, 23),
3675};
3676static const unsigned int scif_clk_a_mux[] = {
3677 SCIF_CLK_A_MARK,
3678};
3679static const unsigned int scif_clk_b_pins[] = {
3680 /* SCIF_CLK */
3681 RCAR_GP_PIN(5, 9),
3682};
3683static const unsigned int scif_clk_b_mux[] = {
3684 SCIF_CLK_B_MARK,
3685};
3686
3687/* - SDHI0 ------------------------------------------------------------------ */
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]3688static const unsigned int sdhi0_data_pins[] = {
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]3689 /* D[0:3] */
3690 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3691 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3692};
3693
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]3694static const unsigned int sdhi0_data_mux[] = {
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]3695 SD0_DAT0_MARK, SD0_DAT1_MARK,
3696 SD0_DAT2_MARK, SD0_DAT3_MARK,
3697};
3698
3699static const unsigned int sdhi0_ctrl_pins[] = {
3700 /* CLK, CMD */
3701 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3702};
3703
3704static const unsigned int sdhi0_ctrl_mux[] = {
3705 SD0_CLK_MARK, SD0_CMD_MARK,
3706};
3707
3708static const unsigned int sdhi0_cd_pins[] = {
3709 /* CD */
3710 RCAR_GP_PIN(3, 12),
3711};
3712
3713static const unsigned int sdhi0_cd_mux[] = {
3714 SD0_CD_MARK,
3715};
3716
3717static const unsigned int sdhi0_wp_pins[] = {
3718 /* WP */
3719 RCAR_GP_PIN(3, 13),
3720};
3721
3722static const unsigned int sdhi0_wp_mux[] = {
3723 SD0_WP_MARK,
3724};
3725
3726/* - SDHI1 ------------------------------------------------------------------ */
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]3727static const unsigned int sdhi1_data_pins[] = {
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]3728 /* D[0:3] */
3729 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3730 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3731};
3732
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]3733static const unsigned int sdhi1_data_mux[] = {
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]3734 SD1_DAT0_MARK, SD1_DAT1_MARK,
3735 SD1_DAT2_MARK, SD1_DAT3_MARK,
3736};
3737
3738static const unsigned int sdhi1_ctrl_pins[] = {
3739 /* CLK, CMD */
3740 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3741};
3742
3743static const unsigned int sdhi1_ctrl_mux[] = {
3744 SD1_CLK_MARK, SD1_CMD_MARK,
3745};
3746
3747static const unsigned int sdhi1_cd_pins[] = {
3748 /* CD */
3749 RCAR_GP_PIN(3, 14),
3750};
3751
3752static const unsigned int sdhi1_cd_mux[] = {
3753 SD1_CD_MARK,
3754};
3755
3756static const unsigned int sdhi1_wp_pins[] = {
3757 /* WP */
3758 RCAR_GP_PIN(3, 15),
3759};
3760
3761static const unsigned int sdhi1_wp_mux[] = {
3762 SD1_WP_MARK,
3763};
3764
3765/* - SDHI2 ------------------------------------------------------------------ */
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]3766static const unsigned int sdhi2_data_pins[] = {
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]3767 /* D[0:7] */
3768 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3769 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3770 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3771 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3772};
3773
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]3774static const unsigned int sdhi2_data_mux[] = {
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]3775 SD2_DAT0_MARK, SD2_DAT1_MARK,
3776 SD2_DAT2_MARK, SD2_DAT3_MARK,
3777 SD2_DAT4_MARK, SD2_DAT5_MARK,
3778 SD2_DAT6_MARK, SD2_DAT7_MARK,
3779};
3780
3781static const unsigned int sdhi2_ctrl_pins[] = {
3782 /* CLK, CMD */
3783 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3784};
3785
3786static const unsigned int sdhi2_ctrl_mux[] = {
3787 SD2_CLK_MARK, SD2_CMD_MARK,
3788};
3789
3790static const unsigned int sdhi2_cd_a_pins[] = {
3791 /* CD */
3792 RCAR_GP_PIN(4, 13),
3793};
3794
3795static const unsigned int sdhi2_cd_a_mux[] = {
3796 SD2_CD_A_MARK,
3797};
3798
3799static const unsigned int sdhi2_cd_b_pins[] = {
3800 /* CD */
3801 RCAR_GP_PIN(5, 10),
3802};
3803
3804static const unsigned int sdhi2_cd_b_mux[] = {
3805 SD2_CD_B_MARK,
3806};
3807
3808static const unsigned int sdhi2_wp_a_pins[] = {
3809 /* WP */
3810 RCAR_GP_PIN(4, 14),
3811};
3812
3813static const unsigned int sdhi2_wp_a_mux[] = {
3814 SD2_WP_A_MARK,
3815};
3816
3817static const unsigned int sdhi2_wp_b_pins[] = {
3818 /* WP */
3819 RCAR_GP_PIN(5, 11),
3820};
3821
3822static const unsigned int sdhi2_wp_b_mux[] = {
3823 SD2_WP_B_MARK,
3824};
3825
3826static const unsigned int sdhi2_ds_pins[] = {
3827 /* DS */
3828 RCAR_GP_PIN(4, 6),
3829};
3830
3831static const unsigned int sdhi2_ds_mux[] = {
3832 SD2_DS_MARK,
3833};
3834
3835/* - SDHI3 ------------------------------------------------------------------ */
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]3836static const unsigned int sdhi3_data_pins[] = {
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]3837 /* D[0:7] */
3838 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3839 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3840 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3841 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3842};
3843
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]3844static const unsigned int sdhi3_data_mux[] = {
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]3845 SD3_DAT0_MARK, SD3_DAT1_MARK,
3846 SD3_DAT2_MARK, SD3_DAT3_MARK,
3847 SD3_DAT4_MARK, SD3_DAT5_MARK,
3848 SD3_DAT6_MARK, SD3_DAT7_MARK,
3849};
3850
3851static const unsigned int sdhi3_ctrl_pins[] = {
3852 /* CLK, CMD */
3853 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3854};
3855
3856static const unsigned int sdhi3_ctrl_mux[] = {
3857 SD3_CLK_MARK, SD3_CMD_MARK,
3858};
3859
3860static const unsigned int sdhi3_cd_pins[] = {
3861 /* CD */
3862 RCAR_GP_PIN(4, 15),
3863};
3864
3865static const unsigned int sdhi3_cd_mux[] = {
3866 SD3_CD_MARK,
3867};
3868
3869static const unsigned int sdhi3_wp_pins[] = {
3870 /* WP */
3871 RCAR_GP_PIN(4, 16),
3872};
3873
3874static const unsigned int sdhi3_wp_mux[] = {
3875 SD3_WP_MARK,
3876};
3877
3878static const unsigned int sdhi3_ds_pins[] = {
3879 /* DS */
3880 RCAR_GP_PIN(4, 17),
3881};
3882
3883static const unsigned int sdhi3_ds_mux[] = {
3884 SD3_DS_MARK,
3885};
3886
3887/* - SSI -------------------------------------------------------------------- */
3888static const unsigned int ssi0_data_pins[] = {
3889 /* SDATA */
3890 RCAR_GP_PIN(6, 2),
3891};
3892static const unsigned int ssi0_data_mux[] = {
3893 SSI_SDATA0_MARK,
3894};
3895static const unsigned int ssi01239_ctrl_pins[] = {
3896 /* SCK, WS */
3897 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3898};
3899static const unsigned int ssi01239_ctrl_mux[] = {
3900 SSI_SCK01239_MARK, SSI_WS01239_MARK,
3901};
3902static const unsigned int ssi1_data_a_pins[] = {
3903 /* SDATA */
3904 RCAR_GP_PIN(6, 3),
3905};
3906static const unsigned int ssi1_data_a_mux[] = {
3907 SSI_SDATA1_A_MARK,
3908};
3909static const unsigned int ssi1_data_b_pins[] = {
3910 /* SDATA */
3911 RCAR_GP_PIN(5, 12),
3912};
3913static const unsigned int ssi1_data_b_mux[] = {
3914 SSI_SDATA1_B_MARK,
3915};
3916static const unsigned int ssi1_ctrl_a_pins[] = {
3917 /* SCK, WS */
3918 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3919};
3920static const unsigned int ssi1_ctrl_a_mux[] = {
3921 SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3922};
3923static const unsigned int ssi1_ctrl_b_pins[] = {
3924 /* SCK, WS */
3925 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3926};
3927static const unsigned int ssi1_ctrl_b_mux[] = {
3928 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3929};
3930static const unsigned int ssi2_data_a_pins[] = {
3931 /* SDATA */
3932 RCAR_GP_PIN(6, 4),
3933};
3934static const unsigned int ssi2_data_a_mux[] = {
3935 SSI_SDATA2_A_MARK,
3936};
3937static const unsigned int ssi2_data_b_pins[] = {
3938 /* SDATA */
3939 RCAR_GP_PIN(5, 13),
3940};
3941static const unsigned int ssi2_data_b_mux[] = {
3942 SSI_SDATA2_B_MARK,
3943};
3944static const unsigned int ssi2_ctrl_a_pins[] = {
3945 /* SCK, WS */
3946 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3947};
3948static const unsigned int ssi2_ctrl_a_mux[] = {
3949 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3950};
3951static const unsigned int ssi2_ctrl_b_pins[] = {
3952 /* SCK, WS */
3953 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3954};
3955static const unsigned int ssi2_ctrl_b_mux[] = {
3956 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3957};
3958static const unsigned int ssi3_data_pins[] = {
3959 /* SDATA */
3960 RCAR_GP_PIN(6, 7),
3961};
3962static const unsigned int ssi3_data_mux[] = {
3963 SSI_SDATA3_MARK,
3964};
3965static const unsigned int ssi349_ctrl_pins[] = {
3966 /* SCK, WS */
3967 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3968};
3969static const unsigned int ssi349_ctrl_mux[] = {
3970 SSI_SCK349_MARK, SSI_WS349_MARK,
3971};
3972static const unsigned int ssi4_data_pins[] = {
3973 /* SDATA */
3974 RCAR_GP_PIN(6, 10),
3975};
3976static const unsigned int ssi4_data_mux[] = {
3977 SSI_SDATA4_MARK,
3978};
3979static const unsigned int ssi4_ctrl_pins[] = {
3980 /* SCK, WS */
3981 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3982};
3983static const unsigned int ssi4_ctrl_mux[] = {
3984 SSI_SCK4_MARK, SSI_WS4_MARK,
3985};
3986static const unsigned int ssi5_data_pins[] = {
3987 /* SDATA */
3988 RCAR_GP_PIN(6, 13),
3989};
3990static const unsigned int ssi5_data_mux[] = {
3991 SSI_SDATA5_MARK,
3992};
3993static const unsigned int ssi5_ctrl_pins[] = {
3994 /* SCK, WS */
3995 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3996};
3997static const unsigned int ssi5_ctrl_mux[] = {
3998 SSI_SCK5_MARK, SSI_WS5_MARK,
3999};
4000static const unsigned int ssi6_data_pins[] = {
4001 /* SDATA */
4002 RCAR_GP_PIN(6, 16),
4003};
4004static const unsigned int ssi6_data_mux[] = {
4005 SSI_SDATA6_MARK,
4006};
4007static const unsigned int ssi6_ctrl_pins[] = {
4008 /* SCK, WS */
4009 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
4010};
4011static const unsigned int ssi6_ctrl_mux[] = {
4012 SSI_SCK6_MARK, SSI_WS6_MARK,
4013};
4014static const unsigned int ssi7_data_pins[] = {
4015 /* SDATA */
4016 RCAR_GP_PIN(6, 19),
4017};
4018static const unsigned int ssi7_data_mux[] = {
4019 SSI_SDATA7_MARK,
4020};
4021static const unsigned int ssi78_ctrl_pins[] = {
4022 /* SCK, WS */
4023 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
4024};
4025static const unsigned int ssi78_ctrl_mux[] = {
4026 SSI_SCK78_MARK, SSI_WS78_MARK,
4027};
4028static const unsigned int ssi8_data_pins[] = {
4029 /* SDATA */
4030 RCAR_GP_PIN(6, 20),
4031};
4032static const unsigned int ssi8_data_mux[] = {
4033 SSI_SDATA8_MARK,
4034};
4035static const unsigned int ssi9_data_a_pins[] = {
4036 /* SDATA */
4037 RCAR_GP_PIN(6, 21),
4038};
4039static const unsigned int ssi9_data_a_mux[] = {
4040 SSI_SDATA9_A_MARK,
4041};
4042static const unsigned int ssi9_data_b_pins[] = {
4043 /* SDATA */
4044 RCAR_GP_PIN(5, 14),
4045};
4046static const unsigned int ssi9_data_b_mux[] = {
4047 SSI_SDATA9_B_MARK,
4048};
4049static const unsigned int ssi9_ctrl_a_pins[] = {
4050 /* SCK, WS */
4051 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
4052};
4053static const unsigned int ssi9_ctrl_a_mux[] = {
4054 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
4055};
4056static const unsigned int ssi9_ctrl_b_pins[] = {
4057 /* SCK, WS */
4058 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
4059};
4060static const unsigned int ssi9_ctrl_b_mux[] = {
4061 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
4062};
4063
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4064/* - TMU -------------------------------------------------------------------- */
4065static const unsigned int tmu_tclk1_a_pins[] = {
4066 /* TCLK */
4067 RCAR_GP_PIN(6, 23),
4068};
4069
4070static const unsigned int tmu_tclk1_a_mux[] = {
4071 TCLK1_A_MARK,
4072};
4073
4074static const unsigned int tmu_tclk1_b_pins[] = {
4075 /* TCLK */
4076 RCAR_GP_PIN(5, 19),
4077};
4078
4079static const unsigned int tmu_tclk1_b_mux[] = {
4080 TCLK1_B_MARK,
4081};
4082
4083static const unsigned int tmu_tclk2_a_pins[] = {
4084 /* TCLK */
4085 RCAR_GP_PIN(6, 19),
4086};
4087
4088static const unsigned int tmu_tclk2_a_mux[] = {
4089 TCLK2_A_MARK,
4090};
4091
4092static const unsigned int tmu_tclk2_b_pins[] = {
4093 /* TCLK */
4094 RCAR_GP_PIN(6, 28),
4095};
4096
4097static const unsigned int tmu_tclk2_b_mux[] = {
4098 TCLK2_B_MARK,
4099};
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4100
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]4101/* - TPU ------------------------------------------------------------------- */
4102static const unsigned int tpu_to0_pins[] = {
4103 /* TPU0TO0 */
4104 RCAR_GP_PIN(6, 28),
4105};
4106static const unsigned int tpu_to0_mux[] = {
4107 TPU0TO0_MARK,
4108};
4109static const unsigned int tpu_to1_pins[] = {
4110 /* TPU0TO1 */
4111 RCAR_GP_PIN(6, 29),
4112};
4113static const unsigned int tpu_to1_mux[] = {
4114 TPU0TO1_MARK,
4115};
4116static const unsigned int tpu_to2_pins[] = {
4117 /* TPU0TO2 */
4118 RCAR_GP_PIN(6, 30),
4119};
4120static const unsigned int tpu_to2_mux[] = {
4121 TPU0TO2_MARK,
4122};
4123static const unsigned int tpu_to3_pins[] = {
4124 /* TPU0TO3 */
4125 RCAR_GP_PIN(6, 31),
4126};
4127static const unsigned int tpu_to3_mux[] = {
4128 TPU0TO3_MARK,
4129};
4130
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4131/* - USB0 ------------------------------------------------------------------- */
4132static const unsigned int usb0_pins[] = {
4133 /* PWEN, OVC */
4134 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
4135};
4136
4137static const unsigned int usb0_mux[] = {
4138 USB0_PWEN_MARK, USB0_OVC_MARK,
4139};
4140
4141/* - USB1 ------------------------------------------------------------------- */
4142static const unsigned int usb1_pins[] = {
4143 /* PWEN, OVC */
4144 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
4145};
4146
4147static const unsigned int usb1_mux[] = {
4148 USB1_PWEN_MARK, USB1_OVC_MARK,
4149};
4150
4151/* - USB30 ------------------------------------------------------------------ */
4152static const unsigned int usb30_pins[] = {
4153 /* PWEN, OVC */
4154 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
4155};
4156
4157static const unsigned int usb30_mux[] = {
4158 USB30_PWEN_MARK, USB30_OVC_MARK,
4159};
4160
4161/* - VIN4 ------------------------------------------------------------------- */
4162static const unsigned int vin4_data18_a_pins[] = {
4163 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
4164 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
4165 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4166 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4167 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4168 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4169 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4170 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4171 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4172};
4173
4174static const unsigned int vin4_data18_a_mux[] = {
4175 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4176 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4177 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4178 VI4_DATA10_MARK, VI4_DATA11_MARK,
4179 VI4_DATA12_MARK, VI4_DATA13_MARK,
4180 VI4_DATA14_MARK, VI4_DATA15_MARK,
4181 VI4_DATA18_MARK, VI4_DATA19_MARK,
4182 VI4_DATA20_MARK, VI4_DATA21_MARK,
4183 VI4_DATA22_MARK, VI4_DATA23_MARK,
4184};
4185
4186static const unsigned int vin4_data_a_pins[] = {
4187 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
4188 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
4189 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
4190 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
4191 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4192 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4193 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4194 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4195 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4196 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4197 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4198 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4199};
4200
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4201static const unsigned int vin4_data_a_mux[] = {
4202 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4203 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4204 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4205 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4206 VI4_DATA8_MARK, VI4_DATA9_MARK,
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4207 VI4_DATA10_MARK, VI4_DATA11_MARK,
4208 VI4_DATA12_MARK, VI4_DATA13_MARK,
4209 VI4_DATA14_MARK, VI4_DATA15_MARK,
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4210 VI4_DATA16_MARK, VI4_DATA17_MARK,
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4211 VI4_DATA18_MARK, VI4_DATA19_MARK,
4212 VI4_DATA20_MARK, VI4_DATA21_MARK,
4213 VI4_DATA22_MARK, VI4_DATA23_MARK,
4214};
4215
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4216static const unsigned int vin4_data18_b_pins[] = {
4217 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4218 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4219 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4220 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4221 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4222 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4223 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4224 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4225 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4226};
4227
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4228static const unsigned int vin4_data18_b_mux[] = {
4229 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4230 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4231 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4232 VI4_DATA10_MARK, VI4_DATA11_MARK,
4233 VI4_DATA12_MARK, VI4_DATA13_MARK,
4234 VI4_DATA14_MARK, VI4_DATA15_MARK,
4235 VI4_DATA18_MARK, VI4_DATA19_MARK,
4236 VI4_DATA20_MARK, VI4_DATA21_MARK,
4237 VI4_DATA22_MARK, VI4_DATA23_MARK,
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4238};
4239
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4240static const unsigned int vin4_data_b_pins[] = {
4241 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4242 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4243 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4244 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4245 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4246 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4247 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4248 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4249 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4250 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4251 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4252 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4253};
4254
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4255static const unsigned int vin4_data_b_mux[] = {
4256 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4257 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4258 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4259 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4260 VI4_DATA8_MARK, VI4_DATA9_MARK,
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4261 VI4_DATA10_MARK, VI4_DATA11_MARK,
4262 VI4_DATA12_MARK, VI4_DATA13_MARK,
4263 VI4_DATA14_MARK, VI4_DATA15_MARK,
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4264 VI4_DATA16_MARK, VI4_DATA17_MARK,
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4265 VI4_DATA18_MARK, VI4_DATA19_MARK,
4266 VI4_DATA20_MARK, VI4_DATA21_MARK,
4267 VI4_DATA22_MARK, VI4_DATA23_MARK,
4268};
4269
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4270static const unsigned int vin4_sync_pins[] = {
4271 /* VSYNC_N, HSYNC_N */
4272 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
4273};
4274
4275static const unsigned int vin4_sync_mux[] = {
4276 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
4277};
4278
4279static const unsigned int vin4_field_pins[] = {
4280 RCAR_GP_PIN(1, 16),
4281};
4282
4283static const unsigned int vin4_field_mux[] = {
4284 VI4_FIELD_MARK,
4285};
4286
4287static const unsigned int vin4_clkenb_pins[] = {
4288 RCAR_GP_PIN(1, 19),
4289};
4290
4291static const unsigned int vin4_clkenb_mux[] = {
4292 VI4_CLKENB_MARK,
4293};
4294
4295static const unsigned int vin4_clk_pins[] = {
4296 RCAR_GP_PIN(1, 27),
4297};
4298
4299static const unsigned int vin4_clk_mux[] = {
4300 VI4_CLK_MARK,
4301};
4302
4303/* - VIN5 ------------------------------------------------------------------- */
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4304static const unsigned int vin5_data_pins[] = {
4305 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4306 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4307 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4308 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4309 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4310 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4311 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4312 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4313};
4314
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4315static const unsigned int vin5_data_mux[] = {
4316 VI5_DATA0_MARK, VI5_DATA1_MARK,
4317 VI5_DATA2_MARK, VI5_DATA3_MARK,
4318 VI5_DATA4_MARK, VI5_DATA5_MARK,
4319 VI5_DATA6_MARK, VI5_DATA7_MARK,
4320 VI5_DATA8_MARK, VI5_DATA9_MARK,
4321 VI5_DATA10_MARK, VI5_DATA11_MARK,
4322 VI5_DATA12_MARK, VI5_DATA13_MARK,
4323 VI5_DATA14_MARK, VI5_DATA15_MARK,
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4324};
4325
4326static const unsigned int vin5_sync_pins[] = {
4327 /* VSYNC_N, HSYNC_N */
4328 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
4329};
4330
4331static const unsigned int vin5_sync_mux[] = {
4332 VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
4333};
4334
4335static const unsigned int vin5_field_pins[] = {
4336 RCAR_GP_PIN(1, 11),
4337};
4338
4339static const unsigned int vin5_field_mux[] = {
4340 VI5_FIELD_MARK,
4341};
4342
4343static const unsigned int vin5_clkenb_pins[] = {
4344 RCAR_GP_PIN(1, 20),
4345};
4346
4347static const unsigned int vin5_clkenb_mux[] = {
4348 VI5_CLKENB_MARK,
4349};
4350
4351static const unsigned int vin5_clk_pins[] = {
4352 RCAR_GP_PIN(1, 21),
4353};
4354
4355static const unsigned int vin5_clk_mux[] = {
4356 VI5_CLK_MARK,
4357};
4358
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]4359static const struct {
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4360 struct sh_pfc_pin_group common[326];
Biju Das0a362702020-10-28 10:34:24 +0000[diff] [blame]4361#ifdef CONFIG_PINCTRL_PFC_R8A77965
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4362 struct sh_pfc_pin_group automotive[31];
Biju Das0a362702020-10-28 10:34:24 +0000[diff] [blame]4363#endif
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]4364} pinmux_groups = {
4365 .common = {
4366 SH_PFC_PIN_GROUP(audio_clk_a_a),
4367 SH_PFC_PIN_GROUP(audio_clk_a_b),
4368 SH_PFC_PIN_GROUP(audio_clk_a_c),
4369 SH_PFC_PIN_GROUP(audio_clk_b_a),
4370 SH_PFC_PIN_GROUP(audio_clk_b_b),
4371 SH_PFC_PIN_GROUP(audio_clk_c_a),
4372 SH_PFC_PIN_GROUP(audio_clk_c_b),
4373 SH_PFC_PIN_GROUP(audio_clkout_a),
4374 SH_PFC_PIN_GROUP(audio_clkout_b),
4375 SH_PFC_PIN_GROUP(audio_clkout_c),
4376 SH_PFC_PIN_GROUP(audio_clkout_d),
4377 SH_PFC_PIN_GROUP(audio_clkout1_a),
4378 SH_PFC_PIN_GROUP(audio_clkout1_b),
4379 SH_PFC_PIN_GROUP(audio_clkout2_a),
4380 SH_PFC_PIN_GROUP(audio_clkout2_b),
4381 SH_PFC_PIN_GROUP(audio_clkout3_a),
4382 SH_PFC_PIN_GROUP(audio_clkout3_b),
4383 SH_PFC_PIN_GROUP(avb_link),
4384 SH_PFC_PIN_GROUP(avb_magic),
4385 SH_PFC_PIN_GROUP(avb_phy_int),
4386 SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
4387 SH_PFC_PIN_GROUP(avb_mdio),
4388 SH_PFC_PIN_GROUP(avb_mii),
4389 SH_PFC_PIN_GROUP(avb_avtp_pps),
4390 SH_PFC_PIN_GROUP(avb_avtp_match_a),
4391 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
4392 SH_PFC_PIN_GROUP(avb_avtp_match_b),
4393 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
4394 SH_PFC_PIN_GROUP(can0_data_a),
4395 SH_PFC_PIN_GROUP(can0_data_b),
4396 SH_PFC_PIN_GROUP(can1_data),
4397 SH_PFC_PIN_GROUP(can_clk),
4398 SH_PFC_PIN_GROUP(canfd0_data_a),
4399 SH_PFC_PIN_GROUP(canfd0_data_b),
4400 SH_PFC_PIN_GROUP(canfd1_data),
4401 SH_PFC_PIN_GROUP(du_rgb666),
4402 SH_PFC_PIN_GROUP(du_rgb888),
4403 SH_PFC_PIN_GROUP(du_clk_out_0),
4404 SH_PFC_PIN_GROUP(du_clk_out_1),
4405 SH_PFC_PIN_GROUP(du_sync),
4406 SH_PFC_PIN_GROUP(du_oddf),
4407 SH_PFC_PIN_GROUP(du_cde),
4408 SH_PFC_PIN_GROUP(du_disp),
4409 SH_PFC_PIN_GROUP(hscif0_data),
4410 SH_PFC_PIN_GROUP(hscif0_clk),
4411 SH_PFC_PIN_GROUP(hscif0_ctrl),
4412 SH_PFC_PIN_GROUP(hscif1_data_a),
4413 SH_PFC_PIN_GROUP(hscif1_clk_a),
4414 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
4415 SH_PFC_PIN_GROUP(hscif1_data_b),
4416 SH_PFC_PIN_GROUP(hscif1_clk_b),
4417 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
4418 SH_PFC_PIN_GROUP(hscif2_data_a),
4419 SH_PFC_PIN_GROUP(hscif2_clk_a),
4420 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
4421 SH_PFC_PIN_GROUP(hscif2_data_b),
4422 SH_PFC_PIN_GROUP(hscif2_clk_b),
4423 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4424 SH_PFC_PIN_GROUP(hscif2_data_c),
4425 SH_PFC_PIN_GROUP(hscif2_clk_c),
4426 SH_PFC_PIN_GROUP(hscif2_ctrl_c),
4427 SH_PFC_PIN_GROUP(hscif3_data_a),
4428 SH_PFC_PIN_GROUP(hscif3_clk),
4429 SH_PFC_PIN_GROUP(hscif3_ctrl),
4430 SH_PFC_PIN_GROUP(hscif3_data_b),
4431 SH_PFC_PIN_GROUP(hscif3_data_c),
4432 SH_PFC_PIN_GROUP(hscif3_data_d),
4433 SH_PFC_PIN_GROUP(hscif4_data_a),
4434 SH_PFC_PIN_GROUP(hscif4_clk),
4435 SH_PFC_PIN_GROUP(hscif4_ctrl),
4436 SH_PFC_PIN_GROUP(hscif4_data_b),
4437 SH_PFC_PIN_GROUP(i2c0),
4438 SH_PFC_PIN_GROUP(i2c1_a),
4439 SH_PFC_PIN_GROUP(i2c1_b),
4440 SH_PFC_PIN_GROUP(i2c2_a),
4441 SH_PFC_PIN_GROUP(i2c2_b),
4442 SH_PFC_PIN_GROUP(i2c3),
4443 SH_PFC_PIN_GROUP(i2c5),
4444 SH_PFC_PIN_GROUP(i2c6_a),
4445 SH_PFC_PIN_GROUP(i2c6_b),
4446 SH_PFC_PIN_GROUP(i2c6_c),
4447 SH_PFC_PIN_GROUP(intc_ex_irq0),
4448 SH_PFC_PIN_GROUP(intc_ex_irq1),
4449 SH_PFC_PIN_GROUP(intc_ex_irq2),
4450 SH_PFC_PIN_GROUP(intc_ex_irq3),
4451 SH_PFC_PIN_GROUP(intc_ex_irq4),
4452 SH_PFC_PIN_GROUP(intc_ex_irq5),
4453 SH_PFC_PIN_GROUP(msiof0_clk),
4454 SH_PFC_PIN_GROUP(msiof0_sync),
4455 SH_PFC_PIN_GROUP(msiof0_ss1),
4456 SH_PFC_PIN_GROUP(msiof0_ss2),
4457 SH_PFC_PIN_GROUP(msiof0_txd),
4458 SH_PFC_PIN_GROUP(msiof0_rxd),
4459 SH_PFC_PIN_GROUP(msiof1_clk_a),
4460 SH_PFC_PIN_GROUP(msiof1_sync_a),
4461 SH_PFC_PIN_GROUP(msiof1_ss1_a),
4462 SH_PFC_PIN_GROUP(msiof1_ss2_a),
4463 SH_PFC_PIN_GROUP(msiof1_txd_a),
4464 SH_PFC_PIN_GROUP(msiof1_rxd_a),
4465 SH_PFC_PIN_GROUP(msiof1_clk_b),
4466 SH_PFC_PIN_GROUP(msiof1_sync_b),
4467 SH_PFC_PIN_GROUP(msiof1_ss1_b),
4468 SH_PFC_PIN_GROUP(msiof1_ss2_b),
4469 SH_PFC_PIN_GROUP(msiof1_txd_b),
4470 SH_PFC_PIN_GROUP(msiof1_rxd_b),
4471 SH_PFC_PIN_GROUP(msiof1_clk_c),
4472 SH_PFC_PIN_GROUP(msiof1_sync_c),
4473 SH_PFC_PIN_GROUP(msiof1_ss1_c),
4474 SH_PFC_PIN_GROUP(msiof1_ss2_c),
4475 SH_PFC_PIN_GROUP(msiof1_txd_c),
4476 SH_PFC_PIN_GROUP(msiof1_rxd_c),
4477 SH_PFC_PIN_GROUP(msiof1_clk_d),
4478 SH_PFC_PIN_GROUP(msiof1_sync_d),
4479 SH_PFC_PIN_GROUP(msiof1_ss1_d),
4480 SH_PFC_PIN_GROUP(msiof1_ss2_d),
4481 SH_PFC_PIN_GROUP(msiof1_txd_d),
4482 SH_PFC_PIN_GROUP(msiof1_rxd_d),
4483 SH_PFC_PIN_GROUP(msiof1_clk_e),
4484 SH_PFC_PIN_GROUP(msiof1_sync_e),
4485 SH_PFC_PIN_GROUP(msiof1_ss1_e),
4486 SH_PFC_PIN_GROUP(msiof1_ss2_e),
4487 SH_PFC_PIN_GROUP(msiof1_txd_e),
4488 SH_PFC_PIN_GROUP(msiof1_rxd_e),
4489 SH_PFC_PIN_GROUP(msiof1_clk_f),
4490 SH_PFC_PIN_GROUP(msiof1_sync_f),
4491 SH_PFC_PIN_GROUP(msiof1_ss1_f),
4492 SH_PFC_PIN_GROUP(msiof1_ss2_f),
4493 SH_PFC_PIN_GROUP(msiof1_txd_f),
4494 SH_PFC_PIN_GROUP(msiof1_rxd_f),
4495 SH_PFC_PIN_GROUP(msiof1_clk_g),
4496 SH_PFC_PIN_GROUP(msiof1_sync_g),
4497 SH_PFC_PIN_GROUP(msiof1_ss1_g),
4498 SH_PFC_PIN_GROUP(msiof1_ss2_g),
4499 SH_PFC_PIN_GROUP(msiof1_txd_g),
4500 SH_PFC_PIN_GROUP(msiof1_rxd_g),
4501 SH_PFC_PIN_GROUP(msiof2_clk_a),
4502 SH_PFC_PIN_GROUP(msiof2_sync_a),
4503 SH_PFC_PIN_GROUP(msiof2_ss1_a),
4504 SH_PFC_PIN_GROUP(msiof2_ss2_a),
4505 SH_PFC_PIN_GROUP(msiof2_txd_a),
4506 SH_PFC_PIN_GROUP(msiof2_rxd_a),
4507 SH_PFC_PIN_GROUP(msiof2_clk_b),
4508 SH_PFC_PIN_GROUP(msiof2_sync_b),
4509 SH_PFC_PIN_GROUP(msiof2_ss1_b),
4510 SH_PFC_PIN_GROUP(msiof2_ss2_b),
4511 SH_PFC_PIN_GROUP(msiof2_txd_b),
4512 SH_PFC_PIN_GROUP(msiof2_rxd_b),
4513 SH_PFC_PIN_GROUP(msiof2_clk_c),
4514 SH_PFC_PIN_GROUP(msiof2_sync_c),
4515 SH_PFC_PIN_GROUP(msiof2_ss1_c),
4516 SH_PFC_PIN_GROUP(msiof2_ss2_c),
4517 SH_PFC_PIN_GROUP(msiof2_txd_c),
4518 SH_PFC_PIN_GROUP(msiof2_rxd_c),
4519 SH_PFC_PIN_GROUP(msiof2_clk_d),
4520 SH_PFC_PIN_GROUP(msiof2_sync_d),
4521 SH_PFC_PIN_GROUP(msiof2_ss1_d),
4522 SH_PFC_PIN_GROUP(msiof2_ss2_d),
4523 SH_PFC_PIN_GROUP(msiof2_txd_d),
4524 SH_PFC_PIN_GROUP(msiof2_rxd_d),
4525 SH_PFC_PIN_GROUP(msiof3_clk_a),
4526 SH_PFC_PIN_GROUP(msiof3_sync_a),
4527 SH_PFC_PIN_GROUP(msiof3_ss1_a),
4528 SH_PFC_PIN_GROUP(msiof3_ss2_a),
4529 SH_PFC_PIN_GROUP(msiof3_txd_a),
4530 SH_PFC_PIN_GROUP(msiof3_rxd_a),
4531 SH_PFC_PIN_GROUP(msiof3_clk_b),
4532 SH_PFC_PIN_GROUP(msiof3_sync_b),
4533 SH_PFC_PIN_GROUP(msiof3_ss1_b),
4534 SH_PFC_PIN_GROUP(msiof3_ss2_b),
4535 SH_PFC_PIN_GROUP(msiof3_txd_b),
4536 SH_PFC_PIN_GROUP(msiof3_rxd_b),
4537 SH_PFC_PIN_GROUP(msiof3_clk_c),
4538 SH_PFC_PIN_GROUP(msiof3_sync_c),
4539 SH_PFC_PIN_GROUP(msiof3_txd_c),
4540 SH_PFC_PIN_GROUP(msiof3_rxd_c),
4541 SH_PFC_PIN_GROUP(msiof3_clk_d),
4542 SH_PFC_PIN_GROUP(msiof3_sync_d),
4543 SH_PFC_PIN_GROUP(msiof3_ss1_d),
4544 SH_PFC_PIN_GROUP(msiof3_txd_d),
4545 SH_PFC_PIN_GROUP(msiof3_rxd_d),
4546 SH_PFC_PIN_GROUP(msiof3_clk_e),
4547 SH_PFC_PIN_GROUP(msiof3_sync_e),
4548 SH_PFC_PIN_GROUP(msiof3_ss1_e),
4549 SH_PFC_PIN_GROUP(msiof3_ss2_e),
4550 SH_PFC_PIN_GROUP(msiof3_txd_e),
4551 SH_PFC_PIN_GROUP(msiof3_rxd_e),
4552 SH_PFC_PIN_GROUP(pwm0),
4553 SH_PFC_PIN_GROUP(pwm1_a),
4554 SH_PFC_PIN_GROUP(pwm1_b),
4555 SH_PFC_PIN_GROUP(pwm2_a),
4556 SH_PFC_PIN_GROUP(pwm2_b),
4557 SH_PFC_PIN_GROUP(pwm3_a),
4558 SH_PFC_PIN_GROUP(pwm3_b),
4559 SH_PFC_PIN_GROUP(pwm4_a),
4560 SH_PFC_PIN_GROUP(pwm4_b),
4561 SH_PFC_PIN_GROUP(pwm5_a),
4562 SH_PFC_PIN_GROUP(pwm5_b),
4563 SH_PFC_PIN_GROUP(pwm6_a),
4564 SH_PFC_PIN_GROUP(pwm6_b),
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]4565 SH_PFC_PIN_GROUP(qspi0_ctrl),
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4566 BUS_DATA_PIN_GROUP(qspi0_data, 2),
4567 BUS_DATA_PIN_GROUP(qspi0_data, 4),
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]4568 SH_PFC_PIN_GROUP(qspi1_ctrl),
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4569 BUS_DATA_PIN_GROUP(qspi1_data, 2),
4570 BUS_DATA_PIN_GROUP(qspi1_data, 4),
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]4571 SH_PFC_PIN_GROUP(sata0_devslp_a),
4572 SH_PFC_PIN_GROUP(sata0_devslp_b),
4573 SH_PFC_PIN_GROUP(scif0_data),
4574 SH_PFC_PIN_GROUP(scif0_clk),
4575 SH_PFC_PIN_GROUP(scif0_ctrl),
4576 SH_PFC_PIN_GROUP(scif1_data_a),
4577 SH_PFC_PIN_GROUP(scif1_clk),
4578 SH_PFC_PIN_GROUP(scif1_ctrl),
4579 SH_PFC_PIN_GROUP(scif1_data_b),
4580 SH_PFC_PIN_GROUP(scif2_data_a),
4581 SH_PFC_PIN_GROUP(scif2_clk),
4582 SH_PFC_PIN_GROUP(scif2_data_b),
4583 SH_PFC_PIN_GROUP(scif3_data_a),
4584 SH_PFC_PIN_GROUP(scif3_clk),
4585 SH_PFC_PIN_GROUP(scif3_ctrl),
4586 SH_PFC_PIN_GROUP(scif3_data_b),
4587 SH_PFC_PIN_GROUP(scif4_data_a),
4588 SH_PFC_PIN_GROUP(scif4_clk_a),
4589 SH_PFC_PIN_GROUP(scif4_ctrl_a),
4590 SH_PFC_PIN_GROUP(scif4_data_b),
4591 SH_PFC_PIN_GROUP(scif4_clk_b),
4592 SH_PFC_PIN_GROUP(scif4_ctrl_b),
4593 SH_PFC_PIN_GROUP(scif4_data_c),
4594 SH_PFC_PIN_GROUP(scif4_clk_c),
4595 SH_PFC_PIN_GROUP(scif4_ctrl_c),
4596 SH_PFC_PIN_GROUP(scif5_data_a),
4597 SH_PFC_PIN_GROUP(scif5_clk_a),
4598 SH_PFC_PIN_GROUP(scif5_data_b),
4599 SH_PFC_PIN_GROUP(scif5_clk_b),
4600 SH_PFC_PIN_GROUP(scif_clk_a),
4601 SH_PFC_PIN_GROUP(scif_clk_b),
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4602 BUS_DATA_PIN_GROUP(sdhi0_data, 1),
4603 BUS_DATA_PIN_GROUP(sdhi0_data, 4),
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]4604 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4605 SH_PFC_PIN_GROUP(sdhi0_cd),
4606 SH_PFC_PIN_GROUP(sdhi0_wp),
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4607 BUS_DATA_PIN_GROUP(sdhi1_data, 1),
4608 BUS_DATA_PIN_GROUP(sdhi1_data, 4),
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]4609 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4610 SH_PFC_PIN_GROUP(sdhi1_cd),
4611 SH_PFC_PIN_GROUP(sdhi1_wp),
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4612 BUS_DATA_PIN_GROUP(sdhi2_data, 1),
4613 BUS_DATA_PIN_GROUP(sdhi2_data, 4),
4614 BUS_DATA_PIN_GROUP(sdhi2_data, 8),
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]4615 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4616 SH_PFC_PIN_GROUP(sdhi2_cd_a),
4617 SH_PFC_PIN_GROUP(sdhi2_wp_a),
4618 SH_PFC_PIN_GROUP(sdhi2_cd_b),
4619 SH_PFC_PIN_GROUP(sdhi2_wp_b),
4620 SH_PFC_PIN_GROUP(sdhi2_ds),
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4621 BUS_DATA_PIN_GROUP(sdhi3_data, 1),
4622 BUS_DATA_PIN_GROUP(sdhi3_data, 4),
4623 BUS_DATA_PIN_GROUP(sdhi3_data, 8),
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]4624 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4625 SH_PFC_PIN_GROUP(sdhi3_cd),
4626 SH_PFC_PIN_GROUP(sdhi3_wp),
4627 SH_PFC_PIN_GROUP(sdhi3_ds),
4628 SH_PFC_PIN_GROUP(ssi0_data),
4629 SH_PFC_PIN_GROUP(ssi01239_ctrl),
4630 SH_PFC_PIN_GROUP(ssi1_data_a),
4631 SH_PFC_PIN_GROUP(ssi1_data_b),
4632 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4633 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4634 SH_PFC_PIN_GROUP(ssi2_data_a),
4635 SH_PFC_PIN_GROUP(ssi2_data_b),
4636 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4637 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4638 SH_PFC_PIN_GROUP(ssi3_data),
4639 SH_PFC_PIN_GROUP(ssi349_ctrl),
4640 SH_PFC_PIN_GROUP(ssi4_data),
4641 SH_PFC_PIN_GROUP(ssi4_ctrl),
4642 SH_PFC_PIN_GROUP(ssi5_data),
4643 SH_PFC_PIN_GROUP(ssi5_ctrl),
4644 SH_PFC_PIN_GROUP(ssi6_data),
4645 SH_PFC_PIN_GROUP(ssi6_ctrl),
4646 SH_PFC_PIN_GROUP(ssi7_data),
4647 SH_PFC_PIN_GROUP(ssi78_ctrl),
4648 SH_PFC_PIN_GROUP(ssi8_data),
4649 SH_PFC_PIN_GROUP(ssi9_data_a),
4650 SH_PFC_PIN_GROUP(ssi9_data_b),
4651 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4652 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4653 SH_PFC_PIN_GROUP(tmu_tclk1_a),
4654 SH_PFC_PIN_GROUP(tmu_tclk1_b),
4655 SH_PFC_PIN_GROUP(tmu_tclk2_a),
4656 SH_PFC_PIN_GROUP(tmu_tclk2_b),
4657 SH_PFC_PIN_GROUP(tpu_to0),
4658 SH_PFC_PIN_GROUP(tpu_to1),
4659 SH_PFC_PIN_GROUP(tpu_to2),
4660 SH_PFC_PIN_GROUP(tpu_to3),
4661 SH_PFC_PIN_GROUP(usb0),
4662 SH_PFC_PIN_GROUP(usb1),
4663 SH_PFC_PIN_GROUP(usb30),
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4664 BUS_DATA_PIN_GROUP(vin4_data, 8, _a),
4665 BUS_DATA_PIN_GROUP(vin4_data, 10, _a),
4666 BUS_DATA_PIN_GROUP(vin4_data, 12, _a),
4667 BUS_DATA_PIN_GROUP(vin4_data, 16, _a),
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]4668 SH_PFC_PIN_GROUP(vin4_data18_a),
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4669 BUS_DATA_PIN_GROUP(vin4_data, 20, _a),
4670 BUS_DATA_PIN_GROUP(vin4_data, 24, _a),
4671 BUS_DATA_PIN_GROUP(vin4_data, 8, _b),
4672 BUS_DATA_PIN_GROUP(vin4_data, 10, _b),
4673 BUS_DATA_PIN_GROUP(vin4_data, 12, _b),
4674 BUS_DATA_PIN_GROUP(vin4_data, 16, _b),
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]4675 SH_PFC_PIN_GROUP(vin4_data18_b),
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4676 BUS_DATA_PIN_GROUP(vin4_data, 20, _b),
4677 BUS_DATA_PIN_GROUP(vin4_data, 24, _b),
4678 SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8),
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]4679 SH_PFC_PIN_GROUP(vin4_sync),
4680 SH_PFC_PIN_GROUP(vin4_field),
4681 SH_PFC_PIN_GROUP(vin4_clkenb),
4682 SH_PFC_PIN_GROUP(vin4_clk),
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4683 BUS_DATA_PIN_GROUP(vin5_data, 8),
4684 BUS_DATA_PIN_GROUP(vin5_data, 10),
4685 BUS_DATA_PIN_GROUP(vin5_data, 12),
4686 BUS_DATA_PIN_GROUP(vin5_data, 16),
4687 SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data, 8, 8),
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]4688 SH_PFC_PIN_GROUP(vin5_sync),
4689 SH_PFC_PIN_GROUP(vin5_field),
4690 SH_PFC_PIN_GROUP(vin5_clkenb),
4691 SH_PFC_PIN_GROUP(vin5_clk),
4692 },
Biju Das0a362702020-10-28 10:34:24 +0000[diff] [blame]4693#ifdef CONFIG_PINCTRL_PFC_R8A77965
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]4694 .automotive = {
4695 SH_PFC_PIN_GROUP(drif0_ctrl_a),
4696 SH_PFC_PIN_GROUP(drif0_data0_a),
4697 SH_PFC_PIN_GROUP(drif0_data1_a),
4698 SH_PFC_PIN_GROUP(drif0_ctrl_b),
4699 SH_PFC_PIN_GROUP(drif0_data0_b),
4700 SH_PFC_PIN_GROUP(drif0_data1_b),
4701 SH_PFC_PIN_GROUP(drif0_ctrl_c),
4702 SH_PFC_PIN_GROUP(drif0_data0_c),
4703 SH_PFC_PIN_GROUP(drif0_data1_c),
4704 SH_PFC_PIN_GROUP(drif1_ctrl_a),
4705 SH_PFC_PIN_GROUP(drif1_data0_a),
4706 SH_PFC_PIN_GROUP(drif1_data1_a),
4707 SH_PFC_PIN_GROUP(drif1_ctrl_b),
4708 SH_PFC_PIN_GROUP(drif1_data0_b),
4709 SH_PFC_PIN_GROUP(drif1_data1_b),
4710 SH_PFC_PIN_GROUP(drif1_ctrl_c),
4711 SH_PFC_PIN_GROUP(drif1_data0_c),
4712 SH_PFC_PIN_GROUP(drif1_data1_c),
4713 SH_PFC_PIN_GROUP(drif2_ctrl_a),
4714 SH_PFC_PIN_GROUP(drif2_data0_a),
4715 SH_PFC_PIN_GROUP(drif2_data1_a),
4716 SH_PFC_PIN_GROUP(drif2_ctrl_b),
4717 SH_PFC_PIN_GROUP(drif2_data0_b),
4718 SH_PFC_PIN_GROUP(drif2_data1_b),
4719 SH_PFC_PIN_GROUP(drif3_ctrl_a),
4720 SH_PFC_PIN_GROUP(drif3_data0_a),
4721 SH_PFC_PIN_GROUP(drif3_data1_a),
4722 SH_PFC_PIN_GROUP(drif3_ctrl_b),
4723 SH_PFC_PIN_GROUP(drif3_data0_b),
4724 SH_PFC_PIN_GROUP(drif3_data1_b),
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4725 SH_PFC_PIN_GROUP(mlb_3pin),
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]4726 }
Biju Das0a362702020-10-28 10:34:24 +0000[diff] [blame]4727#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4728};
4729
4730static const char * const audio_clk_groups[] = {
4731 "audio_clk_a_a",
4732 "audio_clk_a_b",
4733 "audio_clk_a_c",
4734 "audio_clk_b_a",
4735 "audio_clk_b_b",
4736 "audio_clk_c_a",
4737 "audio_clk_c_b",
4738 "audio_clkout_a",
4739 "audio_clkout_b",
4740 "audio_clkout_c",
4741 "audio_clkout_d",
4742 "audio_clkout1_a",
4743 "audio_clkout1_b",
4744 "audio_clkout2_a",
4745 "audio_clkout2_b",
4746 "audio_clkout3_a",
4747 "audio_clkout3_b",
4748};
4749
4750static const char * const avb_groups[] = {
4751 "avb_link",
4752 "avb_magic",
4753 "avb_phy_int",
4754 "avb_mdc", /* Deprecated, please use "avb_mdio" instead */
4755 "avb_mdio",
4756 "avb_mii",
4757 "avb_avtp_pps",
4758 "avb_avtp_match_a",
4759 "avb_avtp_capture_a",
4760 "avb_avtp_match_b",
4761 "avb_avtp_capture_b",
4762};
4763
4764static const char * const can0_groups[] = {
4765 "can0_data_a",
4766 "can0_data_b",
4767};
4768
4769static const char * const can1_groups[] = {
4770 "can1_data",
4771};
4772
4773static const char * const can_clk_groups[] = {
4774 "can_clk",
4775};
4776
4777static const char * const canfd0_groups[] = {
4778 "canfd0_data_a",
4779 "canfd0_data_b",
4780};
4781
4782static const char * const canfd1_groups[] = {
4783 "canfd1_data",
4784};
4785
Biju Das0a362702020-10-28 10:34:24 +0000[diff] [blame]4786#ifdef CONFIG_PINCTRL_PFC_R8A77965
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4787static const char * const drif0_groups[] = {
4788 "drif0_ctrl_a",
4789 "drif0_data0_a",
4790 "drif0_data1_a",
4791 "drif0_ctrl_b",
4792 "drif0_data0_b",
4793 "drif0_data1_b",
4794 "drif0_ctrl_c",
4795 "drif0_data0_c",
4796 "drif0_data1_c",
4797};
4798
4799static const char * const drif1_groups[] = {
4800 "drif1_ctrl_a",
4801 "drif1_data0_a",
4802 "drif1_data1_a",
4803 "drif1_ctrl_b",
4804 "drif1_data0_b",
4805 "drif1_data1_b",
4806 "drif1_ctrl_c",
4807 "drif1_data0_c",
4808 "drif1_data1_c",
4809};
4810
4811static const char * const drif2_groups[] = {
4812 "drif2_ctrl_a",
4813 "drif2_data0_a",
4814 "drif2_data1_a",
4815 "drif2_ctrl_b",
4816 "drif2_data0_b",
4817 "drif2_data1_b",
4818};
4819
4820static const char * const drif3_groups[] = {
4821 "drif3_ctrl_a",
4822 "drif3_data0_a",
4823 "drif3_data1_a",
4824 "drif3_ctrl_b",
4825 "drif3_data0_b",
4826 "drif3_data1_b",
4827};
Biju Das0a362702020-10-28 10:34:24 +0000[diff] [blame]4828#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4829
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4830static const char * const du_groups[] = {
4831 "du_rgb666",
4832 "du_rgb888",
4833 "du_clk_out_0",
4834 "du_clk_out_1",
4835 "du_sync",
4836 "du_oddf",
4837 "du_cde",
4838 "du_disp",
4839};
4840
4841static const char * const hscif0_groups[] = {
4842 "hscif0_data",
4843 "hscif0_clk",
4844 "hscif0_ctrl",
4845};
4846
4847static const char * const hscif1_groups[] = {
4848 "hscif1_data_a",
4849 "hscif1_clk_a",
4850 "hscif1_ctrl_a",
4851 "hscif1_data_b",
4852 "hscif1_clk_b",
4853 "hscif1_ctrl_b",
4854};
4855
4856static const char * const hscif2_groups[] = {
4857 "hscif2_data_a",
4858 "hscif2_clk_a",
4859 "hscif2_ctrl_a",
4860 "hscif2_data_b",
4861 "hscif2_clk_b",
4862 "hscif2_ctrl_b",
4863 "hscif2_data_c",
4864 "hscif2_clk_c",
4865 "hscif2_ctrl_c",
4866};
4867
4868static const char * const hscif3_groups[] = {
4869 "hscif3_data_a",
4870 "hscif3_clk",
4871 "hscif3_ctrl",
4872 "hscif3_data_b",
4873 "hscif3_data_c",
4874 "hscif3_data_d",
4875};
4876
4877static const char * const hscif4_groups[] = {
4878 "hscif4_data_a",
4879 "hscif4_clk",
4880 "hscif4_ctrl",
4881 "hscif4_data_b",
4882};
4883
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]4884static const char * const i2c0_groups[] = {
4885 "i2c0",
4886};
4887
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4888static const char * const i2c1_groups[] = {
4889 "i2c1_a",
4890 "i2c1_b",
4891};
4892
4893static const char * const i2c2_groups[] = {
4894 "i2c2_a",
4895 "i2c2_b",
4896};
4897
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]4898static const char * const i2c3_groups[] = {
4899 "i2c3",
4900};
4901
4902static const char * const i2c5_groups[] = {
4903 "i2c5",
4904};
4905
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4906static const char * const i2c6_groups[] = {
4907 "i2c6_a",
4908 "i2c6_b",
4909 "i2c6_c",
4910};
4911
4912static const char * const intc_ex_groups[] = {
4913 "intc_ex_irq0",
4914 "intc_ex_irq1",
4915 "intc_ex_irq2",
4916 "intc_ex_irq3",
4917 "intc_ex_irq4",
4918 "intc_ex_irq5",
4919};
4920
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]4921#ifdef CONFIG_PINCTRL_PFC_R8A77965
4922static const char * const mlb_3pin_groups[] = {
4923 "mlb_3pin",
4924};
4925#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
4926
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4927static const char * const msiof0_groups[] = {
4928 "msiof0_clk",
4929 "msiof0_sync",
4930 "msiof0_ss1",
4931 "msiof0_ss2",
4932 "msiof0_txd",
4933 "msiof0_rxd",
4934};
4935
4936static const char * const msiof1_groups[] = {
4937 "msiof1_clk_a",
4938 "msiof1_sync_a",
4939 "msiof1_ss1_a",
4940 "msiof1_ss2_a",
4941 "msiof1_txd_a",
4942 "msiof1_rxd_a",
4943 "msiof1_clk_b",
4944 "msiof1_sync_b",
4945 "msiof1_ss1_b",
4946 "msiof1_ss2_b",
4947 "msiof1_txd_b",
4948 "msiof1_rxd_b",
4949 "msiof1_clk_c",
4950 "msiof1_sync_c",
4951 "msiof1_ss1_c",
4952 "msiof1_ss2_c",
4953 "msiof1_txd_c",
4954 "msiof1_rxd_c",
4955 "msiof1_clk_d",
4956 "msiof1_sync_d",
4957 "msiof1_ss1_d",
4958 "msiof1_ss2_d",
4959 "msiof1_txd_d",
4960 "msiof1_rxd_d",
4961 "msiof1_clk_e",
4962 "msiof1_sync_e",
4963 "msiof1_ss1_e",
4964 "msiof1_ss2_e",
4965 "msiof1_txd_e",
4966 "msiof1_rxd_e",
4967 "msiof1_clk_f",
4968 "msiof1_sync_f",
4969 "msiof1_ss1_f",
4970 "msiof1_ss2_f",
4971 "msiof1_txd_f",
4972 "msiof1_rxd_f",
4973 "msiof1_clk_g",
4974 "msiof1_sync_g",
4975 "msiof1_ss1_g",
4976 "msiof1_ss2_g",
4977 "msiof1_txd_g",
4978 "msiof1_rxd_g",
4979};
4980
4981static const char * const msiof2_groups[] = {
4982 "msiof2_clk_a",
4983 "msiof2_sync_a",
4984 "msiof2_ss1_a",
4985 "msiof2_ss2_a",
4986 "msiof2_txd_a",
4987 "msiof2_rxd_a",
4988 "msiof2_clk_b",
4989 "msiof2_sync_b",
4990 "msiof2_ss1_b",
4991 "msiof2_ss2_b",
4992 "msiof2_txd_b",
4993 "msiof2_rxd_b",
4994 "msiof2_clk_c",
4995 "msiof2_sync_c",
4996 "msiof2_ss1_c",
4997 "msiof2_ss2_c",
4998 "msiof2_txd_c",
4999 "msiof2_rxd_c",
5000 "msiof2_clk_d",
5001 "msiof2_sync_d",
5002 "msiof2_ss1_d",
5003 "msiof2_ss2_d",
5004 "msiof2_txd_d",
5005 "msiof2_rxd_d",
5006};
5007
5008static const char * const msiof3_groups[] = {
5009 "msiof3_clk_a",
5010 "msiof3_sync_a",
5011 "msiof3_ss1_a",
5012 "msiof3_ss2_a",
5013 "msiof3_txd_a",
5014 "msiof3_rxd_a",
5015 "msiof3_clk_b",
5016 "msiof3_sync_b",
5017 "msiof3_ss1_b",
5018 "msiof3_ss2_b",
5019 "msiof3_txd_b",
5020 "msiof3_rxd_b",
5021 "msiof3_clk_c",
5022 "msiof3_sync_c",
5023 "msiof3_txd_c",
5024 "msiof3_rxd_c",
5025 "msiof3_clk_d",
5026 "msiof3_sync_d",
5027 "msiof3_ss1_d",
5028 "msiof3_txd_d",
5029 "msiof3_rxd_d",
5030 "msiof3_clk_e",
5031 "msiof3_sync_e",
5032 "msiof3_ss1_e",
5033 "msiof3_ss2_e",
5034 "msiof3_txd_e",
5035 "msiof3_rxd_e",
5036};
5037
5038static const char * const pwm0_groups[] = {
5039 "pwm0",
5040};
5041
5042static const char * const pwm1_groups[] = {
5043 "pwm1_a",
5044 "pwm1_b",
5045};
5046
5047static const char * const pwm2_groups[] = {
5048 "pwm2_a",
5049 "pwm2_b",
5050};
5051
5052static const char * const pwm3_groups[] = {
5053 "pwm3_a",
5054 "pwm3_b",
5055};
5056
5057static const char * const pwm4_groups[] = {
5058 "pwm4_a",
5059 "pwm4_b",
5060};
5061
5062static const char * const pwm5_groups[] = {
5063 "pwm5_a",
5064 "pwm5_b",
5065};
5066
5067static const char * const pwm6_groups[] = {
5068 "pwm6_a",
5069 "pwm6_b",
5070};
5071
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5072static const char * const qspi0_groups[] = {
5073 "qspi0_ctrl",
5074 "qspi0_data2",
5075 "qspi0_data4",
5076};
5077
5078static const char * const qspi1_groups[] = {
5079 "qspi1_ctrl",
5080 "qspi1_data2",
5081 "qspi1_data4",
5082};
5083
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5084static const char * const sata0_groups[] = {
5085 "sata0_devslp_a",
5086 "sata0_devslp_b",
5087};
5088
5089static const char * const scif0_groups[] = {
5090 "scif0_data",
5091 "scif0_clk",
5092 "scif0_ctrl",
5093};
5094
5095static const char * const scif1_groups[] = {
5096 "scif1_data_a",
5097 "scif1_clk",
5098 "scif1_ctrl",
5099 "scif1_data_b",
5100};
5101static const char * const scif2_groups[] = {
5102 "scif2_data_a",
5103 "scif2_clk",
5104 "scif2_data_b",
5105};
5106
5107static const char * const scif3_groups[] = {
5108 "scif3_data_a",
5109 "scif3_clk",
5110 "scif3_ctrl",
5111 "scif3_data_b",
5112};
5113
5114static const char * const scif4_groups[] = {
5115 "scif4_data_a",
5116 "scif4_clk_a",
5117 "scif4_ctrl_a",
5118 "scif4_data_b",
5119 "scif4_clk_b",
5120 "scif4_ctrl_b",
5121 "scif4_data_c",
5122 "scif4_clk_c",
5123 "scif4_ctrl_c",
5124};
5125
5126static const char * const scif5_groups[] = {
5127 "scif5_data_a",
5128 "scif5_clk_a",
5129 "scif5_data_b",
5130 "scif5_clk_b",
5131};
5132
5133static const char * const scif_clk_groups[] = {
5134 "scif_clk_a",
5135 "scif_clk_b",
5136};
5137
5138static const char * const sdhi0_groups[] = {
5139 "sdhi0_data1",
5140 "sdhi0_data4",
5141 "sdhi0_ctrl",
5142 "sdhi0_cd",
5143 "sdhi0_wp",
5144};
5145
5146static const char * const sdhi1_groups[] = {
5147 "sdhi1_data1",
5148 "sdhi1_data4",
5149 "sdhi1_ctrl",
5150 "sdhi1_cd",
5151 "sdhi1_wp",
5152};
5153
5154static const char * const sdhi2_groups[] = {
5155 "sdhi2_data1",
5156 "sdhi2_data4",
5157 "sdhi2_data8",
5158 "sdhi2_ctrl",
5159 "sdhi2_cd_a",
5160 "sdhi2_wp_a",
5161 "sdhi2_cd_b",
5162 "sdhi2_wp_b",
5163 "sdhi2_ds",
5164};
5165
5166static const char * const sdhi3_groups[] = {
5167 "sdhi3_data1",
5168 "sdhi3_data4",
5169 "sdhi3_data8",
5170 "sdhi3_ctrl",
5171 "sdhi3_cd",
5172 "sdhi3_wp",
5173 "sdhi3_ds",
5174};
5175
5176static const char * const ssi_groups[] = {
5177 "ssi0_data",
5178 "ssi01239_ctrl",
5179 "ssi1_data_a",
5180 "ssi1_data_b",
5181 "ssi1_ctrl_a",
5182 "ssi1_ctrl_b",
5183 "ssi2_data_a",
5184 "ssi2_data_b",
5185 "ssi2_ctrl_a",
5186 "ssi2_ctrl_b",
5187 "ssi3_data",
5188 "ssi349_ctrl",
5189 "ssi4_data",
5190 "ssi4_ctrl",
5191 "ssi5_data",
5192 "ssi5_ctrl",
5193 "ssi6_data",
5194 "ssi6_ctrl",
5195 "ssi7_data",
5196 "ssi78_ctrl",
5197 "ssi8_data",
5198 "ssi9_data_a",
5199 "ssi9_data_b",
5200 "ssi9_ctrl_a",
5201 "ssi9_ctrl_b",
5202};
5203
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]5204static const char * const tmu_groups[] = {
5205 "tmu_tclk1_a",
5206 "tmu_tclk1_b",
5207 "tmu_tclk2_a",
5208 "tmu_tclk2_b",
5209};
5210
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]5211static const char * const tpu_groups[] = {
5212 "tpu_to0",
5213 "tpu_to1",
5214 "tpu_to2",
5215 "tpu_to3",
5216};
5217
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5218static const char * const usb0_groups[] = {
5219 "usb0",
5220};
5221
5222static const char * const usb1_groups[] = {
5223 "usb1",
5224};
5225
5226static const char * const usb30_groups[] = {
5227 "usb30",
5228};
5229
5230static const char * const vin4_groups[] = {
5231 "vin4_data8_a",
5232 "vin4_data10_a",
5233 "vin4_data12_a",
5234 "vin4_data16_a",
5235 "vin4_data18_a",
5236 "vin4_data20_a",
5237 "vin4_data24_a",
5238 "vin4_data8_b",
5239 "vin4_data10_b",
5240 "vin4_data12_b",
5241 "vin4_data16_b",
5242 "vin4_data18_b",
5243 "vin4_data20_b",
5244 "vin4_data24_b",
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]5245 "vin4_g8",
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5246 "vin4_sync",
5247 "vin4_field",
5248 "vin4_clkenb",
5249 "vin4_clk",
5250};
5251
5252static const char * const vin5_groups[] = {
5253 "vin5_data8",
5254 "vin5_data10",
5255 "vin5_data12",
5256 "vin5_data16",
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]5257 "vin5_high8",
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5258 "vin5_sync",
5259 "vin5_field",
5260 "vin5_clkenb",
5261 "vin5_clk",
5262};
5263
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]5264static const struct {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5265 struct sh_pfc_function common[53];
Biju Das0a362702020-10-28 10:34:24 +0000[diff] [blame]5266#ifdef CONFIG_PINCTRL_PFC_R8A77965
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]5267 struct sh_pfc_function automotive[5];
Biju Das0a362702020-10-28 10:34:24 +0000[diff] [blame]5268#endif
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]5269} pinmux_functions = {
5270 .common = {
5271 SH_PFC_FUNCTION(audio_clk),
5272 SH_PFC_FUNCTION(avb),
5273 SH_PFC_FUNCTION(can0),
5274 SH_PFC_FUNCTION(can1),
5275 SH_PFC_FUNCTION(can_clk),
5276 SH_PFC_FUNCTION(canfd0),
5277 SH_PFC_FUNCTION(canfd1),
5278 SH_PFC_FUNCTION(du),
5279 SH_PFC_FUNCTION(hscif0),
5280 SH_PFC_FUNCTION(hscif1),
5281 SH_PFC_FUNCTION(hscif2),
5282 SH_PFC_FUNCTION(hscif3),
5283 SH_PFC_FUNCTION(hscif4),
5284 SH_PFC_FUNCTION(i2c0),
5285 SH_PFC_FUNCTION(i2c1),
5286 SH_PFC_FUNCTION(i2c2),
5287 SH_PFC_FUNCTION(i2c3),
5288 SH_PFC_FUNCTION(i2c5),
5289 SH_PFC_FUNCTION(i2c6),
5290 SH_PFC_FUNCTION(intc_ex),
5291 SH_PFC_FUNCTION(msiof0),
5292 SH_PFC_FUNCTION(msiof1),
5293 SH_PFC_FUNCTION(msiof2),
5294 SH_PFC_FUNCTION(msiof3),
5295 SH_PFC_FUNCTION(pwm0),
5296 SH_PFC_FUNCTION(pwm1),
5297 SH_PFC_FUNCTION(pwm2),
5298 SH_PFC_FUNCTION(pwm3),
5299 SH_PFC_FUNCTION(pwm4),
5300 SH_PFC_FUNCTION(pwm5),
5301 SH_PFC_FUNCTION(pwm6),
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5302 SH_PFC_FUNCTION(qspi0),
5303 SH_PFC_FUNCTION(qspi1),
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]5304 SH_PFC_FUNCTION(sata0),
5305 SH_PFC_FUNCTION(scif0),
5306 SH_PFC_FUNCTION(scif1),
5307 SH_PFC_FUNCTION(scif2),
5308 SH_PFC_FUNCTION(scif3),
5309 SH_PFC_FUNCTION(scif4),
5310 SH_PFC_FUNCTION(scif5),
5311 SH_PFC_FUNCTION(scif_clk),
5312 SH_PFC_FUNCTION(sdhi0),
5313 SH_PFC_FUNCTION(sdhi1),
5314 SH_PFC_FUNCTION(sdhi2),
5315 SH_PFC_FUNCTION(sdhi3),
5316 SH_PFC_FUNCTION(ssi),
5317 SH_PFC_FUNCTION(tmu),
5318 SH_PFC_FUNCTION(tpu),
5319 SH_PFC_FUNCTION(usb0),
5320 SH_PFC_FUNCTION(usb1),
5321 SH_PFC_FUNCTION(usb30),
5322 SH_PFC_FUNCTION(vin4),
5323 SH_PFC_FUNCTION(vin5),
5324 },
Biju Das0a362702020-10-28 10:34:24 +0000[diff] [blame]5325#ifdef CONFIG_PINCTRL_PFC_R8A77965
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]5326 .automotive = {
5327 SH_PFC_FUNCTION(drif0),
5328 SH_PFC_FUNCTION(drif1),
5329 SH_PFC_FUNCTION(drif2),
5330 SH_PFC_FUNCTION(drif3),
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]5331 SH_PFC_FUNCTION(mlb_3pin),
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]5332 }
Biju Das0a362702020-10-28 10:34:24 +0000[diff] [blame]5333#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5334};
5335
5336static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5337#define F_(x, y) FN_##y
5338#define FM(x) FN_##x
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]5339 { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
5340 GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5341 1, 1, 1, 1, 1),
5342 GROUP(
5343 /* GP0_31_16 RESERVED */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5344 GP_0_15_FN, GPSR0_15,
5345 GP_0_14_FN, GPSR0_14,
5346 GP_0_13_FN, GPSR0_13,
5347 GP_0_12_FN, GPSR0_12,
5348 GP_0_11_FN, GPSR0_11,
5349 GP_0_10_FN, GPSR0_10,
5350 GP_0_9_FN, GPSR0_9,
5351 GP_0_8_FN, GPSR0_8,
5352 GP_0_7_FN, GPSR0_7,
5353 GP_0_6_FN, GPSR0_6,
5354 GP_0_5_FN, GPSR0_5,
5355 GP_0_4_FN, GPSR0_4,
5356 GP_0_3_FN, GPSR0_3,
5357 GP_0_2_FN, GPSR0_2,
5358 GP_0_1_FN, GPSR0_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5359 GP_0_0_FN, GPSR0_0, ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5360 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5361 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5362 0, 0,
5363 0, 0,
5364 0, 0,
5365 GP_1_28_FN, GPSR1_28,
5366 GP_1_27_FN, GPSR1_27,
5367 GP_1_26_FN, GPSR1_26,
5368 GP_1_25_FN, GPSR1_25,
5369 GP_1_24_FN, GPSR1_24,
5370 GP_1_23_FN, GPSR1_23,
5371 GP_1_22_FN, GPSR1_22,
5372 GP_1_21_FN, GPSR1_21,
5373 GP_1_20_FN, GPSR1_20,
5374 GP_1_19_FN, GPSR1_19,
5375 GP_1_18_FN, GPSR1_18,
5376 GP_1_17_FN, GPSR1_17,
5377 GP_1_16_FN, GPSR1_16,
5378 GP_1_15_FN, GPSR1_15,
5379 GP_1_14_FN, GPSR1_14,
5380 GP_1_13_FN, GPSR1_13,
5381 GP_1_12_FN, GPSR1_12,
5382 GP_1_11_FN, GPSR1_11,
5383 GP_1_10_FN, GPSR1_10,
5384 GP_1_9_FN, GPSR1_9,
5385 GP_1_8_FN, GPSR1_8,
5386 GP_1_7_FN, GPSR1_7,
5387 GP_1_6_FN, GPSR1_6,
5388 GP_1_5_FN, GPSR1_5,
5389 GP_1_4_FN, GPSR1_4,
5390 GP_1_3_FN, GPSR1_3,
5391 GP_1_2_FN, GPSR1_2,
5392 GP_1_1_FN, GPSR1_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5393 GP_1_0_FN, GPSR1_0, ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5394 },
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]5395 { PINMUX_CFG_REG_VAR("GPSR2", 0xe6060108, 32,
5396 GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5397 1, 1, 1, 1),
5398 GROUP(
5399 /* GP2_31_15 RESERVED */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5400 GP_2_14_FN, GPSR2_14,
5401 GP_2_13_FN, GPSR2_13,
5402 GP_2_12_FN, GPSR2_12,
5403 GP_2_11_FN, GPSR2_11,
5404 GP_2_10_FN, GPSR2_10,
5405 GP_2_9_FN, GPSR2_9,
5406 GP_2_8_FN, GPSR2_8,
5407 GP_2_7_FN, GPSR2_7,
5408 GP_2_6_FN, GPSR2_6,
5409 GP_2_5_FN, GPSR2_5,
5410 GP_2_4_FN, GPSR2_4,
5411 GP_2_3_FN, GPSR2_3,
5412 GP_2_2_FN, GPSR2_2,
5413 GP_2_1_FN, GPSR2_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5414 GP_2_0_FN, GPSR2_0, ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5415 },
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]5416 { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
5417 GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5418 1, 1, 1, 1, 1),
5419 GROUP(
5420 /* GP3_31_16 RESERVED */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5421 GP_3_15_FN, GPSR3_15,
5422 GP_3_14_FN, GPSR3_14,
5423 GP_3_13_FN, GPSR3_13,
5424 GP_3_12_FN, GPSR3_12,
5425 GP_3_11_FN, GPSR3_11,
5426 GP_3_10_FN, GPSR3_10,
5427 GP_3_9_FN, GPSR3_9,
5428 GP_3_8_FN, GPSR3_8,
5429 GP_3_7_FN, GPSR3_7,
5430 GP_3_6_FN, GPSR3_6,
5431 GP_3_5_FN, GPSR3_5,
5432 GP_3_4_FN, GPSR3_4,
5433 GP_3_3_FN, GPSR3_3,
5434 GP_3_2_FN, GPSR3_2,
5435 GP_3_1_FN, GPSR3_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5436 GP_3_0_FN, GPSR3_0, ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5437 },
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]5438 { PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
5439 GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5440 1, 1, 1, 1, 1, 1, 1),
5441 GROUP(
5442 /* GP4_31_18 RESERVED */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5443 GP_4_17_FN, GPSR4_17,
5444 GP_4_16_FN, GPSR4_16,
5445 GP_4_15_FN, GPSR4_15,
5446 GP_4_14_FN, GPSR4_14,
5447 GP_4_13_FN, GPSR4_13,
5448 GP_4_12_FN, GPSR4_12,
5449 GP_4_11_FN, GPSR4_11,
5450 GP_4_10_FN, GPSR4_10,
5451 GP_4_9_FN, GPSR4_9,
5452 GP_4_8_FN, GPSR4_8,
5453 GP_4_7_FN, GPSR4_7,
5454 GP_4_6_FN, GPSR4_6,
5455 GP_4_5_FN, GPSR4_5,
5456 GP_4_4_FN, GPSR4_4,
5457 GP_4_3_FN, GPSR4_3,
5458 GP_4_2_FN, GPSR4_2,
5459 GP_4_1_FN, GPSR4_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5460 GP_4_0_FN, GPSR4_0, ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5461 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5462 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5463 0, 0,
5464 0, 0,
5465 0, 0,
5466 0, 0,
5467 0, 0,
5468 0, 0,
5469 GP_5_25_FN, GPSR5_25,
5470 GP_5_24_FN, GPSR5_24,
5471 GP_5_23_FN, GPSR5_23,
5472 GP_5_22_FN, GPSR5_22,
5473 GP_5_21_FN, GPSR5_21,
5474 GP_5_20_FN, GPSR5_20,
5475 GP_5_19_FN, GPSR5_19,
5476 GP_5_18_FN, GPSR5_18,
5477 GP_5_17_FN, GPSR5_17,
5478 GP_5_16_FN, GPSR5_16,
5479 GP_5_15_FN, GPSR5_15,
5480 GP_5_14_FN, GPSR5_14,
5481 GP_5_13_FN, GPSR5_13,
5482 GP_5_12_FN, GPSR5_12,
5483 GP_5_11_FN, GPSR5_11,
5484 GP_5_10_FN, GPSR5_10,
5485 GP_5_9_FN, GPSR5_9,
5486 GP_5_8_FN, GPSR5_8,
5487 GP_5_7_FN, GPSR5_7,
5488 GP_5_6_FN, GPSR5_6,
5489 GP_5_5_FN, GPSR5_5,
5490 GP_5_4_FN, GPSR5_4,
5491 GP_5_3_FN, GPSR5_3,
5492 GP_5_2_FN, GPSR5_2,
5493 GP_5_1_FN, GPSR5_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5494 GP_5_0_FN, GPSR5_0, ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5495 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5496 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5497 GP_6_31_FN, GPSR6_31,
5498 GP_6_30_FN, GPSR6_30,
5499 GP_6_29_FN, GPSR6_29,
5500 GP_6_28_FN, GPSR6_28,
5501 GP_6_27_FN, GPSR6_27,
5502 GP_6_26_FN, GPSR6_26,
5503 GP_6_25_FN, GPSR6_25,
5504 GP_6_24_FN, GPSR6_24,
5505 GP_6_23_FN, GPSR6_23,
5506 GP_6_22_FN, GPSR6_22,
5507 GP_6_21_FN, GPSR6_21,
5508 GP_6_20_FN, GPSR6_20,
5509 GP_6_19_FN, GPSR6_19,
5510 GP_6_18_FN, GPSR6_18,
5511 GP_6_17_FN, GPSR6_17,
5512 GP_6_16_FN, GPSR6_16,
5513 GP_6_15_FN, GPSR6_15,
5514 GP_6_14_FN, GPSR6_14,
5515 GP_6_13_FN, GPSR6_13,
5516 GP_6_12_FN, GPSR6_12,
5517 GP_6_11_FN, GPSR6_11,
5518 GP_6_10_FN, GPSR6_10,
5519 GP_6_9_FN, GPSR6_9,
5520 GP_6_8_FN, GPSR6_8,
5521 GP_6_7_FN, GPSR6_7,
5522 GP_6_6_FN, GPSR6_6,
5523 GP_6_5_FN, GPSR6_5,
5524 GP_6_4_FN, GPSR6_4,
5525 GP_6_3_FN, GPSR6_3,
5526 GP_6_2_FN, GPSR6_2,
5527 GP_6_1_FN, GPSR6_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5528 GP_6_0_FN, GPSR6_0, ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5529 },
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]5530 { PINMUX_CFG_REG_VAR("GPSR7", 0xe606011c, 32,
5531 GROUP(-28, 1, 1, 1, 1),
5532 GROUP(
5533 /* GP7_31_4 RESERVED */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5534 GP_7_3_FN, GPSR7_3,
5535 GP_7_2_FN, GPSR7_2,
5536 GP_7_1_FN, GPSR7_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5537 GP_7_0_FN, GPSR7_0, ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5538 },
5539#undef F_
5540#undef FM
5541
5542#define F_(x, y) x,
5543#define FM(x) FN_##x,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5544 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5545 IP0_31_28
5546 IP0_27_24
5547 IP0_23_20
5548 IP0_19_16
5549 IP0_15_12
5550 IP0_11_8
5551 IP0_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5552 IP0_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5553 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5554 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5555 IP1_31_28
5556 IP1_27_24
5557 IP1_23_20
5558 IP1_19_16
5559 IP1_15_12
5560 IP1_11_8
5561 IP1_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5562 IP1_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5563 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5564 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5565 IP2_31_28
5566 IP2_27_24
5567 IP2_23_20
5568 IP2_19_16
5569 IP2_15_12
5570 IP2_11_8
5571 IP2_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5572 IP2_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5573 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5574 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5575 IP3_31_28
5576 IP3_27_24
5577 IP3_23_20
5578 IP3_19_16
5579 IP3_15_12
5580 IP3_11_8
5581 IP3_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5582 IP3_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5583 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5584 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5585 IP4_31_28
5586 IP4_27_24
5587 IP4_23_20
5588 IP4_19_16
5589 IP4_15_12
5590 IP4_11_8
5591 IP4_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5592 IP4_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5593 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5594 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5595 IP5_31_28
5596 IP5_27_24
5597 IP5_23_20
5598 IP5_19_16
5599 IP5_15_12
5600 IP5_11_8
5601 IP5_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5602 IP5_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5603 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5604 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5605 IP6_31_28
5606 IP6_27_24
5607 IP6_23_20
5608 IP6_19_16
5609 IP6_15_12
5610 IP6_11_8
5611 IP6_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5612 IP6_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5613 },
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]5614 { PINMUX_CFG_REG_VAR("IPSR7", 0xe606021c, 32,
5615 GROUP(4, 4, 4, 4, -4, 4, 4, 4),
5616 GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5617 IP7_31_28
5618 IP7_27_24
5619 IP7_23_20
5620 IP7_19_16
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]5621 /* IP7_15_12 RESERVED */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5622 IP7_11_8
5623 IP7_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5624 IP7_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5625 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5626 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5627 IP8_31_28
5628 IP8_27_24
5629 IP8_23_20
5630 IP8_19_16
5631 IP8_15_12
5632 IP8_11_8
5633 IP8_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5634 IP8_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5635 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5636 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5637 IP9_31_28
5638 IP9_27_24
5639 IP9_23_20
5640 IP9_19_16
5641 IP9_15_12
5642 IP9_11_8
5643 IP9_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5644 IP9_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5645 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5646 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5647 IP10_31_28
5648 IP10_27_24
5649 IP10_23_20
5650 IP10_19_16
5651 IP10_15_12
5652 IP10_11_8
5653 IP10_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5654 IP10_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5655 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5656 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5657 IP11_31_28
5658 IP11_27_24
5659 IP11_23_20
5660 IP11_19_16
5661 IP11_15_12
5662 IP11_11_8
5663 IP11_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5664 IP11_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5665 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5666 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5667 IP12_31_28
5668 IP12_27_24
5669 IP12_23_20
5670 IP12_19_16
5671 IP12_15_12
5672 IP12_11_8
5673 IP12_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5674 IP12_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5675 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5676 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5677 IP13_31_28
5678 IP13_27_24
5679 IP13_23_20
5680 IP13_19_16
5681 IP13_15_12
5682 IP13_11_8
5683 IP13_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5684 IP13_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5685 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5686 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5687 IP14_31_28
5688 IP14_27_24
5689 IP14_23_20
5690 IP14_19_16
5691 IP14_15_12
5692 IP14_11_8
5693 IP14_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5694 IP14_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5695 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5696 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5697 IP15_31_28
5698 IP15_27_24
5699 IP15_23_20
5700 IP15_19_16
5701 IP15_15_12
5702 IP15_11_8
5703 IP15_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5704 IP15_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5705 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5706 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5707 IP16_31_28
5708 IP16_27_24
5709 IP16_23_20
5710 IP16_19_16
5711 IP16_15_12
5712 IP16_11_8
5713 IP16_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5714 IP16_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5715 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5716 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5717 IP17_31_28
5718 IP17_27_24
5719 IP17_23_20
5720 IP17_19_16
5721 IP17_15_12
5722 IP17_11_8
5723 IP17_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5724 IP17_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5725 },
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]5726 { PINMUX_CFG_REG_VAR("IPSR18", 0xe6060248, 32,
5727 GROUP(-24, 4, 4),
5728 GROUP(
5729 /* IP18_31_8 RESERVED */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5730 IP18_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5731 IP18_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5732 },
5733#undef F_
5734#undef FM
5735
5736#define F_(x, y) x,
5737#define FM(x) FN_##x,
5738 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]5739 GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, -1, 2,
5740 1, 1, 1, 2, 2, 1, 2, -3),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5741 GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5742 MOD_SEL0_31_30_29
5743 MOD_SEL0_28_27
5744 MOD_SEL0_26_25_24
5745 MOD_SEL0_23
5746 MOD_SEL0_22
5747 MOD_SEL0_21
5748 MOD_SEL0_20
5749 MOD_SEL0_19
5750 MOD_SEL0_18_17
5751 MOD_SEL0_16
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]5752 /* RESERVED 15 */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5753 MOD_SEL0_14_13
5754 MOD_SEL0_12
5755 MOD_SEL0_11
5756 MOD_SEL0_10
5757 MOD_SEL0_9_8
5758 MOD_SEL0_7_6
5759 MOD_SEL0_5
5760 MOD_SEL0_4_3
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]5761 /* RESERVED 2, 1, 0 */ ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5762 },
5763 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5764 GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]5765 1, 1, 1, -2, 1, 1, 1, 1, 1, 1, 1),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5766 GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5767 MOD_SEL1_31_30
5768 MOD_SEL1_29_28_27
5769 MOD_SEL1_26
5770 MOD_SEL1_25_24
5771 MOD_SEL1_23_22_21
5772 MOD_SEL1_20
5773 MOD_SEL1_19
5774 MOD_SEL1_18_17
5775 MOD_SEL1_16
5776 MOD_SEL1_15_14
5777 MOD_SEL1_13
5778 MOD_SEL1_12
5779 MOD_SEL1_11
5780 MOD_SEL1_10
5781 MOD_SEL1_9
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]5782 /* RESERVED 8, 7 */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5783 MOD_SEL1_6
5784 MOD_SEL1_5
5785 MOD_SEL1_4
5786 MOD_SEL1_3
5787 MOD_SEL1_2
5788 MOD_SEL1_1
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5789 MOD_SEL1_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5790 },
5791 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5792 GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]5793 -16, 1),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5794 GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5795 MOD_SEL2_31
5796 MOD_SEL2_30
5797 MOD_SEL2_29
5798 MOD_SEL2_28_27
5799 MOD_SEL2_26
5800 MOD_SEL2_25_24_23
5801 MOD_SEL2_22
5802 MOD_SEL2_21
5803 MOD_SEL2_20
5804 MOD_SEL2_19
5805 MOD_SEL2_18
5806 MOD_SEL2_17
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]5807 /* RESERVED 16-1 */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5808 MOD_SEL2_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5809 },
Marek Vasutb8227b32023-09-17 16:08:42 +0200[diff] [blame]5810 { /* sentinel */ }
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5811};
5812
5813static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5814 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5815 { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */
5816 { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */
5817 { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */
5818 { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */
5819 { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */
5820 { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */
5821 { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */
5822 { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5823 } },
5824 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5825 { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */
5826 { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */
5827 { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */
5828 { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */
5829 { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */
5830 { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */
5831 { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */
5832 { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5833 } },
5834 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5835 { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
5836 { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */
5837 { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */
5838 { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */
5839 { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */
5840 { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */
5841 { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */
5842 { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5843 } },
5844 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5845 { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */
5846 { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */
5847 { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */
5848 { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */
5849 { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */
5850 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
5851 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
5852 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5853 } },
5854 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5855 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
5856 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
5857 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
5858 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
5859 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
5860 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
5861 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
5862 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
5863 } },
5864 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5865 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
5866 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
5867 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
5868 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
5869 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
5870 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
5871 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
5872 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
5873 } },
5874 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5875 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
5876 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
5877 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
5878 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
5879 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
5880 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
5881 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
5882 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
5883 } },
5884 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5885 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
5886 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
5887 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
5888 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
5889 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
5890 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
5891 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
5892 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
5893 } },
5894 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5895 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
5896 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
5897 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
5898 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
5899 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
5900 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
5901 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
5902 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
5903 } },
5904 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5905 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5906 { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5907 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
5908 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
5909 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
5910 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
5911 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
5912 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
5913 } },
5914 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5915 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
5916 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
5917 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
5918 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
5919 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
5920 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
5921 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
5922 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
5923 } },
5924 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5925 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
5926 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
5927 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
5928 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
5929 { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
5930 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
5931 { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */
5932 { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5933 } },
5934 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5935 { PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */
5936 { PIN_FSCLKST, 20, 2 }, /* FSCLKST */
5937 { PIN_TMS, 4, 2 }, /* TMS */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5938 } },
5939 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]5940 { PIN_TDO, 28, 2 }, /* TDO */
5941 { PIN_ASEBRK, 24, 2 }, /* ASEBRK */
5942 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
5943 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
5944 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
5945 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
5946 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
5947 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5948 } },
5949 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5950 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
5951 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
5952 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
5953 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
5954 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
5955 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
5956 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
5957 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
5958 } },
5959 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5960 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
5961 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
5962 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
5963 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
5964 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
5965 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
5966 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
5967 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
5968 } },
5969 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5970 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
5971 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
5972 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
5973 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
5974 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
5975 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
5976 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
5977 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
5978 } },
5979 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5980 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
5981 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
5982 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
5983 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
5984 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
5985 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
5986 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
5987 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
5988 } },
5989 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
5990 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
5991 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
5992 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
5993 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
5994 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
5995 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
5996 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
5997 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
5998 } },
5999 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
6000 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
6001 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
6002 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
6003 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
6004 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
6005 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
6006 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
6007 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
6008 } },
6009 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
6010 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
6011 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
6012 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
6013 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
6014 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
6015 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]6016 { PIN_MLB_REF, 4, 3 }, /* MLB_REF */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6017 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
6018 } },
6019 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
6020 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
6021 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
6022 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
6023 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
6024 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
6025 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
6026 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
6027 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
6028 } },
6029 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
6030 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
6031 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
6032 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
6033 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
6034 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
6035 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
6036 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
6037 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
6038 } },
6039 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
6040 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
6041 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
6042 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
6043 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
6044 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
6045 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
6046 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
6047 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
6048 } },
6049 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
6050 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
6051 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
6052 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
6053 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
6054 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
6055 { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30 */
6056 { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31 */
6057 } },
Marek Vasutb8227b32023-09-17 16:08:42 +0200[diff] [blame]6058 { /* sentinel */ }
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6059};
6060
6061enum ioctrl_regs {
6062 POCCTRL,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]6063 TDSELCTRL,
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6064};
6065
6066static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
6067 [POCCTRL] = { 0xe6060380, },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]6068 [TDSELCTRL] = { 0xe60603c0, },
Marek Vasutb8227b32023-09-17 16:08:42 +0200[diff] [blame]6069 { /* sentinel */ }
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6070};
6071
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]6072static int r8a77965_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6073{
6074 int bit = -EINVAL;
6075
6076 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
6077
6078 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
6079 bit = pin & 0x1f;
6080
6081 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
6082 bit = (pin & 0x1f) + 12;
6083
6084 return bit;
6085}
6086
6087static const struct pinmux_bias_reg pinmux_bias_regs[] = {
6088 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]6089 [ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */
6090 [ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */
6091 [ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */
6092 [ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */
6093 [ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */
6094 [ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */
6095 [ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */
6096 [ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */
6097 [ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */
6098 [ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */
6099 [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */
6100 [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */
6101 [12] = PIN_RPC_INT_N, /* RPC_INT# */
6102 [13] = PIN_RPC_WP_N, /* RPC_WP# */
6103 [14] = PIN_RPC_RESET_N, /* RPC_RESET# */
6104 [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */
6105 [16] = PIN_AVB_RXC, /* AVB_RXC */
6106 [17] = PIN_AVB_RD0, /* AVB_RD0 */
6107 [18] = PIN_AVB_RD1, /* AVB_RD1 */
6108 [19] = PIN_AVB_RD2, /* AVB_RD2 */
6109 [20] = PIN_AVB_RD3, /* AVB_RD3 */
6110 [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */
6111 [22] = PIN_AVB_TXC, /* AVB_TXC */
6112 [23] = PIN_AVB_TD0, /* AVB_TD0 */
6113 [24] = PIN_AVB_TD1, /* AVB_TD1 */
6114 [25] = PIN_AVB_TD2, /* AVB_TD2 */
6115 [26] = PIN_AVB_TD3, /* AVB_TD3 */
6116 [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */
6117 [28] = PIN_AVB_MDIO, /* AVB_MDIO */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6118 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
6119 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
6120 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
6121 } },
6122 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
6123 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
6124 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
6125 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
6126 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
6127 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
6128 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
6129 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
6130 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
6131 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
6132 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
6133 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
6134 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
6135 [12] = RCAR_GP_PIN(1, 0), /* A0 */
6136 [13] = RCAR_GP_PIN(1, 1), /* A1 */
6137 [14] = RCAR_GP_PIN(1, 2), /* A2 */
6138 [15] = RCAR_GP_PIN(1, 3), /* A3 */
6139 [16] = RCAR_GP_PIN(1, 4), /* A4 */
6140 [17] = RCAR_GP_PIN(1, 5), /* A5 */
6141 [18] = RCAR_GP_PIN(1, 6), /* A6 */
6142 [19] = RCAR_GP_PIN(1, 7), /* A7 */
6143 [20] = RCAR_GP_PIN(1, 8), /* A8 */
6144 [21] = RCAR_GP_PIN(1, 9), /* A9 */
6145 [22] = RCAR_GP_PIN(1, 10), /* A10 */
6146 [23] = RCAR_GP_PIN(1, 11), /* A11 */
6147 [24] = RCAR_GP_PIN(1, 12), /* A12 */
6148 [25] = RCAR_GP_PIN(1, 13), /* A13 */
6149 [26] = RCAR_GP_PIN(1, 14), /* A14 */
6150 [27] = RCAR_GP_PIN(1, 15), /* A15 */
6151 [28] = RCAR_GP_PIN(1, 16), /* A16 */
6152 [29] = RCAR_GP_PIN(1, 17), /* A17 */
6153 [30] = RCAR_GP_PIN(1, 18), /* A18 */
6154 [31] = RCAR_GP_PIN(1, 19), /* A19 */
6155 } },
6156 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
6157 [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */
6158 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
6159 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */
6160 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
6161 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
6162 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
6163 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
6164 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
6165 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]6166 [ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6167 [10] = RCAR_GP_PIN(0, 0), /* D0 */
6168 [11] = RCAR_GP_PIN(0, 1), /* D1 */
6169 [12] = RCAR_GP_PIN(0, 2), /* D2 */
6170 [13] = RCAR_GP_PIN(0, 3), /* D3 */
6171 [14] = RCAR_GP_PIN(0, 4), /* D4 */
6172 [15] = RCAR_GP_PIN(0, 5), /* D5 */
6173 [16] = RCAR_GP_PIN(0, 6), /* D6 */
6174 [17] = RCAR_GP_PIN(0, 7), /* D7 */
6175 [18] = RCAR_GP_PIN(0, 8), /* D8 */
6176 [19] = RCAR_GP_PIN(0, 9), /* D9 */
6177 [20] = RCAR_GP_PIN(0, 10), /* D10 */
6178 [21] = RCAR_GP_PIN(0, 11), /* D11 */
6179 [22] = RCAR_GP_PIN(0, 12), /* D12 */
6180 [23] = RCAR_GP_PIN(0, 13), /* D13 */
6181 [24] = RCAR_GP_PIN(0, 14), /* D14 */
6182 [25] = RCAR_GP_PIN(0, 15), /* D15 */
6183 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
6184 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]6185 [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6186 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]6187 [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */
6188 [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6189 } },
6190 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]6191 [ 0] = SH_PFC_PIN_NONE,
6192 [ 1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */
6193 [ 2] = PIN_FSCLKST, /* FSCLKST */
6194 [ 3] = PIN_EXTALR, /* EXTALR*/
6195 [ 4] = PIN_TRST_N, /* TRST# */
6196 [ 5] = PIN_TCK, /* TCK */
6197 [ 6] = PIN_TMS, /* TMS */
6198 [ 7] = PIN_TDI, /* TDI */
6199 [ 8] = SH_PFC_PIN_NONE,
6200 [ 9] = PIN_ASEBRK, /* ASEBRK */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6201 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
6202 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
6203 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
6204 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
6205 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
6206 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
6207 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
6208 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
6209 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
6210 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
6211 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
6212 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
6213 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
6214 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
6215 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
6216 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
6217 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
6218 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
6219 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
6220 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
6221 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
6222 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
6223 } },
6224 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
6225 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
6226 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
6227 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
6228 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
6229 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
6230 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
6231 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
6232 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
6233 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
6234 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
6235 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
6236 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
6237 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
6238 [13] = RCAR_GP_PIN(5, 1), /* RX0 */
6239 [14] = RCAR_GP_PIN(5, 2), /* TX0 */
6240 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
6241 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
6242 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
6243 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
6244 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
6245 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
6246 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
6247 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
6248 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
6249 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
6250 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */
6251 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */
6252 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
6253 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
6254 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
6255 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
6256 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
6257 } },
6258 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
6259 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
6260 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
6261 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
6262 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
6263 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
6264 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]6265 [ 6] = PIN_MLB_REF, /* MLB_REF */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6266 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
6267 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
6268 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
6269 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
6270 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
6271 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
6272 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
6273 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
6274 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
6275 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
6276 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
6277 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
6278 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
6279 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
6280 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
6281 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
6282 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
6283 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
6284 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
6285 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
6286 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
6287 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
6288 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
6289 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
6290 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
6291 } },
6292 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
6293 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
6294 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
6295 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
6296 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
6297 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
6298 [ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */
6299 [ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame]6300 [ 7] = SH_PFC_PIN_NONE,
6301 [ 8] = SH_PFC_PIN_NONE,
6302 [ 9] = SH_PFC_PIN_NONE,
6303 [10] = SH_PFC_PIN_NONE,
6304 [11] = SH_PFC_PIN_NONE,
6305 [12] = SH_PFC_PIN_NONE,
6306 [13] = SH_PFC_PIN_NONE,
6307 [14] = SH_PFC_PIN_NONE,
6308 [15] = SH_PFC_PIN_NONE,
6309 [16] = SH_PFC_PIN_NONE,
6310 [17] = SH_PFC_PIN_NONE,
6311 [18] = SH_PFC_PIN_NONE,
6312 [19] = SH_PFC_PIN_NONE,
6313 [20] = SH_PFC_PIN_NONE,
6314 [21] = SH_PFC_PIN_NONE,
6315 [22] = SH_PFC_PIN_NONE,
6316 [23] = SH_PFC_PIN_NONE,
6317 [24] = SH_PFC_PIN_NONE,
6318 [25] = SH_PFC_PIN_NONE,
6319 [26] = SH_PFC_PIN_NONE,
6320 [27] = SH_PFC_PIN_NONE,
6321 [28] = SH_PFC_PIN_NONE,
6322 [29] = SH_PFC_PIN_NONE,
6323 [30] = SH_PFC_PIN_NONE,
6324 [31] = SH_PFC_PIN_NONE,
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6325 } },
Marek Vasutb8227b32023-09-17 16:08:42 +0200[diff] [blame]6326 { /* sentinel */ }
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6327};
6328
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]6329static const struct sh_pfc_soc_operations r8a77965_pfc_ops = {
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6330 .pin_to_pocctrl = r8a77965_pin_to_pocctrl,
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]6331 .get_bias = rcar_pinmux_get_bias,
6332 .set_bias = rcar_pinmux_set_bias,
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6333};
6334
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]6335#ifdef CONFIG_PINCTRL_PFC_R8A774B1
6336const struct sh_pfc_soc_info r8a774b1_pinmux_info = {
6337 .name = "r8a774b1_pfc",
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]6338 .ops = &r8a77965_pfc_ops,
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]6339 .unlock_reg = 0xe6060000, /* PMMR */
6340
6341 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6342
6343 .pins = pinmux_pins,
6344 .nr_pins = ARRAY_SIZE(pinmux_pins),
6345 .groups = pinmux_groups.common,
6346 .nr_groups = ARRAY_SIZE(pinmux_groups.common),
6347 .functions = pinmux_functions.common,
6348 .nr_functions = ARRAY_SIZE(pinmux_functions.common),
6349
6350 .cfg_regs = pinmux_config_regs,
6351 .drive_regs = pinmux_drive_regs,
6352 .bias_regs = pinmux_bias_regs,
6353 .ioctrl_regs = pinmux_ioctrl_regs,
6354
6355 .pinmux_data = pinmux_data,
6356 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6357};
6358#endif
6359
6360#ifdef CONFIG_PINCTRL_PFC_R8A77965
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6361const struct sh_pfc_soc_info r8a77965_pinmux_info = {
6362 .name = "r8a77965_pfc",
Marek Vasut7df55262023-01-26 21:01:42 +0100[diff] [blame]6363 .ops = &r8a77965_pfc_ops,
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6364 .unlock_reg = 0xe6060000, /* PMMR */
6365
6366 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6367
6368 .pins = pinmux_pins,
6369 .nr_pins = ARRAY_SIZE(pinmux_pins),
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]6370 .groups = pinmux_groups.common,
6371 .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6372 ARRAY_SIZE(pinmux_groups.automotive),
6373 .functions = pinmux_functions.common,
6374 .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6375 ARRAY_SIZE(pinmux_functions.automotive),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6376
6377 .cfg_regs = pinmux_config_regs,
6378 .drive_regs = pinmux_drive_regs,
6379 .bias_regs = pinmux_bias_regs,
6380 .ioctrl_regs = pinmux_ioctrl_regs,
6381
6382 .pinmux_data = pinmux_data,
6383 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6384};
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]6385#endif