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git01.mediatek.com / filogic / uboot / 0e8e9894423c9e0cc9410241eaa799a5858c7e41 / . / drivers / pinctrl / renesas / pfc-r8a77965.c
blob: fae29d535c845c483578d06080ff18cbd7bf94c8 [file] [log] [blame]
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * R8A77965 processor support - PFC hardware block.
4 *
5 * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]6 * Copyright (C) 2016-2019 Renesas Electronics Corp.
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]7 *
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame^]8 * This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]9 *
10 * R-Car Gen3 processor support - PFC hardware block.
11 *
12 * Copyright (C) 2015 Renesas Electronics Corporation
13 */
14
15#include <common.h>
16#include <dm.h>
17#include <errno.h>
18#include <dm/pinctrl.h>
19#include <linux/kernel.h>
20
21#include "sh_pfc.h"
22
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame^]23#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]24
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame^]25#define CPU_ALL_GP(fn, sfx) \
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]26 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
30 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
31 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
34 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
35 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
36 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
37 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame^]38
39#define CPU_ALL_NOGP(fn) \
40 PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \
41 PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \
42 PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \
43 PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \
44 PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \
45 PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \
46 PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \
47 PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \
48 PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \
49 PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \
50 PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \
51 PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \
52 PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \
53 PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \
54 PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \
55 PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \
56 PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \
57 PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS), \
58 PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
59 PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, CFG_FLAGS), \
60 PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
61 PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \
62 PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \
63 PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \
64 PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \
65 PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \
66 PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \
67 PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \
68 PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \
69 PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \
70 PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \
71 PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \
72 PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \
73 PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \
74 PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \
75 PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \
76 PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \
77 PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
78 PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
79 PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
80 PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \
81 PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
82
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]83/*
84 * F_() : just information
85 * FM() : macro for FN_xxx / xxx_MARK
86 */
87
88/* GPSR0 */
89#define GPSR0_15 F_(D15, IP7_11_8)
90#define GPSR0_14 F_(D14, IP7_7_4)
91#define GPSR0_13 F_(D13, IP7_3_0)
92#define GPSR0_12 F_(D12, IP6_31_28)
93#define GPSR0_11 F_(D11, IP6_27_24)
94#define GPSR0_10 F_(D10, IP6_23_20)
95#define GPSR0_9 F_(D9, IP6_19_16)
96#define GPSR0_8 F_(D8, IP6_15_12)
97#define GPSR0_7 F_(D7, IP6_11_8)
98#define GPSR0_6 F_(D6, IP6_7_4)
99#define GPSR0_5 F_(D5, IP6_3_0)
100#define GPSR0_4 F_(D4, IP5_31_28)
101#define GPSR0_3 F_(D3, IP5_27_24)
102#define GPSR0_2 F_(D2, IP5_23_20)
103#define GPSR0_1 F_(D1, IP5_19_16)
104#define GPSR0_0 F_(D0, IP5_15_12)
105
106/* GPSR1 */
107#define GPSR1_28 FM(CLKOUT)
108#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
109#define GPSR1_26 F_(WE1_N, IP5_7_4)
110#define GPSR1_25 F_(WE0_N, IP5_3_0)
111#define GPSR1_24 F_(RD_WR_N, IP4_31_28)
112#define GPSR1_23 F_(RD_N, IP4_27_24)
113#define GPSR1_22 F_(BS_N, IP4_23_20)
114#define GPSR1_21 F_(CS1_N, IP4_19_16)
115#define GPSR1_20 F_(CS0_N, IP4_15_12)
116#define GPSR1_19 F_(A19, IP4_11_8)
117#define GPSR1_18 F_(A18, IP4_7_4)
118#define GPSR1_17 F_(A17, IP4_3_0)
119#define GPSR1_16 F_(A16, IP3_31_28)
120#define GPSR1_15 F_(A15, IP3_27_24)
121#define GPSR1_14 F_(A14, IP3_23_20)
122#define GPSR1_13 F_(A13, IP3_19_16)
123#define GPSR1_12 F_(A12, IP3_15_12)
124#define GPSR1_11 F_(A11, IP3_11_8)
125#define GPSR1_10 F_(A10, IP3_7_4)
126#define GPSR1_9 F_(A9, IP3_3_0)
127#define GPSR1_8 F_(A8, IP2_31_28)
128#define GPSR1_7 F_(A7, IP2_27_24)
129#define GPSR1_6 F_(A6, IP2_23_20)
130#define GPSR1_5 F_(A5, IP2_19_16)
131#define GPSR1_4 F_(A4, IP2_15_12)
132#define GPSR1_3 F_(A3, IP2_11_8)
133#define GPSR1_2 F_(A2, IP2_7_4)
134#define GPSR1_1 F_(A1, IP2_3_0)
135#define GPSR1_0 F_(A0, IP1_31_28)
136
137/* GPSR2 */
138#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
139#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
140#define GPSR2_12 F_(AVB_LINK, IP0_15_12)
141#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
142#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
143#define GPSR2_9 F_(AVB_MDC, IP0_3_0)
144#define GPSR2_8 F_(PWM2_A, IP1_27_24)
145#define GPSR2_7 F_(PWM1_A, IP1_23_20)
146#define GPSR2_6 F_(PWM0, IP1_19_16)
147#define GPSR2_5 F_(IRQ5, IP1_15_12)
148#define GPSR2_4 F_(IRQ4, IP1_11_8)
149#define GPSR2_3 F_(IRQ3, IP1_7_4)
150#define GPSR2_2 F_(IRQ2, IP1_3_0)
151#define GPSR2_1 F_(IRQ1, IP0_31_28)
152#define GPSR2_0 F_(IRQ0, IP0_27_24)
153
154/* GPSR3 */
155#define GPSR3_15 F_(SD1_WP, IP11_23_20)
156#define GPSR3_14 F_(SD1_CD, IP11_19_16)
157#define GPSR3_13 F_(SD0_WP, IP11_15_12)
158#define GPSR3_12 F_(SD0_CD, IP11_11_8)
159#define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
160#define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
161#define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
162#define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
163#define GPSR3_7 F_(SD1_CMD, IP8_15_12)
164#define GPSR3_6 F_(SD1_CLK, IP8_11_8)
165#define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
166#define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
167#define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
168#define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
169#define GPSR3_1 F_(SD0_CMD, IP7_23_20)
170#define GPSR3_0 F_(SD0_CLK, IP7_19_16)
171
172/* GPSR4 */
173#define GPSR4_17 F_(SD3_DS, IP11_7_4)
174#define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
175#define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
176#define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
177#define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
178#define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
179#define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
180#define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
181#define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
182#define GPSR4_8 F_(SD3_CMD, IP10_3_0)
183#define GPSR4_7 F_(SD3_CLK, IP9_31_28)
184#define GPSR4_6 F_(SD2_DS, IP9_27_24)
185#define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
186#define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
187#define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
188#define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
189#define GPSR4_1 F_(SD2_CMD, IP9_7_4)
190#define GPSR4_0 F_(SD2_CLK, IP9_3_0)
191
192/* GPSR5 */
193#define GPSR5_25 F_(MLB_DAT, IP14_19_16)
194#define GPSR5_24 F_(MLB_SIG, IP14_15_12)
195#define GPSR5_23 F_(MLB_CLK, IP14_11_8)
196#define GPSR5_22 FM(MSIOF0_RXD)
197#define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
198#define GPSR5_20 FM(MSIOF0_TXD)
199#define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
200#define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
201#define GPSR5_17 FM(MSIOF0_SCK)
202#define GPSR5_16 F_(HRTS0_N, IP13_27_24)
203#define GPSR5_15 F_(HCTS0_N, IP13_23_20)
204#define GPSR5_14 F_(HTX0, IP13_19_16)
205#define GPSR5_13 F_(HRX0, IP13_15_12)
206#define GPSR5_12 F_(HSCK0, IP13_11_8)
207#define GPSR5_11 F_(RX2_A, IP13_7_4)
208#define GPSR5_10 F_(TX2_A, IP13_3_0)
209#define GPSR5_9 F_(SCK2, IP12_31_28)
210#define GPSR5_8 F_(RTS1_N, IP12_27_24)
211#define GPSR5_7 F_(CTS1_N, IP12_23_20)
212#define GPSR5_6 F_(TX1_A, IP12_19_16)
213#define GPSR5_5 F_(RX1_A, IP12_15_12)
214#define GPSR5_4 F_(RTS0_N, IP12_11_8)
215#define GPSR5_3 F_(CTS0_N, IP12_7_4)
216#define GPSR5_2 F_(TX0, IP12_3_0)
217#define GPSR5_1 F_(RX0, IP11_31_28)
218#define GPSR5_0 F_(SCK0, IP11_27_24)
219
220/* GPSR6 */
221#define GPSR6_31 F_(GP6_31, IP18_7_4)
222#define GPSR6_30 F_(GP6_30, IP18_3_0)
223#define GPSR6_29 F_(USB30_OVC, IP17_31_28)
224#define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
225#define GPSR6_27 F_(USB1_OVC, IP17_23_20)
226#define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
227#define GPSR6_25 F_(USB0_OVC, IP17_15_12)
228#define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
229#define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
230#define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
231#define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
232#define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
233#define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
234#define GPSR6_18 F_(SSI_WS78, IP16_19_16)
235#define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
236#define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
237#define GPSR6_15 F_(SSI_WS6, IP16_7_4)
238#define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
239#define GPSR6_13 FM(SSI_SDATA5)
240#define GPSR6_12 FM(SSI_WS5)
241#define GPSR6_11 FM(SSI_SCK5)
242#define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
243#define GPSR6_9 F_(SSI_WS4, IP15_27_24)
244#define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
245#define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
246#define GPSR6_6 F_(SSI_WS349, IP15_15_12)
247#define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
248#define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
249#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
250#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
251#define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
252#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
253
254/* GPSR7 */
255#define GPSR7_3 FM(GP7_03)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]256#define GPSR7_2 FM(GP7_02)
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]257#define GPSR7_1 FM(AVS2)
258#define GPSR7_0 FM(AVS1)
259
260
261/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
262#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275#define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276#define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289
290/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
291#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300#define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320
321/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
322#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337#define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338#define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343#define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344#define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345#define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354#define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356
357/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
358#define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359#define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360#define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
361#define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
362#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
363#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
364#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
365#define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
366#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
367#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
368#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
369#define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
370#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
371#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
372#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
373#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
374#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
375#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
376#define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
377#define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
378#define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
379#define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
380#define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
381#define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
382#define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
383#define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
384#define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
385#define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
386
387/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
388#define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
389#define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
390#define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
391#define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
392#define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
393#define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
394#define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
395#define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
396#define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
397#define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
398#define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
399#define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
400#define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
401#define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
402#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
403#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
404#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]405#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]406#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
407#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
408#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
409#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
410#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
411#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
412#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
413#define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
414#define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
415
416#define PINMUX_GPSR \
417\
418 GPSR6_31 \
419 GPSR6_30 \
420 GPSR6_29 \
421 GPSR1_28 GPSR6_28 \
422 GPSR1_27 GPSR6_27 \
423 GPSR1_26 GPSR6_26 \
424 GPSR1_25 GPSR5_25 GPSR6_25 \
425 GPSR1_24 GPSR5_24 GPSR6_24 \
426 GPSR1_23 GPSR5_23 GPSR6_23 \
427 GPSR1_22 GPSR5_22 GPSR6_22 \
428 GPSR1_21 GPSR5_21 GPSR6_21 \
429 GPSR1_20 GPSR5_20 GPSR6_20 \
430 GPSR1_19 GPSR5_19 GPSR6_19 \
431 GPSR1_18 GPSR5_18 GPSR6_18 \
432 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
433 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
434GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
435GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
436GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
437GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
438GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
439GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
440GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
441GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
442GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
443GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
444GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
445GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
446GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
447GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
448GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
449GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
450
451#define PINMUX_IPSR \
452\
453FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
454FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
455FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
456FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
457FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
458FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
459FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
460FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
461\
462FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
463FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
464FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
465FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
466FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
467FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
468FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
469FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
470\
471FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
472FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
473FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
474FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
475FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
476FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
477FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
478FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
479\
480FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
481FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
482FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
483FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
484FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
485FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
486FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
487FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
488\
489FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
490FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
491FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
492FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
493FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
494FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
495FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
496FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
497
498/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
499#define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
500#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
501#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
502#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
503#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
504#define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
505#define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
506#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
507#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
508#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
509#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
510#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
511#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
512#define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
513#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
514#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
515#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]516#define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3)
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]517
518/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
519#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
520#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
521#define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
522#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
523#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
524#define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
525#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
526#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
527#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
528#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
529#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
530#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
531#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
532#define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
533#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
534#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
535#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
536#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
537#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
538#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
539#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
540#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
541
542/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
543#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
544#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
545#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
546#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
547#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
548#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]549#define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1)
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]550#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
551#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
552#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]553#define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1)
554#define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1)
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]555#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
556
557#define PINMUX_MOD_SELS \
558\
559MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
560 MOD_SEL2_30 \
561 MOD_SEL1_29_28_27 MOD_SEL2_29 \
562MOD_SEL0_28_27 MOD_SEL2_28_27 \
563MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
564 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
565MOD_SEL0_23 MOD_SEL1_23_22_21 \
566MOD_SEL0_22 MOD_SEL2_22 \
567MOD_SEL0_21 MOD_SEL2_21 \
568MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
569MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
570MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
571 MOD_SEL2_17 \
572MOD_SEL0_16 MOD_SEL1_16 \
573 MOD_SEL1_15_14 \
574MOD_SEL0_14_13 \
575 MOD_SEL1_13 \
576MOD_SEL0_12 MOD_SEL1_12 \
577MOD_SEL0_11 MOD_SEL1_11 \
578MOD_SEL0_10 MOD_SEL1_10 \
579MOD_SEL0_9_8 MOD_SEL1_9 \
580MOD_SEL0_7_6 \
581 MOD_SEL1_6 \
582MOD_SEL0_5 MOD_SEL1_5 \
583MOD_SEL0_4_3 MOD_SEL1_4 \
584 MOD_SEL1_3 \
585 MOD_SEL1_2 \
586 MOD_SEL1_1 \
587 MOD_SEL1_0 MOD_SEL2_0
588
589/*
590 * These pins are not able to be muxed but have other properties
591 * that can be set, such as drive-strength or pull-up/pull-down enable.
592 */
593#define PINMUX_STATIC \
594 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
595 FM(QSPI0_IO2) FM(QSPI0_IO3) \
596 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
597 FM(QSPI1_IO2) FM(QSPI1_IO3) \
598 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
599 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
600 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
601 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
602 FM(PRESETOUT) \
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]603 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN3) \
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]604 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
605
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]606#define PINMUX_PHYS \
607 FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
608
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]609enum {
610 PINMUX_RESERVED = 0,
611
612 PINMUX_DATA_BEGIN,
613 GP_ALL(DATA),
614 PINMUX_DATA_END,
615
616#define F_(x, y)
617#define FM(x) FN_##x,
618 PINMUX_FUNCTION_BEGIN,
619 GP_ALL(FN),
620 PINMUX_GPSR
621 PINMUX_IPSR
622 PINMUX_MOD_SELS
623 PINMUX_FUNCTION_END,
624#undef F_
625#undef FM
626
627#define F_(x, y)
628#define FM(x) x##_MARK,
629 PINMUX_MARK_BEGIN,
630 PINMUX_GPSR
631 PINMUX_IPSR
632 PINMUX_MOD_SELS
633 PINMUX_STATIC
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]634 PINMUX_PHYS
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]635 PINMUX_MARK_END,
636#undef F_
637#undef FM
638};
639
640static const u16 pinmux_data[] = {
641 PINMUX_DATA_GP_ALL(),
642
643 PINMUX_SINGLE(AVS1),
644 PINMUX_SINGLE(AVS2),
645 PINMUX_SINGLE(CLKOUT),
646 PINMUX_SINGLE(GP7_03),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]647 PINMUX_SINGLE(GP7_02),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]648 PINMUX_SINGLE(MSIOF0_RXD),
649 PINMUX_SINGLE(MSIOF0_SCK),
650 PINMUX_SINGLE(MSIOF0_TXD),
651 PINMUX_SINGLE(SSI_SCK5),
652 PINMUX_SINGLE(SSI_SDATA5),
653 PINMUX_SINGLE(SSI_WS5),
654
655 /* IPSR0 */
656 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
657 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
658
659 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
660 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
661 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
662
663 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
664 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
665 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
666
667 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
668 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
669 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
670 PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A),
671
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]672 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
673 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
674 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
675 PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]676
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]677 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
678 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
679 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
680 PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]681
682 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
683 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
684 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
685 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
686 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
687 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
688 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
689
690 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
691 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
692 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
693 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
694 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
695 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
696 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
697
698 /* IPSR1 */
699 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
700 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
701 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
702 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
703 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
704 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
705
706 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
707 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
708 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
709 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
710 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
711 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
712
713 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
714 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
715 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
716 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
717 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
718 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
719
720 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
721 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
722 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
723 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
724 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
725 PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B),
726 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
727
728 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
729 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
730 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
731 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
732
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]733 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
734 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
735 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
736 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]737 PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]738
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]739 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
740 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
741 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
742 PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]743
744 PINMUX_IPSR_GPSR(IP1_31_28, A0),
745 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
746 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
747 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
748 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
749 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
750
751 /* IPSR2 */
752 PINMUX_IPSR_GPSR(IP2_3_0, A1),
753 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
754 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
755 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
756 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
757 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
758
759 PINMUX_IPSR_GPSR(IP2_7_4, A2),
760 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
761 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
762 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
763 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
764 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
765
766 PINMUX_IPSR_GPSR(IP2_11_8, A3),
767 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
768 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
769 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
770 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
771 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
772
773 PINMUX_IPSR_GPSR(IP2_15_12, A4),
774 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
775 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
776 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
777 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
778 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
779
780 PINMUX_IPSR_GPSR(IP2_19_16, A5),
781 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
782 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
783 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
784 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
785 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
786 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
787
788 PINMUX_IPSR_GPSR(IP2_23_20, A6),
789 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
790 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
791 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
792 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
793 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
794 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
795
796 PINMUX_IPSR_GPSR(IP2_27_24, A7),
797 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
798 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
799 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
800 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
801 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
802 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
803
804 PINMUX_IPSR_GPSR(IP2_31_28, A8),
805 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
806 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
807 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
808 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
809 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
810 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
811
812 /* IPSR3 */
813 PINMUX_IPSR_GPSR(IP3_3_0, A9),
814 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
815 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
816 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
817
818 PINMUX_IPSR_GPSR(IP3_7_4, A10),
819 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
820 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
821 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
822
823 PINMUX_IPSR_GPSR(IP3_11_8, A11),
824 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
825 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
826 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
827 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
828 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
829 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
830 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
831 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
832
833 PINMUX_IPSR_GPSR(IP3_15_12, A12),
834 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
835 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
836 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
837 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
838 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
839
840 PINMUX_IPSR_GPSR(IP3_19_16, A13),
841 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
842 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
843 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
844 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
845 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
846
847 PINMUX_IPSR_GPSR(IP3_23_20, A14),
848 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
849 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
850 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
851 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
852 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
853
854 PINMUX_IPSR_GPSR(IP3_27_24, A15),
855 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
856 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
857 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
858 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
859 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
860
861 PINMUX_IPSR_GPSR(IP3_31_28, A16),
862 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
863 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
864 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
865
866 /* IPSR4 */
867 PINMUX_IPSR_GPSR(IP4_3_0, A17),
868 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
869 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
870 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
871
872 PINMUX_IPSR_GPSR(IP4_7_4, A18),
873 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
874 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
875 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
876
877 PINMUX_IPSR_GPSR(IP4_11_8, A19),
878 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
879 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
880 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
881
882 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
883 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
884
885 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
886 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
887 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
888
889 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
890 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
891 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
892 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
893 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
894 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
895 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
896 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
897
898 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
899 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
900 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
901 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
902 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
903 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
904
905 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
906 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
907 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
908 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
909 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
910 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
911
912 /* IPSR5 */
913 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
914 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
915 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
916 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
917 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
918 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
919 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
920
921 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
922 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
923 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
924 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
925 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
926 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
927 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
928 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
929
930 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
931 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
932 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
933 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
934
935 PINMUX_IPSR_GPSR(IP5_15_12, D0),
936 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
937 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
938 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
939 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
940
941 PINMUX_IPSR_GPSR(IP5_19_16, D1),
942 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
943 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
944 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
945 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
946
947 PINMUX_IPSR_GPSR(IP5_23_20, D2),
948 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
949 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
950 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
951
952 PINMUX_IPSR_GPSR(IP5_27_24, D3),
953 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
954 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
955 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
956
957 PINMUX_IPSR_GPSR(IP5_31_28, D4),
958 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
959 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
960 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
961
962 /* IPSR6 */
963 PINMUX_IPSR_GPSR(IP6_3_0, D5),
964 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
965 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
966 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
967
968 PINMUX_IPSR_GPSR(IP6_7_4, D6),
969 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
970 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
971 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
972
973 PINMUX_IPSR_GPSR(IP6_11_8, D7),
974 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
975 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
976 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
977
978 PINMUX_IPSR_GPSR(IP6_15_12, D8),
979 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
980 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
981 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
982 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
983 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
984
985 PINMUX_IPSR_GPSR(IP6_19_16, D9),
986 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
987 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
988 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
989 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
990
991 PINMUX_IPSR_GPSR(IP6_23_20, D10),
992 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
993 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
994 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
995 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
996 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
997 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
998
999 PINMUX_IPSR_GPSR(IP6_27_24, D11),
1000 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
1001 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
1002 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
1003 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
1004 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
1005 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
1006
1007 PINMUX_IPSR_GPSR(IP6_31_28, D12),
1008 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
1009 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
1010 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
1011 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
1012 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
1013
1014 /* IPSR7 */
1015 PINMUX_IPSR_GPSR(IP7_3_0, D13),
1016 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
1017 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
1018 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
1019 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
1020 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
1021
1022 PINMUX_IPSR_GPSR(IP7_7_4, D14),
1023 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
1024 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
1025 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
1026 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
1027 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
1028 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
1029
1030 PINMUX_IPSR_GPSR(IP7_11_8, D15),
1031 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
1032 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
1033 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
1034 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
1035 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
1036 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
1037
1038 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
1039 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
1040 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
1041
1042 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
1043 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
1044 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
1045
1046 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
1047 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
1048 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
1049 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
1050
1051 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
1052 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
1053 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
1054 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
1055
1056 /* IPSR8 */
1057 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
1058 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1059 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1060 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
1061
1062 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1063 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1064 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1065 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
1066
1067 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1068 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1069 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
1070
1071 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1072 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1073 PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1074 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1075 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
1076
1077 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1078 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1079 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1080 PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1081 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1082 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1083
1084 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1085 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1086 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1087 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1088 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1089 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1090
1091 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1092 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1093 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1094 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1095 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1096 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1097
1098 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1099 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1100 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1101 PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1102 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1103 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1104
1105 /* IPSR9 */
1106 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1107 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
1108
1109 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
1110 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
1111
1112 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
1113 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
1114
1115 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1116 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
1117
1118 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1119 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
1120
1121 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1122 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
1123
1124 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1125 PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1126 PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B),
1127
1128 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1129 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
1130
1131 /* IPSR10 */
1132 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
1133 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
1134
1135 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
1136 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
1137
1138 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1139 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
1140
1141 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
1142 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
1143
1144 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
1145 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
1146
1147 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
1148 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
1149 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
1150
1151 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
1152 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
1153 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
1154
1155 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
1156 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
1157 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
1158
1159 /* IPSR11 */
1160 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
1161 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
1162 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
1163
1164 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
1165 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1166
1167 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1168 PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDF_0),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1169 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1170 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1171
1172 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1173 PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDF_0),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1174 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1175
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1176 PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0),
1177 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0),
1178 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1179 PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1180
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1181 PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0),
1182 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0),
1183 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1184 PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1185
1186 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1187 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1188 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1189 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1190 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1191 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1192 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1193 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1194 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
1195 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
1196
1197 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
1198 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
1199 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
1200 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1201 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
1202
1203 /* IPSR12 */
1204 PINMUX_IPSR_GPSR(IP12_3_0, TX0),
1205 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
1206 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1207 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1208 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
1209
1210 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
1211 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1212 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1213 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1214 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1215 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1216 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1217 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1218
1219 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
1220 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1221 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1222 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1223 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1224 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1225 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1226 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1227
1228 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
1229 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
1230 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1231 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1232 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1233
1234 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
1235 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
1236 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1237 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1238 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
1239
1240 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
1241 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1242 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1243 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1244 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1245 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1246 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1247
1248 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N),
1249 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1250 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1251 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1252 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1253 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
1254 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1255
1256 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
1257 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
1258 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1259 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1260 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1261 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1262 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
1263
1264 /* IPSR13 */
1265 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
1266 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
1267 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1268 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1269 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
1270 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
1271
1272 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1273 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1274 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1275 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1276 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1277 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
1278
1279 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1280 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1281 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1282 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
1283 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1284 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1285 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1286 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
1287
1288 PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
1289 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
1290 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1),
1291 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1292 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1293 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
1294
1295 PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
1296 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
1297 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1),
1298 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1299 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1300 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
1301
1302 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
1303 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
1304 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
1305 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0),
1306 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1307 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1308 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1309 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
1310
1311 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
1312 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
1313 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
1314 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0),
1315 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1316 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
1317 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
1318
1319 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
1320 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
1321 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
1322 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
1323
1324 /* IPSR14 */
1325 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1326 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1327 PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0),
1328 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1329 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
1330 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1331 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
1332 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1),
1333
1334 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1335 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1336 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1337 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1338 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
1339 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1340 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
1341 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1342
1343 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1344 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1345 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
1346
1347 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
1348 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
1349 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1350 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
1351
1352 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
1353 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
1354 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1355
1356 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
1357 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1358
1359 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
1360 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1361
1362 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
1363 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1364
1365 /* IPSR15 */
1366 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0),
1367
1368 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0),
1369 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1),
1370
1371 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
1372 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1373 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1374
1375 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
1376 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1377 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1378 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1379
1380 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
1381 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1382 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1383 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
1384 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1385 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
1386 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
1387
1388 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
1389 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
1390 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1391 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1392 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1393 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1394 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1395
1396 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
1397 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
1398 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1399 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1400 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1401 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1402 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1403
1404 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
1405 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
1406 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1407 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1408 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1409 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
1410 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
1411
1412 /* IPSR16 */
1413 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
1414 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1415
1416 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
1417 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
1418
1419 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1420 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1421 PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A),
1422
1423 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
1424 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
1425 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1426 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
1427 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1428 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1429 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1430
1431 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
1432 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
1433 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1434 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1435 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1436 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1437 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1438
1439 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
1440 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1441 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1442 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1443 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1444 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1445 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
1446 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
1447
1448 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1449 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1450 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1451 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1452 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1453 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
1454 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
1455
1456 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0),
1457 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
1458 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1459 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
1460 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1),
1461 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1462 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1463 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
1464
1465 /* IPSR17 */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1466 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1467
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1468 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1469 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
1470 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1471 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
1472 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0),
1473
1474 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1475 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1476 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
1477 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1478 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
1479 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1480 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
1481
1482 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
1483 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
1484 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
1485 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
1486 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
1487 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
1488
1489 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
1490 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
1491 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0),
1492 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
1493 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1494 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
1495 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1496 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1497 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
1498
1499 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
1500 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
1501 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0),
1502 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1503 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1504 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
1505 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1506 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
1507 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
1508
1509 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
1510 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
1511 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1),
1512 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1513 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
1514 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1515 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
1516 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
1517 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1518 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1519 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
1520
1521 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
1522 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
1523 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1),
1524 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1525 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1526 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1527 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
1528 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
1529 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1530
1531 /* IPSR18 */
1532 PINMUX_IPSR_GPSR(IP18_3_0, GP6_30),
1533 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
1534 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1),
1535 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1536 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1537 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1538 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
1539 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1540 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1541
1542 PINMUX_IPSR_GPSR(IP18_7_4, GP6_31),
1543 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
1544 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1),
1545 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1546 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1547 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1548 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
1549 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1550 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
1551
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1552/*
1553 * Static pins can not be muxed between different functions but
1554 * still need mark entries in the pinmux list. Add each static
1555 * pin to the list without an associated function. The sh-pfc
1556 * core will do the right thing and skip trying to mux the pin
1557 * while still applying configuration to it.
1558 */
1559#define FM(x) PINMUX_DATA(x##_MARK, 0),
1560 PINMUX_STATIC
1561#undef FM
1562};
1563
1564/*
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame^]1565 * Pins not associated with a GPIO port.
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1566 */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame^]1567enum {
1568 GP_ASSIGN_LAST(),
1569 NOGP_ALL(),
1570};
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1571
1572static const struct sh_pfc_pin pinmux_pins[] = {
1573 PINMUX_GPIO_GP_ALL(),
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame^]1574 PINMUX_NOGP_ALL(),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1575};
1576
1577/* - AUDIO CLOCK ------------------------------------------------------------ */
1578static const unsigned int audio_clk_a_a_pins[] = {
1579 /* CLK A */
1580 RCAR_GP_PIN(6, 22),
1581};
1582static const unsigned int audio_clk_a_a_mux[] = {
1583 AUDIO_CLKA_A_MARK,
1584};
1585static const unsigned int audio_clk_a_b_pins[] = {
1586 /* CLK A */
1587 RCAR_GP_PIN(5, 4),
1588};
1589static const unsigned int audio_clk_a_b_mux[] = {
1590 AUDIO_CLKA_B_MARK,
1591};
1592static const unsigned int audio_clk_a_c_pins[] = {
1593 /* CLK A */
1594 RCAR_GP_PIN(5, 19),
1595};
1596static const unsigned int audio_clk_a_c_mux[] = {
1597 AUDIO_CLKA_C_MARK,
1598};
1599static const unsigned int audio_clk_b_a_pins[] = {
1600 /* CLK B */
1601 RCAR_GP_PIN(5, 12),
1602};
1603static const unsigned int audio_clk_b_a_mux[] = {
1604 AUDIO_CLKB_A_MARK,
1605};
1606static const unsigned int audio_clk_b_b_pins[] = {
1607 /* CLK B */
1608 RCAR_GP_PIN(6, 23),
1609};
1610static const unsigned int audio_clk_b_b_mux[] = {
1611 AUDIO_CLKB_B_MARK,
1612};
1613static const unsigned int audio_clk_c_a_pins[] = {
1614 /* CLK C */
1615 RCAR_GP_PIN(5, 21),
1616};
1617static const unsigned int audio_clk_c_a_mux[] = {
1618 AUDIO_CLKC_A_MARK,
1619};
1620static const unsigned int audio_clk_c_b_pins[] = {
1621 /* CLK C */
1622 RCAR_GP_PIN(5, 0),
1623};
1624static const unsigned int audio_clk_c_b_mux[] = {
1625 AUDIO_CLKC_B_MARK,
1626};
1627static const unsigned int audio_clkout_a_pins[] = {
1628 /* CLKOUT */
1629 RCAR_GP_PIN(5, 18),
1630};
1631static const unsigned int audio_clkout_a_mux[] = {
1632 AUDIO_CLKOUT_A_MARK,
1633};
1634static const unsigned int audio_clkout_b_pins[] = {
1635 /* CLKOUT */
1636 RCAR_GP_PIN(6, 28),
1637};
1638static const unsigned int audio_clkout_b_mux[] = {
1639 AUDIO_CLKOUT_B_MARK,
1640};
1641static const unsigned int audio_clkout_c_pins[] = {
1642 /* CLKOUT */
1643 RCAR_GP_PIN(5, 3),
1644};
1645static const unsigned int audio_clkout_c_mux[] = {
1646 AUDIO_CLKOUT_C_MARK,
1647};
1648static const unsigned int audio_clkout_d_pins[] = {
1649 /* CLKOUT */
1650 RCAR_GP_PIN(5, 21),
1651};
1652static const unsigned int audio_clkout_d_mux[] = {
1653 AUDIO_CLKOUT_D_MARK,
1654};
1655static const unsigned int audio_clkout1_a_pins[] = {
1656 /* CLKOUT1 */
1657 RCAR_GP_PIN(5, 15),
1658};
1659static const unsigned int audio_clkout1_a_mux[] = {
1660 AUDIO_CLKOUT1_A_MARK,
1661};
1662static const unsigned int audio_clkout1_b_pins[] = {
1663 /* CLKOUT1 */
1664 RCAR_GP_PIN(6, 29),
1665};
1666static const unsigned int audio_clkout1_b_mux[] = {
1667 AUDIO_CLKOUT1_B_MARK,
1668};
1669static const unsigned int audio_clkout2_a_pins[] = {
1670 /* CLKOUT2 */
1671 RCAR_GP_PIN(5, 16),
1672};
1673static const unsigned int audio_clkout2_a_mux[] = {
1674 AUDIO_CLKOUT2_A_MARK,
1675};
1676static const unsigned int audio_clkout2_b_pins[] = {
1677 /* CLKOUT2 */
1678 RCAR_GP_PIN(6, 30),
1679};
1680static const unsigned int audio_clkout2_b_mux[] = {
1681 AUDIO_CLKOUT2_B_MARK,
1682};
1683
1684static const unsigned int audio_clkout3_a_pins[] = {
1685 /* CLKOUT3 */
1686 RCAR_GP_PIN(5, 19),
1687};
1688static const unsigned int audio_clkout3_a_mux[] = {
1689 AUDIO_CLKOUT3_A_MARK,
1690};
1691static const unsigned int audio_clkout3_b_pins[] = {
1692 /* CLKOUT3 */
1693 RCAR_GP_PIN(6, 31),
1694};
1695static const unsigned int audio_clkout3_b_mux[] = {
1696 AUDIO_CLKOUT3_B_MARK,
1697};
1698
1699/* - EtherAVB --------------------------------------------------------------- */
1700static const unsigned int avb_link_pins[] = {
1701 /* AVB_LINK */
1702 RCAR_GP_PIN(2, 12),
1703};
1704static const unsigned int avb_link_mux[] = {
1705 AVB_LINK_MARK,
1706};
1707static const unsigned int avb_magic_pins[] = {
1708 /* AVB_MAGIC_ */
1709 RCAR_GP_PIN(2, 10),
1710};
1711static const unsigned int avb_magic_mux[] = {
1712 AVB_MAGIC_MARK,
1713};
1714static const unsigned int avb_phy_int_pins[] = {
1715 /* AVB_PHY_INT */
1716 RCAR_GP_PIN(2, 11),
1717};
1718static const unsigned int avb_phy_int_mux[] = {
1719 AVB_PHY_INT_MARK,
1720};
1721static const unsigned int avb_mdio_pins[] = {
1722 /* AVB_MDC, AVB_MDIO */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame^]1723 RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1724};
1725static const unsigned int avb_mdio_mux[] = {
1726 AVB_MDC_MARK, AVB_MDIO_MARK,
1727};
1728static const unsigned int avb_mii_pins[] = {
1729 /*
1730 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1731 * AVB_TD1, AVB_TD2, AVB_TD3,
1732 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1733 * AVB_RD1, AVB_RD2, AVB_RD3,
1734 * AVB_TXCREFCLK
1735 */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame^]1736 PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,
1737 PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,
1738 PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
1739 PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
1740 PIN_AVB_TXCREFCLK,
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1741};
1742static const unsigned int avb_mii_mux[] = {
1743 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1744 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1745 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1746 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1747 AVB_TXCREFCLK_MARK,
1748};
1749static const unsigned int avb_avtp_pps_pins[] = {
1750 /* AVB_AVTP_PPS */
1751 RCAR_GP_PIN(2, 6),
1752};
1753static const unsigned int avb_avtp_pps_mux[] = {
1754 AVB_AVTP_PPS_MARK,
1755};
1756static const unsigned int avb_avtp_match_a_pins[] = {
1757 /* AVB_AVTP_MATCH_A */
1758 RCAR_GP_PIN(2, 13),
1759};
1760static const unsigned int avb_avtp_match_a_mux[] = {
1761 AVB_AVTP_MATCH_A_MARK,
1762};
1763static const unsigned int avb_avtp_capture_a_pins[] = {
1764 /* AVB_AVTP_CAPTURE_A */
1765 RCAR_GP_PIN(2, 14),
1766};
1767static const unsigned int avb_avtp_capture_a_mux[] = {
1768 AVB_AVTP_CAPTURE_A_MARK,
1769};
1770static const unsigned int avb_avtp_match_b_pins[] = {
1771 /* AVB_AVTP_MATCH_B */
1772 RCAR_GP_PIN(1, 8),
1773};
1774static const unsigned int avb_avtp_match_b_mux[] = {
1775 AVB_AVTP_MATCH_B_MARK,
1776};
1777static const unsigned int avb_avtp_capture_b_pins[] = {
1778 /* AVB_AVTP_CAPTURE_B */
1779 RCAR_GP_PIN(1, 11),
1780};
1781static const unsigned int avb_avtp_capture_b_mux[] = {
1782 AVB_AVTP_CAPTURE_B_MARK,
1783};
1784
1785/* - CAN ------------------------------------------------------------------ */
1786static const unsigned int can0_data_a_pins[] = {
1787 /* TX, RX */
1788 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1789};
1790
1791static const unsigned int can0_data_a_mux[] = {
1792 CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1793};
1794
1795static const unsigned int can0_data_b_pins[] = {
1796 /* TX, RX */
1797 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1798};
1799
1800static const unsigned int can0_data_b_mux[] = {
1801 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1802};
1803
1804static const unsigned int can1_data_pins[] = {
1805 /* TX, RX */
1806 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1807};
1808
1809static const unsigned int can1_data_mux[] = {
1810 CAN1_TX_MARK, CAN1_RX_MARK,
1811};
1812
1813/* - CAN Clock -------------------------------------------------------------- */
1814static const unsigned int can_clk_pins[] = {
1815 /* CLK */
1816 RCAR_GP_PIN(1, 25),
1817};
1818
1819static const unsigned int can_clk_mux[] = {
1820 CAN_CLK_MARK,
1821};
1822
1823/* - CAN FD --------------------------------------------------------------- */
1824static const unsigned int canfd0_data_a_pins[] = {
1825 /* TX, RX */
1826 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1827};
1828
1829static const unsigned int canfd0_data_a_mux[] = {
1830 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
1831};
1832
1833static const unsigned int canfd0_data_b_pins[] = {
1834 /* TX, RX */
1835 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1836};
1837
1838static const unsigned int canfd0_data_b_mux[] = {
1839 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
1840};
1841
1842static const unsigned int canfd1_data_pins[] = {
1843 /* TX, RX */
1844 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1845};
1846
1847static const unsigned int canfd1_data_mux[] = {
1848 CANFD1_TX_MARK, CANFD1_RX_MARK,
1849};
1850
Biju Das0a362702020-10-28 10:34:24 +0000[diff] [blame]1851#ifdef CONFIG_PINCTRL_PFC_R8A77965
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1852/* - DRIF0 --------------------------------------------------------------- */
1853static const unsigned int drif0_ctrl_a_pins[] = {
1854 /* CLK, SYNC */
1855 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1856};
1857
1858static const unsigned int drif0_ctrl_a_mux[] = {
1859 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1860};
1861
1862static const unsigned int drif0_data0_a_pins[] = {
1863 /* D0 */
1864 RCAR_GP_PIN(6, 10),
1865};
1866
1867static const unsigned int drif0_data0_a_mux[] = {
1868 RIF0_D0_A_MARK,
1869};
1870
1871static const unsigned int drif0_data1_a_pins[] = {
1872 /* D1 */
1873 RCAR_GP_PIN(6, 7),
1874};
1875
1876static const unsigned int drif0_data1_a_mux[] = {
1877 RIF0_D1_A_MARK,
1878};
1879
1880static const unsigned int drif0_ctrl_b_pins[] = {
1881 /* CLK, SYNC */
1882 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1883};
1884
1885static const unsigned int drif0_ctrl_b_mux[] = {
1886 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1887};
1888
1889static const unsigned int drif0_data0_b_pins[] = {
1890 /* D0 */
1891 RCAR_GP_PIN(5, 1),
1892};
1893
1894static const unsigned int drif0_data0_b_mux[] = {
1895 RIF0_D0_B_MARK,
1896};
1897
1898static const unsigned int drif0_data1_b_pins[] = {
1899 /* D1 */
1900 RCAR_GP_PIN(5, 2),
1901};
1902
1903static const unsigned int drif0_data1_b_mux[] = {
1904 RIF0_D1_B_MARK,
1905};
1906
1907static const unsigned int drif0_ctrl_c_pins[] = {
1908 /* CLK, SYNC */
1909 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1910};
1911
1912static const unsigned int drif0_ctrl_c_mux[] = {
1913 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1914};
1915
1916static const unsigned int drif0_data0_c_pins[] = {
1917 /* D0 */
1918 RCAR_GP_PIN(5, 13),
1919};
1920
1921static const unsigned int drif0_data0_c_mux[] = {
1922 RIF0_D0_C_MARK,
1923};
1924
1925static const unsigned int drif0_data1_c_pins[] = {
1926 /* D1 */
1927 RCAR_GP_PIN(5, 14),
1928};
1929
1930static const unsigned int drif0_data1_c_mux[] = {
1931 RIF0_D1_C_MARK,
1932};
1933
1934/* - DRIF1 --------------------------------------------------------------- */
1935static const unsigned int drif1_ctrl_a_pins[] = {
1936 /* CLK, SYNC */
1937 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1938};
1939
1940static const unsigned int drif1_ctrl_a_mux[] = {
1941 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1942};
1943
1944static const unsigned int drif1_data0_a_pins[] = {
1945 /* D0 */
1946 RCAR_GP_PIN(6, 19),
1947};
1948
1949static const unsigned int drif1_data0_a_mux[] = {
1950 RIF1_D0_A_MARK,
1951};
1952
1953static const unsigned int drif1_data1_a_pins[] = {
1954 /* D1 */
1955 RCAR_GP_PIN(6, 20),
1956};
1957
1958static const unsigned int drif1_data1_a_mux[] = {
1959 RIF1_D1_A_MARK,
1960};
1961
1962static const unsigned int drif1_ctrl_b_pins[] = {
1963 /* CLK, SYNC */
1964 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1965};
1966
1967static const unsigned int drif1_ctrl_b_mux[] = {
1968 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1969};
1970
1971static const unsigned int drif1_data0_b_pins[] = {
1972 /* D0 */
1973 RCAR_GP_PIN(5, 7),
1974};
1975
1976static const unsigned int drif1_data0_b_mux[] = {
1977 RIF1_D0_B_MARK,
1978};
1979
1980static const unsigned int drif1_data1_b_pins[] = {
1981 /* D1 */
1982 RCAR_GP_PIN(5, 8),
1983};
1984
1985static const unsigned int drif1_data1_b_mux[] = {
1986 RIF1_D1_B_MARK,
1987};
1988
1989static const unsigned int drif1_ctrl_c_pins[] = {
1990 /* CLK, SYNC */
1991 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1992};
1993
1994static const unsigned int drif1_ctrl_c_mux[] = {
1995 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1996};
1997
1998static const unsigned int drif1_data0_c_pins[] = {
1999 /* D0 */
2000 RCAR_GP_PIN(5, 6),
2001};
2002
2003static const unsigned int drif1_data0_c_mux[] = {
2004 RIF1_D0_C_MARK,
2005};
2006
2007static const unsigned int drif1_data1_c_pins[] = {
2008 /* D1 */
2009 RCAR_GP_PIN(5, 10),
2010};
2011
2012static const unsigned int drif1_data1_c_mux[] = {
2013 RIF1_D1_C_MARK,
2014};
2015
2016/* - DRIF2 --------------------------------------------------------------- */
2017static const unsigned int drif2_ctrl_a_pins[] = {
2018 /* CLK, SYNC */
2019 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2020};
2021
2022static const unsigned int drif2_ctrl_a_mux[] = {
2023 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
2024};
2025
2026static const unsigned int drif2_data0_a_pins[] = {
2027 /* D0 */
2028 RCAR_GP_PIN(6, 7),
2029};
2030
2031static const unsigned int drif2_data0_a_mux[] = {
2032 RIF2_D0_A_MARK,
2033};
2034
2035static const unsigned int drif2_data1_a_pins[] = {
2036 /* D1 */
2037 RCAR_GP_PIN(6, 10),
2038};
2039
2040static const unsigned int drif2_data1_a_mux[] = {
2041 RIF2_D1_A_MARK,
2042};
2043
2044static const unsigned int drif2_ctrl_b_pins[] = {
2045 /* CLK, SYNC */
2046 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
2047};
2048
2049static const unsigned int drif2_ctrl_b_mux[] = {
2050 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
2051};
2052
2053static const unsigned int drif2_data0_b_pins[] = {
2054 /* D0 */
2055 RCAR_GP_PIN(6, 30),
2056};
2057
2058static const unsigned int drif2_data0_b_mux[] = {
2059 RIF2_D0_B_MARK,
2060};
2061
2062static const unsigned int drif2_data1_b_pins[] = {
2063 /* D1 */
2064 RCAR_GP_PIN(6, 31),
2065};
2066
2067static const unsigned int drif2_data1_b_mux[] = {
2068 RIF2_D1_B_MARK,
2069};
2070
2071/* - DRIF3 --------------------------------------------------------------- */
2072static const unsigned int drif3_ctrl_a_pins[] = {
2073 /* CLK, SYNC */
2074 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2075};
2076
2077static const unsigned int drif3_ctrl_a_mux[] = {
2078 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
2079};
2080
2081static const unsigned int drif3_data0_a_pins[] = {
2082 /* D0 */
2083 RCAR_GP_PIN(6, 19),
2084};
2085
2086static const unsigned int drif3_data0_a_mux[] = {
2087 RIF3_D0_A_MARK,
2088};
2089
2090static const unsigned int drif3_data1_a_pins[] = {
2091 /* D1 */
2092 RCAR_GP_PIN(6, 20),
2093};
2094
2095static const unsigned int drif3_data1_a_mux[] = {
2096 RIF3_D1_A_MARK,
2097};
2098
2099static const unsigned int drif3_ctrl_b_pins[] = {
2100 /* CLK, SYNC */
2101 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2102};
2103
2104static const unsigned int drif3_ctrl_b_mux[] = {
2105 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
2106};
2107
2108static const unsigned int drif3_data0_b_pins[] = {
2109 /* D0 */
2110 RCAR_GP_PIN(6, 28),
2111};
2112
2113static const unsigned int drif3_data0_b_mux[] = {
2114 RIF3_D0_B_MARK,
2115};
2116
2117static const unsigned int drif3_data1_b_pins[] = {
2118 /* D1 */
2119 RCAR_GP_PIN(6, 29),
2120};
2121
2122static const unsigned int drif3_data1_b_mux[] = {
2123 RIF3_D1_B_MARK,
2124};
Biju Das0a362702020-10-28 10:34:24 +0000[diff] [blame]2125#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]2126
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2127/* - DU --------------------------------------------------------------------- */
2128static const unsigned int du_rgb666_pins[] = {
2129 /* R[7:2], G[7:2], B[7:2] */
2130 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2131 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2132 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2133 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2134 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2135 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2136};
2137
2138static const unsigned int du_rgb666_mux[] = {
2139 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2140 DU_DR3_MARK, DU_DR2_MARK,
2141 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2142 DU_DG3_MARK, DU_DG2_MARK,
2143 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2144 DU_DB3_MARK, DU_DB2_MARK,
2145};
2146
2147static const unsigned int du_rgb888_pins[] = {
2148 /* R[7:0], G[7:0], B[7:0] */
2149 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2150 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2151 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
2152 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2153 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2154 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2155 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2156 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2157 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2158};
2159
2160static const unsigned int du_rgb888_mux[] = {
2161 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2162 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2163 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2164 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2165 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2166 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2167};
2168
2169static const unsigned int du_clk_out_0_pins[] = {
2170 /* CLKOUT */
2171 RCAR_GP_PIN(1, 27),
2172};
2173
2174static const unsigned int du_clk_out_0_mux[] = {
2175 DU_DOTCLKOUT0_MARK
2176};
2177
2178static const unsigned int du_clk_out_1_pins[] = {
2179 /* CLKOUT */
2180 RCAR_GP_PIN(2, 3),
2181};
2182
2183static const unsigned int du_clk_out_1_mux[] = {
2184 DU_DOTCLKOUT1_MARK
2185};
2186
2187static const unsigned int du_sync_pins[] = {
2188 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2189 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2190};
2191
2192static const unsigned int du_sync_mux[] = {
2193 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2194};
2195
2196static const unsigned int du_oddf_pins[] = {
2197 /* EXDISP/EXODDF/EXCDE */
2198 RCAR_GP_PIN(2, 2),
2199};
2200
2201static const unsigned int du_oddf_mux[] = {
2202 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2203};
2204
2205static const unsigned int du_cde_pins[] = {
2206 /* CDE */
2207 RCAR_GP_PIN(2, 0),
2208};
2209
2210static const unsigned int du_cde_mux[] = {
2211 DU_CDE_MARK,
2212};
2213
2214static const unsigned int du_disp_pins[] = {
2215 /* DISP */
2216 RCAR_GP_PIN(2, 1),
2217};
2218
2219static const unsigned int du_disp_mux[] = {
2220 DU_DISP_MARK,
2221};
2222
2223/* - HSCIF0 ----------------------------------------------------------------- */
2224static const unsigned int hscif0_data_pins[] = {
2225 /* RX, TX */
2226 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2227};
2228
2229static const unsigned int hscif0_data_mux[] = {
2230 HRX0_MARK, HTX0_MARK,
2231};
2232
2233static const unsigned int hscif0_clk_pins[] = {
2234 /* SCK */
2235 RCAR_GP_PIN(5, 12),
2236};
2237
2238static const unsigned int hscif0_clk_mux[] = {
2239 HSCK0_MARK,
2240};
2241
2242static const unsigned int hscif0_ctrl_pins[] = {
2243 /* RTS, CTS */
2244 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2245};
2246
2247static const unsigned int hscif0_ctrl_mux[] = {
2248 HRTS0_N_MARK, HCTS0_N_MARK,
2249};
2250
2251/* - HSCIF1 ----------------------------------------------------------------- */
2252static const unsigned int hscif1_data_a_pins[] = {
2253 /* RX, TX */
2254 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2255};
2256
2257static const unsigned int hscif1_data_a_mux[] = {
2258 HRX1_A_MARK, HTX1_A_MARK,
2259};
2260
2261static const unsigned int hscif1_clk_a_pins[] = {
2262 /* SCK */
2263 RCAR_GP_PIN(6, 21),
2264};
2265
2266static const unsigned int hscif1_clk_a_mux[] = {
2267 HSCK1_A_MARK,
2268};
2269
2270static const unsigned int hscif1_ctrl_a_pins[] = {
2271 /* RTS, CTS */
2272 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2273};
2274
2275static const unsigned int hscif1_ctrl_a_mux[] = {
2276 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2277};
2278
2279static const unsigned int hscif1_data_b_pins[] = {
2280 /* RX, TX */
2281 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2282};
2283
2284static const unsigned int hscif1_data_b_mux[] = {
2285 HRX1_B_MARK, HTX1_B_MARK,
2286};
2287
2288static const unsigned int hscif1_clk_b_pins[] = {
2289 /* SCK */
2290 RCAR_GP_PIN(5, 0),
2291};
2292
2293static const unsigned int hscif1_clk_b_mux[] = {
2294 HSCK1_B_MARK,
2295};
2296
2297static const unsigned int hscif1_ctrl_b_pins[] = {
2298 /* RTS, CTS */
2299 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2300};
2301
2302static const unsigned int hscif1_ctrl_b_mux[] = {
2303 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2304};
2305
2306/* - HSCIF2 ----------------------------------------------------------------- */
2307static const unsigned int hscif2_data_a_pins[] = {
2308 /* RX, TX */
2309 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2310};
2311
2312static const unsigned int hscif2_data_a_mux[] = {
2313 HRX2_A_MARK, HTX2_A_MARK,
2314};
2315
2316static const unsigned int hscif2_clk_a_pins[] = {
2317 /* SCK */
2318 RCAR_GP_PIN(6, 10),
2319};
2320
2321static const unsigned int hscif2_clk_a_mux[] = {
2322 HSCK2_A_MARK,
2323};
2324
2325static const unsigned int hscif2_ctrl_a_pins[] = {
2326 /* RTS, CTS */
2327 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2328};
2329
2330static const unsigned int hscif2_ctrl_a_mux[] = {
2331 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2332};
2333
2334static const unsigned int hscif2_data_b_pins[] = {
2335 /* RX, TX */
2336 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2337};
2338
2339static const unsigned int hscif2_data_b_mux[] = {
2340 HRX2_B_MARK, HTX2_B_MARK,
2341};
2342
2343static const unsigned int hscif2_clk_b_pins[] = {
2344 /* SCK */
2345 RCAR_GP_PIN(6, 21),
2346};
2347
2348static const unsigned int hscif2_clk_b_mux[] = {
2349 HSCK2_B_MARK,
2350};
2351
2352static const unsigned int hscif2_ctrl_b_pins[] = {
2353 /* RTS, CTS */
2354 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2355};
2356
2357static const unsigned int hscif2_ctrl_b_mux[] = {
2358 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2359};
2360
2361static const unsigned int hscif2_data_c_pins[] = {
2362 /* RX, TX */
2363 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2364};
2365
2366static const unsigned int hscif2_data_c_mux[] = {
2367 HRX2_C_MARK, HTX2_C_MARK,
2368};
2369
2370static const unsigned int hscif2_clk_c_pins[] = {
2371 /* SCK */
2372 RCAR_GP_PIN(6, 24),
2373};
2374
2375static const unsigned int hscif2_clk_c_mux[] = {
2376 HSCK2_C_MARK,
2377};
2378
2379static const unsigned int hscif2_ctrl_c_pins[] = {
2380 /* RTS, CTS */
2381 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2382};
2383
2384static const unsigned int hscif2_ctrl_c_mux[] = {
2385 HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2386};
2387
2388/* - HSCIF3 ----------------------------------------------------------------- */
2389static const unsigned int hscif3_data_a_pins[] = {
2390 /* RX, TX */
2391 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2392};
2393
2394static const unsigned int hscif3_data_a_mux[] = {
2395 HRX3_A_MARK, HTX3_A_MARK,
2396};
2397
2398static const unsigned int hscif3_clk_pins[] = {
2399 /* SCK */
2400 RCAR_GP_PIN(1, 22),
2401};
2402
2403static const unsigned int hscif3_clk_mux[] = {
2404 HSCK3_MARK,
2405};
2406
2407static const unsigned int hscif3_ctrl_pins[] = {
2408 /* RTS, CTS */
2409 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2410};
2411
2412static const unsigned int hscif3_ctrl_mux[] = {
2413 HRTS3_N_MARK, HCTS3_N_MARK,
2414};
2415
2416static const unsigned int hscif3_data_b_pins[] = {
2417 /* RX, TX */
2418 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2419};
2420
2421static const unsigned int hscif3_data_b_mux[] = {
2422 HRX3_B_MARK, HTX3_B_MARK,
2423};
2424
2425static const unsigned int hscif3_data_c_pins[] = {
2426 /* RX, TX */
2427 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2428};
2429
2430static const unsigned int hscif3_data_c_mux[] = {
2431 HRX3_C_MARK, HTX3_C_MARK,
2432};
2433
2434static const unsigned int hscif3_data_d_pins[] = {
2435 /* RX, TX */
2436 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2437};
2438
2439static const unsigned int hscif3_data_d_mux[] = {
2440 HRX3_D_MARK, HTX3_D_MARK,
2441};
2442
2443/* - HSCIF4 ----------------------------------------------------------------- */
2444static const unsigned int hscif4_data_a_pins[] = {
2445 /* RX, TX */
2446 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2447};
2448
2449static const unsigned int hscif4_data_a_mux[] = {
2450 HRX4_A_MARK, HTX4_A_MARK,
2451};
2452
2453static const unsigned int hscif4_clk_pins[] = {
2454 /* SCK */
2455 RCAR_GP_PIN(1, 11),
2456};
2457
2458static const unsigned int hscif4_clk_mux[] = {
2459 HSCK4_MARK,
2460};
2461
2462static const unsigned int hscif4_ctrl_pins[] = {
2463 /* RTS, CTS */
2464 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2465};
2466
2467static const unsigned int hscif4_ctrl_mux[] = {
2468 HRTS4_N_MARK, HCTS4_N_MARK,
2469};
2470
2471static const unsigned int hscif4_data_b_pins[] = {
2472 /* RX, TX */
2473 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2474};
2475
2476static const unsigned int hscif4_data_b_mux[] = {
2477 HRX4_B_MARK, HTX4_B_MARK,
2478};
2479
2480/* - I2C -------------------------------------------------------------------- */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2481static const unsigned int i2c0_pins[] = {
2482 /* SCL, SDA */
2483 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2484};
2485
2486static const unsigned int i2c0_mux[] = {
2487 SCL0_MARK, SDA0_MARK,
2488};
2489
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2490static const unsigned int i2c1_a_pins[] = {
2491 /* SDA, SCL */
2492 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2493};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2494
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2495static const unsigned int i2c1_a_mux[] = {
2496 SDA1_A_MARK, SCL1_A_MARK,
2497};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2498
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2499static const unsigned int i2c1_b_pins[] = {
2500 /* SDA, SCL */
2501 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2502};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2503
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2504static const unsigned int i2c1_b_mux[] = {
2505 SDA1_B_MARK, SCL1_B_MARK,
2506};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2507
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2508static const unsigned int i2c2_a_pins[] = {
2509 /* SDA, SCL */
2510 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2511};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2512
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2513static const unsigned int i2c2_a_mux[] = {
2514 SDA2_A_MARK, SCL2_A_MARK,
2515};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2516
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2517static const unsigned int i2c2_b_pins[] = {
2518 /* SDA, SCL */
2519 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2520};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2521
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2522static const unsigned int i2c2_b_mux[] = {
2523 SDA2_B_MARK, SCL2_B_MARK,
2524};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2525
2526static const unsigned int i2c3_pins[] = {
2527 /* SCL, SDA */
2528 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2529};
2530
2531static const unsigned int i2c3_mux[] = {
2532 SCL3_MARK, SDA3_MARK,
2533};
2534
2535static const unsigned int i2c5_pins[] = {
2536 /* SCL, SDA */
2537 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
2538};
2539
2540static const unsigned int i2c5_mux[] = {
2541 SCL5_MARK, SDA5_MARK,
2542};
2543
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2544static const unsigned int i2c6_a_pins[] = {
2545 /* SDA, SCL */
2546 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2547};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2548
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2549static const unsigned int i2c6_a_mux[] = {
2550 SDA6_A_MARK, SCL6_A_MARK,
2551};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2552
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2553static const unsigned int i2c6_b_pins[] = {
2554 /* SDA, SCL */
2555 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2556};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2557
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2558static const unsigned int i2c6_b_mux[] = {
2559 SDA6_B_MARK, SCL6_B_MARK,
2560};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2561
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2562static const unsigned int i2c6_c_pins[] = {
2563 /* SDA, SCL */
2564 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2565};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2566
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2567static const unsigned int i2c6_c_mux[] = {
2568 SDA6_C_MARK, SCL6_C_MARK,
2569};
2570
2571/* - INTC-EX ---------------------------------------------------------------- */
2572static const unsigned int intc_ex_irq0_pins[] = {
2573 /* IRQ0 */
2574 RCAR_GP_PIN(2, 0),
2575};
2576static const unsigned int intc_ex_irq0_mux[] = {
2577 IRQ0_MARK,
2578};
2579static const unsigned int intc_ex_irq1_pins[] = {
2580 /* IRQ1 */
2581 RCAR_GP_PIN(2, 1),
2582};
2583static const unsigned int intc_ex_irq1_mux[] = {
2584 IRQ1_MARK,
2585};
2586static const unsigned int intc_ex_irq2_pins[] = {
2587 /* IRQ2 */
2588 RCAR_GP_PIN(2, 2),
2589};
2590static const unsigned int intc_ex_irq2_mux[] = {
2591 IRQ2_MARK,
2592};
2593static const unsigned int intc_ex_irq3_pins[] = {
2594 /* IRQ3 */
2595 RCAR_GP_PIN(2, 3),
2596};
2597static const unsigned int intc_ex_irq3_mux[] = {
2598 IRQ3_MARK,
2599};
2600static const unsigned int intc_ex_irq4_pins[] = {
2601 /* IRQ4 */
2602 RCAR_GP_PIN(2, 4),
2603};
2604static const unsigned int intc_ex_irq4_mux[] = {
2605 IRQ4_MARK,
2606};
2607static const unsigned int intc_ex_irq5_pins[] = {
2608 /* IRQ5 */
2609 RCAR_GP_PIN(2, 5),
2610};
2611static const unsigned int intc_ex_irq5_mux[] = {
2612 IRQ5_MARK,
2613};
2614
2615/* - MSIOF0 ----------------------------------------------------------------- */
2616static const unsigned int msiof0_clk_pins[] = {
2617 /* SCK */
2618 RCAR_GP_PIN(5, 17),
2619};
2620static const unsigned int msiof0_clk_mux[] = {
2621 MSIOF0_SCK_MARK,
2622};
2623static const unsigned int msiof0_sync_pins[] = {
2624 /* SYNC */
2625 RCAR_GP_PIN(5, 18),
2626};
2627static const unsigned int msiof0_sync_mux[] = {
2628 MSIOF0_SYNC_MARK,
2629};
2630static const unsigned int msiof0_ss1_pins[] = {
2631 /* SS1 */
2632 RCAR_GP_PIN(5, 19),
2633};
2634static const unsigned int msiof0_ss1_mux[] = {
2635 MSIOF0_SS1_MARK,
2636};
2637static const unsigned int msiof0_ss2_pins[] = {
2638 /* SS2 */
2639 RCAR_GP_PIN(5, 21),
2640};
2641static const unsigned int msiof0_ss2_mux[] = {
2642 MSIOF0_SS2_MARK,
2643};
2644static const unsigned int msiof0_txd_pins[] = {
2645 /* TXD */
2646 RCAR_GP_PIN(5, 20),
2647};
2648static const unsigned int msiof0_txd_mux[] = {
2649 MSIOF0_TXD_MARK,
2650};
2651static const unsigned int msiof0_rxd_pins[] = {
2652 /* RXD */
2653 RCAR_GP_PIN(5, 22),
2654};
2655static const unsigned int msiof0_rxd_mux[] = {
2656 MSIOF0_RXD_MARK,
2657};
2658/* - MSIOF1 ----------------------------------------------------------------- */
2659static const unsigned int msiof1_clk_a_pins[] = {
2660 /* SCK */
2661 RCAR_GP_PIN(6, 8),
2662};
2663static const unsigned int msiof1_clk_a_mux[] = {
2664 MSIOF1_SCK_A_MARK,
2665};
2666static const unsigned int msiof1_sync_a_pins[] = {
2667 /* SYNC */
2668 RCAR_GP_PIN(6, 9),
2669};
2670static const unsigned int msiof1_sync_a_mux[] = {
2671 MSIOF1_SYNC_A_MARK,
2672};
2673static const unsigned int msiof1_ss1_a_pins[] = {
2674 /* SS1 */
2675 RCAR_GP_PIN(6, 5),
2676};
2677static const unsigned int msiof1_ss1_a_mux[] = {
2678 MSIOF1_SS1_A_MARK,
2679};
2680static const unsigned int msiof1_ss2_a_pins[] = {
2681 /* SS2 */
2682 RCAR_GP_PIN(6, 6),
2683};
2684static const unsigned int msiof1_ss2_a_mux[] = {
2685 MSIOF1_SS2_A_MARK,
2686};
2687static const unsigned int msiof1_txd_a_pins[] = {
2688 /* TXD */
2689 RCAR_GP_PIN(6, 7),
2690};
2691static const unsigned int msiof1_txd_a_mux[] = {
2692 MSIOF1_TXD_A_MARK,
2693};
2694static const unsigned int msiof1_rxd_a_pins[] = {
2695 /* RXD */
2696 RCAR_GP_PIN(6, 10),
2697};
2698static const unsigned int msiof1_rxd_a_mux[] = {
2699 MSIOF1_RXD_A_MARK,
2700};
2701static const unsigned int msiof1_clk_b_pins[] = {
2702 /* SCK */
2703 RCAR_GP_PIN(5, 9),
2704};
2705static const unsigned int msiof1_clk_b_mux[] = {
2706 MSIOF1_SCK_B_MARK,
2707};
2708static const unsigned int msiof1_sync_b_pins[] = {
2709 /* SYNC */
2710 RCAR_GP_PIN(5, 3),
2711};
2712static const unsigned int msiof1_sync_b_mux[] = {
2713 MSIOF1_SYNC_B_MARK,
2714};
2715static const unsigned int msiof1_ss1_b_pins[] = {
2716 /* SS1 */
2717 RCAR_GP_PIN(5, 4),
2718};
2719static const unsigned int msiof1_ss1_b_mux[] = {
2720 MSIOF1_SS1_B_MARK,
2721};
2722static const unsigned int msiof1_ss2_b_pins[] = {
2723 /* SS2 */
2724 RCAR_GP_PIN(5, 0),
2725};
2726static const unsigned int msiof1_ss2_b_mux[] = {
2727 MSIOF1_SS2_B_MARK,
2728};
2729static const unsigned int msiof1_txd_b_pins[] = {
2730 /* TXD */
2731 RCAR_GP_PIN(5, 8),
2732};
2733static const unsigned int msiof1_txd_b_mux[] = {
2734 MSIOF1_TXD_B_MARK,
2735};
2736static const unsigned int msiof1_rxd_b_pins[] = {
2737 /* RXD */
2738 RCAR_GP_PIN(5, 7),
2739};
2740static const unsigned int msiof1_rxd_b_mux[] = {
2741 MSIOF1_RXD_B_MARK,
2742};
2743static const unsigned int msiof1_clk_c_pins[] = {
2744 /* SCK */
2745 RCAR_GP_PIN(6, 17),
2746};
2747static const unsigned int msiof1_clk_c_mux[] = {
2748 MSIOF1_SCK_C_MARK,
2749};
2750static const unsigned int msiof1_sync_c_pins[] = {
2751 /* SYNC */
2752 RCAR_GP_PIN(6, 18),
2753};
2754static const unsigned int msiof1_sync_c_mux[] = {
2755 MSIOF1_SYNC_C_MARK,
2756};
2757static const unsigned int msiof1_ss1_c_pins[] = {
2758 /* SS1 */
2759 RCAR_GP_PIN(6, 21),
2760};
2761static const unsigned int msiof1_ss1_c_mux[] = {
2762 MSIOF1_SS1_C_MARK,
2763};
2764static const unsigned int msiof1_ss2_c_pins[] = {
2765 /* SS2 */
2766 RCAR_GP_PIN(6, 27),
2767};
2768static const unsigned int msiof1_ss2_c_mux[] = {
2769 MSIOF1_SS2_C_MARK,
2770};
2771static const unsigned int msiof1_txd_c_pins[] = {
2772 /* TXD */
2773 RCAR_GP_PIN(6, 20),
2774};
2775static const unsigned int msiof1_txd_c_mux[] = {
2776 MSIOF1_TXD_C_MARK,
2777};
2778static const unsigned int msiof1_rxd_c_pins[] = {
2779 /* RXD */
2780 RCAR_GP_PIN(6, 19),
2781};
2782static const unsigned int msiof1_rxd_c_mux[] = {
2783 MSIOF1_RXD_C_MARK,
2784};
2785static const unsigned int msiof1_clk_d_pins[] = {
2786 /* SCK */
2787 RCAR_GP_PIN(5, 12),
2788};
2789static const unsigned int msiof1_clk_d_mux[] = {
2790 MSIOF1_SCK_D_MARK,
2791};
2792static const unsigned int msiof1_sync_d_pins[] = {
2793 /* SYNC */
2794 RCAR_GP_PIN(5, 15),
2795};
2796static const unsigned int msiof1_sync_d_mux[] = {
2797 MSIOF1_SYNC_D_MARK,
2798};
2799static const unsigned int msiof1_ss1_d_pins[] = {
2800 /* SS1 */
2801 RCAR_GP_PIN(5, 16),
2802};
2803static const unsigned int msiof1_ss1_d_mux[] = {
2804 MSIOF1_SS1_D_MARK,
2805};
2806static const unsigned int msiof1_ss2_d_pins[] = {
2807 /* SS2 */
2808 RCAR_GP_PIN(5, 21),
2809};
2810static const unsigned int msiof1_ss2_d_mux[] = {
2811 MSIOF1_SS2_D_MARK,
2812};
2813static const unsigned int msiof1_txd_d_pins[] = {
2814 /* TXD */
2815 RCAR_GP_PIN(5, 14),
2816};
2817static const unsigned int msiof1_txd_d_mux[] = {
2818 MSIOF1_TXD_D_MARK,
2819};
2820static const unsigned int msiof1_rxd_d_pins[] = {
2821 /* RXD */
2822 RCAR_GP_PIN(5, 13),
2823};
2824static const unsigned int msiof1_rxd_d_mux[] = {
2825 MSIOF1_RXD_D_MARK,
2826};
2827static const unsigned int msiof1_clk_e_pins[] = {
2828 /* SCK */
2829 RCAR_GP_PIN(3, 0),
2830};
2831static const unsigned int msiof1_clk_e_mux[] = {
2832 MSIOF1_SCK_E_MARK,
2833};
2834static const unsigned int msiof1_sync_e_pins[] = {
2835 /* SYNC */
2836 RCAR_GP_PIN(3, 1),
2837};
2838static const unsigned int msiof1_sync_e_mux[] = {
2839 MSIOF1_SYNC_E_MARK,
2840};
2841static const unsigned int msiof1_ss1_e_pins[] = {
2842 /* SS1 */
2843 RCAR_GP_PIN(3, 4),
2844};
2845static const unsigned int msiof1_ss1_e_mux[] = {
2846 MSIOF1_SS1_E_MARK,
2847};
2848static const unsigned int msiof1_ss2_e_pins[] = {
2849 /* SS2 */
2850 RCAR_GP_PIN(3, 5),
2851};
2852static const unsigned int msiof1_ss2_e_mux[] = {
2853 MSIOF1_SS2_E_MARK,
2854};
2855static const unsigned int msiof1_txd_e_pins[] = {
2856 /* TXD */
2857 RCAR_GP_PIN(3, 3),
2858};
2859static const unsigned int msiof1_txd_e_mux[] = {
2860 MSIOF1_TXD_E_MARK,
2861};
2862static const unsigned int msiof1_rxd_e_pins[] = {
2863 /* RXD */
2864 RCAR_GP_PIN(3, 2),
2865};
2866static const unsigned int msiof1_rxd_e_mux[] = {
2867 MSIOF1_RXD_E_MARK,
2868};
2869static const unsigned int msiof1_clk_f_pins[] = {
2870 /* SCK */
2871 RCAR_GP_PIN(5, 23),
2872};
2873static const unsigned int msiof1_clk_f_mux[] = {
2874 MSIOF1_SCK_F_MARK,
2875};
2876static const unsigned int msiof1_sync_f_pins[] = {
2877 /* SYNC */
2878 RCAR_GP_PIN(5, 24),
2879};
2880static const unsigned int msiof1_sync_f_mux[] = {
2881 MSIOF1_SYNC_F_MARK,
2882};
2883static const unsigned int msiof1_ss1_f_pins[] = {
2884 /* SS1 */
2885 RCAR_GP_PIN(6, 1),
2886};
2887static const unsigned int msiof1_ss1_f_mux[] = {
2888 MSIOF1_SS1_F_MARK,
2889};
2890static const unsigned int msiof1_ss2_f_pins[] = {
2891 /* SS2 */
2892 RCAR_GP_PIN(6, 2),
2893};
2894static const unsigned int msiof1_ss2_f_mux[] = {
2895 MSIOF1_SS2_F_MARK,
2896};
2897static const unsigned int msiof1_txd_f_pins[] = {
2898 /* TXD */
2899 RCAR_GP_PIN(6, 0),
2900};
2901static const unsigned int msiof1_txd_f_mux[] = {
2902 MSIOF1_TXD_F_MARK,
2903};
2904static const unsigned int msiof1_rxd_f_pins[] = {
2905 /* RXD */
2906 RCAR_GP_PIN(5, 25),
2907};
2908static const unsigned int msiof1_rxd_f_mux[] = {
2909 MSIOF1_RXD_F_MARK,
2910};
2911static const unsigned int msiof1_clk_g_pins[] = {
2912 /* SCK */
2913 RCAR_GP_PIN(3, 6),
2914};
2915static const unsigned int msiof1_clk_g_mux[] = {
2916 MSIOF1_SCK_G_MARK,
2917};
2918static const unsigned int msiof1_sync_g_pins[] = {
2919 /* SYNC */
2920 RCAR_GP_PIN(3, 7),
2921};
2922static const unsigned int msiof1_sync_g_mux[] = {
2923 MSIOF1_SYNC_G_MARK,
2924};
2925static const unsigned int msiof1_ss1_g_pins[] = {
2926 /* SS1 */
2927 RCAR_GP_PIN(3, 10),
2928};
2929static const unsigned int msiof1_ss1_g_mux[] = {
2930 MSIOF1_SS1_G_MARK,
2931};
2932static const unsigned int msiof1_ss2_g_pins[] = {
2933 /* SS2 */
2934 RCAR_GP_PIN(3, 11),
2935};
2936static const unsigned int msiof1_ss2_g_mux[] = {
2937 MSIOF1_SS2_G_MARK,
2938};
2939static const unsigned int msiof1_txd_g_pins[] = {
2940 /* TXD */
2941 RCAR_GP_PIN(3, 9),
2942};
2943static const unsigned int msiof1_txd_g_mux[] = {
2944 MSIOF1_TXD_G_MARK,
2945};
2946static const unsigned int msiof1_rxd_g_pins[] = {
2947 /* RXD */
2948 RCAR_GP_PIN(3, 8),
2949};
2950static const unsigned int msiof1_rxd_g_mux[] = {
2951 MSIOF1_RXD_G_MARK,
2952};
2953/* - MSIOF2 ----------------------------------------------------------------- */
2954static const unsigned int msiof2_clk_a_pins[] = {
2955 /* SCK */
2956 RCAR_GP_PIN(1, 9),
2957};
2958static const unsigned int msiof2_clk_a_mux[] = {
2959 MSIOF2_SCK_A_MARK,
2960};
2961static const unsigned int msiof2_sync_a_pins[] = {
2962 /* SYNC */
2963 RCAR_GP_PIN(1, 8),
2964};
2965static const unsigned int msiof2_sync_a_mux[] = {
2966 MSIOF2_SYNC_A_MARK,
2967};
2968static const unsigned int msiof2_ss1_a_pins[] = {
2969 /* SS1 */
2970 RCAR_GP_PIN(1, 6),
2971};
2972static const unsigned int msiof2_ss1_a_mux[] = {
2973 MSIOF2_SS1_A_MARK,
2974};
2975static const unsigned int msiof2_ss2_a_pins[] = {
2976 /* SS2 */
2977 RCAR_GP_PIN(1, 7),
2978};
2979static const unsigned int msiof2_ss2_a_mux[] = {
2980 MSIOF2_SS2_A_MARK,
2981};
2982static const unsigned int msiof2_txd_a_pins[] = {
2983 /* TXD */
2984 RCAR_GP_PIN(1, 11),
2985};
2986static const unsigned int msiof2_txd_a_mux[] = {
2987 MSIOF2_TXD_A_MARK,
2988};
2989static const unsigned int msiof2_rxd_a_pins[] = {
2990 /* RXD */
2991 RCAR_GP_PIN(1, 10),
2992};
2993static const unsigned int msiof2_rxd_a_mux[] = {
2994 MSIOF2_RXD_A_MARK,
2995};
2996static const unsigned int msiof2_clk_b_pins[] = {
2997 /* SCK */
2998 RCAR_GP_PIN(0, 4),
2999};
3000static const unsigned int msiof2_clk_b_mux[] = {
3001 MSIOF2_SCK_B_MARK,
3002};
3003static const unsigned int msiof2_sync_b_pins[] = {
3004 /* SYNC */
3005 RCAR_GP_PIN(0, 5),
3006};
3007static const unsigned int msiof2_sync_b_mux[] = {
3008 MSIOF2_SYNC_B_MARK,
3009};
3010static const unsigned int msiof2_ss1_b_pins[] = {
3011 /* SS1 */
3012 RCAR_GP_PIN(0, 0),
3013};
3014static const unsigned int msiof2_ss1_b_mux[] = {
3015 MSIOF2_SS1_B_MARK,
3016};
3017static const unsigned int msiof2_ss2_b_pins[] = {
3018 /* SS2 */
3019 RCAR_GP_PIN(0, 1),
3020};
3021static const unsigned int msiof2_ss2_b_mux[] = {
3022 MSIOF2_SS2_B_MARK,
3023};
3024static const unsigned int msiof2_txd_b_pins[] = {
3025 /* TXD */
3026 RCAR_GP_PIN(0, 7),
3027};
3028static const unsigned int msiof2_txd_b_mux[] = {
3029 MSIOF2_TXD_B_MARK,
3030};
3031static const unsigned int msiof2_rxd_b_pins[] = {
3032 /* RXD */
3033 RCAR_GP_PIN(0, 6),
3034};
3035static const unsigned int msiof2_rxd_b_mux[] = {
3036 MSIOF2_RXD_B_MARK,
3037};
3038static const unsigned int msiof2_clk_c_pins[] = {
3039 /* SCK */
3040 RCAR_GP_PIN(2, 12),
3041};
3042static const unsigned int msiof2_clk_c_mux[] = {
3043 MSIOF2_SCK_C_MARK,
3044};
3045static const unsigned int msiof2_sync_c_pins[] = {
3046 /* SYNC */
3047 RCAR_GP_PIN(2, 11),
3048};
3049static const unsigned int msiof2_sync_c_mux[] = {
3050 MSIOF2_SYNC_C_MARK,
3051};
3052static const unsigned int msiof2_ss1_c_pins[] = {
3053 /* SS1 */
3054 RCAR_GP_PIN(2, 10),
3055};
3056static const unsigned int msiof2_ss1_c_mux[] = {
3057 MSIOF2_SS1_C_MARK,
3058};
3059static const unsigned int msiof2_ss2_c_pins[] = {
3060 /* SS2 */
3061 RCAR_GP_PIN(2, 9),
3062};
3063static const unsigned int msiof2_ss2_c_mux[] = {
3064 MSIOF2_SS2_C_MARK,
3065};
3066static const unsigned int msiof2_txd_c_pins[] = {
3067 /* TXD */
3068 RCAR_GP_PIN(2, 14),
3069};
3070static const unsigned int msiof2_txd_c_mux[] = {
3071 MSIOF2_TXD_C_MARK,
3072};
3073static const unsigned int msiof2_rxd_c_pins[] = {
3074 /* RXD */
3075 RCAR_GP_PIN(2, 13),
3076};
3077static const unsigned int msiof2_rxd_c_mux[] = {
3078 MSIOF2_RXD_C_MARK,
3079};
3080static const unsigned int msiof2_clk_d_pins[] = {
3081 /* SCK */
3082 RCAR_GP_PIN(0, 8),
3083};
3084static const unsigned int msiof2_clk_d_mux[] = {
3085 MSIOF2_SCK_D_MARK,
3086};
3087static const unsigned int msiof2_sync_d_pins[] = {
3088 /* SYNC */
3089 RCAR_GP_PIN(0, 9),
3090};
3091static const unsigned int msiof2_sync_d_mux[] = {
3092 MSIOF2_SYNC_D_MARK,
3093};
3094static const unsigned int msiof2_ss1_d_pins[] = {
3095 /* SS1 */
3096 RCAR_GP_PIN(0, 12),
3097};
3098static const unsigned int msiof2_ss1_d_mux[] = {
3099 MSIOF2_SS1_D_MARK,
3100};
3101static const unsigned int msiof2_ss2_d_pins[] = {
3102 /* SS2 */
3103 RCAR_GP_PIN(0, 13),
3104};
3105static const unsigned int msiof2_ss2_d_mux[] = {
3106 MSIOF2_SS2_D_MARK,
3107};
3108static const unsigned int msiof2_txd_d_pins[] = {
3109 /* TXD */
3110 RCAR_GP_PIN(0, 11),
3111};
3112static const unsigned int msiof2_txd_d_mux[] = {
3113 MSIOF2_TXD_D_MARK,
3114};
3115static const unsigned int msiof2_rxd_d_pins[] = {
3116 /* RXD */
3117 RCAR_GP_PIN(0, 10),
3118};
3119static const unsigned int msiof2_rxd_d_mux[] = {
3120 MSIOF2_RXD_D_MARK,
3121};
3122/* - MSIOF3 ----------------------------------------------------------------- */
3123static const unsigned int msiof3_clk_a_pins[] = {
3124 /* SCK */
3125 RCAR_GP_PIN(0, 0),
3126};
3127static const unsigned int msiof3_clk_a_mux[] = {
3128 MSIOF3_SCK_A_MARK,
3129};
3130static const unsigned int msiof3_sync_a_pins[] = {
3131 /* SYNC */
3132 RCAR_GP_PIN(0, 1),
3133};
3134static const unsigned int msiof3_sync_a_mux[] = {
3135 MSIOF3_SYNC_A_MARK,
3136};
3137static const unsigned int msiof3_ss1_a_pins[] = {
3138 /* SS1 */
3139 RCAR_GP_PIN(0, 14),
3140};
3141static const unsigned int msiof3_ss1_a_mux[] = {
3142 MSIOF3_SS1_A_MARK,
3143};
3144static const unsigned int msiof3_ss2_a_pins[] = {
3145 /* SS2 */
3146 RCAR_GP_PIN(0, 15),
3147};
3148static const unsigned int msiof3_ss2_a_mux[] = {
3149 MSIOF3_SS2_A_MARK,
3150};
3151static const unsigned int msiof3_txd_a_pins[] = {
3152 /* TXD */
3153 RCAR_GP_PIN(0, 3),
3154};
3155static const unsigned int msiof3_txd_a_mux[] = {
3156 MSIOF3_TXD_A_MARK,
3157};
3158static const unsigned int msiof3_rxd_a_pins[] = {
3159 /* RXD */
3160 RCAR_GP_PIN(0, 2),
3161};
3162static const unsigned int msiof3_rxd_a_mux[] = {
3163 MSIOF3_RXD_A_MARK,
3164};
3165static const unsigned int msiof3_clk_b_pins[] = {
3166 /* SCK */
3167 RCAR_GP_PIN(1, 2),
3168};
3169static const unsigned int msiof3_clk_b_mux[] = {
3170 MSIOF3_SCK_B_MARK,
3171};
3172static const unsigned int msiof3_sync_b_pins[] = {
3173 /* SYNC */
3174 RCAR_GP_PIN(1, 0),
3175};
3176static const unsigned int msiof3_sync_b_mux[] = {
3177 MSIOF3_SYNC_B_MARK,
3178};
3179static const unsigned int msiof3_ss1_b_pins[] = {
3180 /* SS1 */
3181 RCAR_GP_PIN(1, 4),
3182};
3183static const unsigned int msiof3_ss1_b_mux[] = {
3184 MSIOF3_SS1_B_MARK,
3185};
3186static const unsigned int msiof3_ss2_b_pins[] = {
3187 /* SS2 */
3188 RCAR_GP_PIN(1, 5),
3189};
3190static const unsigned int msiof3_ss2_b_mux[] = {
3191 MSIOF3_SS2_B_MARK,
3192};
3193static const unsigned int msiof3_txd_b_pins[] = {
3194 /* TXD */
3195 RCAR_GP_PIN(1, 1),
3196};
3197static const unsigned int msiof3_txd_b_mux[] = {
3198 MSIOF3_TXD_B_MARK,
3199};
3200static const unsigned int msiof3_rxd_b_pins[] = {
3201 /* RXD */
3202 RCAR_GP_PIN(1, 3),
3203};
3204static const unsigned int msiof3_rxd_b_mux[] = {
3205 MSIOF3_RXD_B_MARK,
3206};
3207static const unsigned int msiof3_clk_c_pins[] = {
3208 /* SCK */
3209 RCAR_GP_PIN(1, 12),
3210};
3211static const unsigned int msiof3_clk_c_mux[] = {
3212 MSIOF3_SCK_C_MARK,
3213};
3214static const unsigned int msiof3_sync_c_pins[] = {
3215 /* SYNC */
3216 RCAR_GP_PIN(1, 13),
3217};
3218static const unsigned int msiof3_sync_c_mux[] = {
3219 MSIOF3_SYNC_C_MARK,
3220};
3221static const unsigned int msiof3_txd_c_pins[] = {
3222 /* TXD */
3223 RCAR_GP_PIN(1, 15),
3224};
3225static const unsigned int msiof3_txd_c_mux[] = {
3226 MSIOF3_TXD_C_MARK,
3227};
3228static const unsigned int msiof3_rxd_c_pins[] = {
3229 /* RXD */
3230 RCAR_GP_PIN(1, 14),
3231};
3232static const unsigned int msiof3_rxd_c_mux[] = {
3233 MSIOF3_RXD_C_MARK,
3234};
3235static const unsigned int msiof3_clk_d_pins[] = {
3236 /* SCK */
3237 RCAR_GP_PIN(1, 22),
3238};
3239static const unsigned int msiof3_clk_d_mux[] = {
3240 MSIOF3_SCK_D_MARK,
3241};
3242static const unsigned int msiof3_sync_d_pins[] = {
3243 /* SYNC */
3244 RCAR_GP_PIN(1, 23),
3245};
3246static const unsigned int msiof3_sync_d_mux[] = {
3247 MSIOF3_SYNC_D_MARK,
3248};
3249static const unsigned int msiof3_ss1_d_pins[] = {
3250 /* SS1 */
3251 RCAR_GP_PIN(1, 26),
3252};
3253static const unsigned int msiof3_ss1_d_mux[] = {
3254 MSIOF3_SS1_D_MARK,
3255};
3256static const unsigned int msiof3_txd_d_pins[] = {
3257 /* TXD */
3258 RCAR_GP_PIN(1, 25),
3259};
3260static const unsigned int msiof3_txd_d_mux[] = {
3261 MSIOF3_TXD_D_MARK,
3262};
3263static const unsigned int msiof3_rxd_d_pins[] = {
3264 /* RXD */
3265 RCAR_GP_PIN(1, 24),
3266};
3267static const unsigned int msiof3_rxd_d_mux[] = {
3268 MSIOF3_RXD_D_MARK,
3269};
3270static const unsigned int msiof3_clk_e_pins[] = {
3271 /* SCK */
3272 RCAR_GP_PIN(2, 3),
3273};
3274static const unsigned int msiof3_clk_e_mux[] = {
3275 MSIOF3_SCK_E_MARK,
3276};
3277static const unsigned int msiof3_sync_e_pins[] = {
3278 /* SYNC */
3279 RCAR_GP_PIN(2, 2),
3280};
3281static const unsigned int msiof3_sync_e_mux[] = {
3282 MSIOF3_SYNC_E_MARK,
3283};
3284static const unsigned int msiof3_ss1_e_pins[] = {
3285 /* SS1 */
3286 RCAR_GP_PIN(2, 1),
3287};
3288static const unsigned int msiof3_ss1_e_mux[] = {
3289 MSIOF3_SS1_E_MARK,
3290};
3291static const unsigned int msiof3_ss2_e_pins[] = {
3292 /* SS2 */
3293 RCAR_GP_PIN(2, 0),
3294};
3295static const unsigned int msiof3_ss2_e_mux[] = {
3296 MSIOF3_SS2_E_MARK,
3297};
3298static const unsigned int msiof3_txd_e_pins[] = {
3299 /* TXD */
3300 RCAR_GP_PIN(2, 5),
3301};
3302static const unsigned int msiof3_txd_e_mux[] = {
3303 MSIOF3_TXD_E_MARK,
3304};
3305static const unsigned int msiof3_rxd_e_pins[] = {
3306 /* RXD */
3307 RCAR_GP_PIN(2, 4),
3308};
3309static const unsigned int msiof3_rxd_e_mux[] = {
3310 MSIOF3_RXD_E_MARK,
3311};
3312
3313/* - PWM0 --------------------------------------------------------------------*/
3314static const unsigned int pwm0_pins[] = {
3315 /* PWM */
3316 RCAR_GP_PIN(2, 6),
3317};
3318static const unsigned int pwm0_mux[] = {
3319 PWM0_MARK,
3320};
3321/* - PWM1 --------------------------------------------------------------------*/
3322static const unsigned int pwm1_a_pins[] = {
3323 /* PWM */
3324 RCAR_GP_PIN(2, 7),
3325};
3326static const unsigned int pwm1_a_mux[] = {
3327 PWM1_A_MARK,
3328};
3329static const unsigned int pwm1_b_pins[] = {
3330 /* PWM */
3331 RCAR_GP_PIN(1, 8),
3332};
3333static const unsigned int pwm1_b_mux[] = {
3334 PWM1_B_MARK,
3335};
3336/* - PWM2 --------------------------------------------------------------------*/
3337static const unsigned int pwm2_a_pins[] = {
3338 /* PWM */
3339 RCAR_GP_PIN(2, 8),
3340};
3341static const unsigned int pwm2_a_mux[] = {
3342 PWM2_A_MARK,
3343};
3344static const unsigned int pwm2_b_pins[] = {
3345 /* PWM */
3346 RCAR_GP_PIN(1, 11),
3347};
3348static const unsigned int pwm2_b_mux[] = {
3349 PWM2_B_MARK,
3350};
3351/* - PWM3 --------------------------------------------------------------------*/
3352static const unsigned int pwm3_a_pins[] = {
3353 /* PWM */
3354 RCAR_GP_PIN(1, 0),
3355};
3356static const unsigned int pwm3_a_mux[] = {
3357 PWM3_A_MARK,
3358};
3359static const unsigned int pwm3_b_pins[] = {
3360 /* PWM */
3361 RCAR_GP_PIN(2, 2),
3362};
3363static const unsigned int pwm3_b_mux[] = {
3364 PWM3_B_MARK,
3365};
3366/* - PWM4 --------------------------------------------------------------------*/
3367static const unsigned int pwm4_a_pins[] = {
3368 /* PWM */
3369 RCAR_GP_PIN(1, 1),
3370};
3371static const unsigned int pwm4_a_mux[] = {
3372 PWM4_A_MARK,
3373};
3374static const unsigned int pwm4_b_pins[] = {
3375 /* PWM */
3376 RCAR_GP_PIN(2, 3),
3377};
3378static const unsigned int pwm4_b_mux[] = {
3379 PWM4_B_MARK,
3380};
3381/* - PWM5 --------------------------------------------------------------------*/
3382static const unsigned int pwm5_a_pins[] = {
3383 /* PWM */
3384 RCAR_GP_PIN(1, 2),
3385};
3386static const unsigned int pwm5_a_mux[] = {
3387 PWM5_A_MARK,
3388};
3389static const unsigned int pwm5_b_pins[] = {
3390 /* PWM */
3391 RCAR_GP_PIN(2, 4),
3392};
3393static const unsigned int pwm5_b_mux[] = {
3394 PWM5_B_MARK,
3395};
3396/* - PWM6 --------------------------------------------------------------------*/
3397static const unsigned int pwm6_a_pins[] = {
3398 /* PWM */
3399 RCAR_GP_PIN(1, 3),
3400};
3401static const unsigned int pwm6_a_mux[] = {
3402 PWM6_A_MARK,
3403};
3404static const unsigned int pwm6_b_pins[] = {
3405 /* PWM */
3406 RCAR_GP_PIN(2, 5),
3407};
3408static const unsigned int pwm6_b_mux[] = {
3409 PWM6_B_MARK,
3410};
3411
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame^]3412/* - QSPI0 ------------------------------------------------------------------ */
3413static const unsigned int qspi0_ctrl_pins[] = {
3414 /* QSPI0_SPCLK, QSPI0_SSL */
3415 PIN_QSPI0_SPCLK, PIN_QSPI0_SSL,
3416};
3417static const unsigned int qspi0_ctrl_mux[] = {
3418 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
3419};
3420static const unsigned int qspi0_data2_pins[] = {
3421 /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
3422 PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
3423};
3424static const unsigned int qspi0_data2_mux[] = {
3425 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
3426};
3427static const unsigned int qspi0_data4_pins[] = {
3428 /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
3429 PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
3430 /* QSPI0_IO2, QSPI0_IO3 */
3431 PIN_QSPI0_IO2, PIN_QSPI0_IO3,
3432};
3433static const unsigned int qspi0_data4_mux[] = {
3434 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
3435 QSPI0_IO2_MARK, QSPI0_IO3_MARK,
3436};
3437/* - QSPI1 ------------------------------------------------------------------ */
3438static const unsigned int qspi1_ctrl_pins[] = {
3439 /* QSPI1_SPCLK, QSPI1_SSL */
3440 PIN_QSPI1_SPCLK, PIN_QSPI1_SSL,
3441};
3442static const unsigned int qspi1_ctrl_mux[] = {
3443 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
3444};
3445static const unsigned int qspi1_data2_pins[] = {
3446 /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
3447 PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
3448};
3449static const unsigned int qspi1_data2_mux[] = {
3450 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
3451};
3452static const unsigned int qspi1_data4_pins[] = {
3453 /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
3454 PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
3455 /* QSPI1_IO2, QSPI1_IO3 */
3456 PIN_QSPI1_IO2, PIN_QSPI1_IO3,
3457};
3458static const unsigned int qspi1_data4_mux[] = {
3459 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
3460 QSPI1_IO2_MARK, QSPI1_IO3_MARK,
3461};
3462
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]3463/* - SATA --------------------------------------------------------------------*/
3464static const unsigned int sata0_devslp_a_pins[] = {
3465 /* DEVSLP */
3466 RCAR_GP_PIN(6, 16),
3467};
3468
3469static const unsigned int sata0_devslp_a_mux[] = {
3470 SATA_DEVSLP_A_MARK,
3471};
3472
3473static const unsigned int sata0_devslp_b_pins[] = {
3474 /* DEVSLP */
3475 RCAR_GP_PIN(4, 6),
3476};
3477
3478static const unsigned int sata0_devslp_b_mux[] = {
3479 SATA_DEVSLP_B_MARK,
3480};
3481
3482/* - SCIF0 ------------------------------------------------------------------ */
3483static const unsigned int scif0_data_pins[] = {
3484 /* RX, TX */
3485 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3486};
3487static const unsigned int scif0_data_mux[] = {
3488 RX0_MARK, TX0_MARK,
3489};
3490static const unsigned int scif0_clk_pins[] = {
3491 /* SCK */
3492 RCAR_GP_PIN(5, 0),
3493};
3494static const unsigned int scif0_clk_mux[] = {
3495 SCK0_MARK,
3496};
3497static const unsigned int scif0_ctrl_pins[] = {
3498 /* RTS, CTS */
3499 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3500};
3501static const unsigned int scif0_ctrl_mux[] = {
3502 RTS0_N_MARK, CTS0_N_MARK,
3503};
3504/* - SCIF1 ------------------------------------------------------------------ */
3505static const unsigned int scif1_data_a_pins[] = {
3506 /* RX, TX */
3507 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3508};
3509static const unsigned int scif1_data_a_mux[] = {
3510 RX1_A_MARK, TX1_A_MARK,
3511};
3512static const unsigned int scif1_clk_pins[] = {
3513 /* SCK */
3514 RCAR_GP_PIN(6, 21),
3515};
3516static const unsigned int scif1_clk_mux[] = {
3517 SCK1_MARK,
3518};
3519static const unsigned int scif1_ctrl_pins[] = {
3520 /* RTS, CTS */
3521 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3522};
3523static const unsigned int scif1_ctrl_mux[] = {
3524 RTS1_N_MARK, CTS1_N_MARK,
3525};
3526static const unsigned int scif1_data_b_pins[] = {
3527 /* RX, TX */
3528 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3529};
3530static const unsigned int scif1_data_b_mux[] = {
3531 RX1_B_MARK, TX1_B_MARK,
3532};
3533/* - SCIF2 ------------------------------------------------------------------ */
3534static const unsigned int scif2_data_a_pins[] = {
3535 /* RX, TX */
3536 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3537};
3538static const unsigned int scif2_data_a_mux[] = {
3539 RX2_A_MARK, TX2_A_MARK,
3540};
3541static const unsigned int scif2_clk_pins[] = {
3542 /* SCK */
3543 RCAR_GP_PIN(5, 9),
3544};
3545static const unsigned int scif2_clk_mux[] = {
3546 SCK2_MARK,
3547};
3548static const unsigned int scif2_data_b_pins[] = {
3549 /* RX, TX */
3550 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3551};
3552static const unsigned int scif2_data_b_mux[] = {
3553 RX2_B_MARK, TX2_B_MARK,
3554};
3555/* - SCIF3 ------------------------------------------------------------------ */
3556static const unsigned int scif3_data_a_pins[] = {
3557 /* RX, TX */
3558 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3559};
3560static const unsigned int scif3_data_a_mux[] = {
3561 RX3_A_MARK, TX3_A_MARK,
3562};
3563static const unsigned int scif3_clk_pins[] = {
3564 /* SCK */
3565 RCAR_GP_PIN(1, 22),
3566};
3567static const unsigned int scif3_clk_mux[] = {
3568 SCK3_MARK,
3569};
3570static const unsigned int scif3_ctrl_pins[] = {
3571 /* RTS, CTS */
3572 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3573};
3574static const unsigned int scif3_ctrl_mux[] = {
3575 RTS3_N_MARK, CTS3_N_MARK,
3576};
3577static const unsigned int scif3_data_b_pins[] = {
3578 /* RX, TX */
3579 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3580};
3581static const unsigned int scif3_data_b_mux[] = {
3582 RX3_B_MARK, TX3_B_MARK,
3583};
3584/* - SCIF4 ------------------------------------------------------------------ */
3585static const unsigned int scif4_data_a_pins[] = {
3586 /* RX, TX */
3587 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3588};
3589static const unsigned int scif4_data_a_mux[] = {
3590 RX4_A_MARK, TX4_A_MARK,
3591};
3592static const unsigned int scif4_clk_a_pins[] = {
3593 /* SCK */
3594 RCAR_GP_PIN(2, 10),
3595};
3596static const unsigned int scif4_clk_a_mux[] = {
3597 SCK4_A_MARK,
3598};
3599static const unsigned int scif4_ctrl_a_pins[] = {
3600 /* RTS, CTS */
3601 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3602};
3603static const unsigned int scif4_ctrl_a_mux[] = {
3604 RTS4_N_A_MARK, CTS4_N_A_MARK,
3605};
3606static const unsigned int scif4_data_b_pins[] = {
3607 /* RX, TX */
3608 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3609};
3610static const unsigned int scif4_data_b_mux[] = {
3611 RX4_B_MARK, TX4_B_MARK,
3612};
3613static const unsigned int scif4_clk_b_pins[] = {
3614 /* SCK */
3615 RCAR_GP_PIN(1, 5),
3616};
3617static const unsigned int scif4_clk_b_mux[] = {
3618 SCK4_B_MARK,
3619};
3620static const unsigned int scif4_ctrl_b_pins[] = {
3621 /* RTS, CTS */
3622 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3623};
3624static const unsigned int scif4_ctrl_b_mux[] = {
3625 RTS4_N_B_MARK, CTS4_N_B_MARK,
3626};
3627static const unsigned int scif4_data_c_pins[] = {
3628 /* RX, TX */
3629 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3630};
3631static const unsigned int scif4_data_c_mux[] = {
3632 RX4_C_MARK, TX4_C_MARK,
3633};
3634static const unsigned int scif4_clk_c_pins[] = {
3635 /* SCK */
3636 RCAR_GP_PIN(0, 8),
3637};
3638static const unsigned int scif4_clk_c_mux[] = {
3639 SCK4_C_MARK,
3640};
3641static const unsigned int scif4_ctrl_c_pins[] = {
3642 /* RTS, CTS */
3643 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3644};
3645static const unsigned int scif4_ctrl_c_mux[] = {
3646 RTS4_N_C_MARK, CTS4_N_C_MARK,
3647};
3648/* - SCIF5 ------------------------------------------------------------------ */
3649static const unsigned int scif5_data_a_pins[] = {
3650 /* RX, TX */
3651 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3652};
3653static const unsigned int scif5_data_a_mux[] = {
3654 RX5_A_MARK, TX5_A_MARK,
3655};
3656static const unsigned int scif5_clk_a_pins[] = {
3657 /* SCK */
3658 RCAR_GP_PIN(6, 21),
3659};
3660static const unsigned int scif5_clk_a_mux[] = {
3661 SCK5_A_MARK,
3662};
3663static const unsigned int scif5_data_b_pins[] = {
3664 /* RX, TX */
3665 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3666};
3667static const unsigned int scif5_data_b_mux[] = {
3668 RX5_B_MARK, TX5_B_MARK,
3669};
3670static const unsigned int scif5_clk_b_pins[] = {
3671 /* SCK */
3672 RCAR_GP_PIN(5, 0),
3673};
3674static const unsigned int scif5_clk_b_mux[] = {
3675 SCK5_B_MARK,
3676};
3677/* - SCIF Clock ------------------------------------------------------------- */
3678static const unsigned int scif_clk_a_pins[] = {
3679 /* SCIF_CLK */
3680 RCAR_GP_PIN(6, 23),
3681};
3682static const unsigned int scif_clk_a_mux[] = {
3683 SCIF_CLK_A_MARK,
3684};
3685static const unsigned int scif_clk_b_pins[] = {
3686 /* SCIF_CLK */
3687 RCAR_GP_PIN(5, 9),
3688};
3689static const unsigned int scif_clk_b_mux[] = {
3690 SCIF_CLK_B_MARK,
3691};
3692
3693/* - SDHI0 ------------------------------------------------------------------ */
3694static const unsigned int sdhi0_data1_pins[] = {
3695 /* D0 */
3696 RCAR_GP_PIN(3, 2),
3697};
3698
3699static const unsigned int sdhi0_data1_mux[] = {
3700 SD0_DAT0_MARK,
3701};
3702
3703static const unsigned int sdhi0_data4_pins[] = {
3704 /* D[0:3] */
3705 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3706 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3707};
3708
3709static const unsigned int sdhi0_data4_mux[] = {
3710 SD0_DAT0_MARK, SD0_DAT1_MARK,
3711 SD0_DAT2_MARK, SD0_DAT3_MARK,
3712};
3713
3714static const unsigned int sdhi0_ctrl_pins[] = {
3715 /* CLK, CMD */
3716 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3717};
3718
3719static const unsigned int sdhi0_ctrl_mux[] = {
3720 SD0_CLK_MARK, SD0_CMD_MARK,
3721};
3722
3723static const unsigned int sdhi0_cd_pins[] = {
3724 /* CD */
3725 RCAR_GP_PIN(3, 12),
3726};
3727
3728static const unsigned int sdhi0_cd_mux[] = {
3729 SD0_CD_MARK,
3730};
3731
3732static const unsigned int sdhi0_wp_pins[] = {
3733 /* WP */
3734 RCAR_GP_PIN(3, 13),
3735};
3736
3737static const unsigned int sdhi0_wp_mux[] = {
3738 SD0_WP_MARK,
3739};
3740
3741/* - SDHI1 ------------------------------------------------------------------ */
3742static const unsigned int sdhi1_data1_pins[] = {
3743 /* D0 */
3744 RCAR_GP_PIN(3, 8),
3745};
3746
3747static const unsigned int sdhi1_data1_mux[] = {
3748 SD1_DAT0_MARK,
3749};
3750
3751static const unsigned int sdhi1_data4_pins[] = {
3752 /* D[0:3] */
3753 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3754 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3755};
3756
3757static const unsigned int sdhi1_data4_mux[] = {
3758 SD1_DAT0_MARK, SD1_DAT1_MARK,
3759 SD1_DAT2_MARK, SD1_DAT3_MARK,
3760};
3761
3762static const unsigned int sdhi1_ctrl_pins[] = {
3763 /* CLK, CMD */
3764 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3765};
3766
3767static const unsigned int sdhi1_ctrl_mux[] = {
3768 SD1_CLK_MARK, SD1_CMD_MARK,
3769};
3770
3771static const unsigned int sdhi1_cd_pins[] = {
3772 /* CD */
3773 RCAR_GP_PIN(3, 14),
3774};
3775
3776static const unsigned int sdhi1_cd_mux[] = {
3777 SD1_CD_MARK,
3778};
3779
3780static const unsigned int sdhi1_wp_pins[] = {
3781 /* WP */
3782 RCAR_GP_PIN(3, 15),
3783};
3784
3785static const unsigned int sdhi1_wp_mux[] = {
3786 SD1_WP_MARK,
3787};
3788
3789/* - SDHI2 ------------------------------------------------------------------ */
3790static const unsigned int sdhi2_data1_pins[] = {
3791 /* D0 */
3792 RCAR_GP_PIN(4, 2),
3793};
3794
3795static const unsigned int sdhi2_data1_mux[] = {
3796 SD2_DAT0_MARK,
3797};
3798
3799static const unsigned int sdhi2_data4_pins[] = {
3800 /* D[0:3] */
3801 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3802 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3803};
3804
3805static const unsigned int sdhi2_data4_mux[] = {
3806 SD2_DAT0_MARK, SD2_DAT1_MARK,
3807 SD2_DAT2_MARK, SD2_DAT3_MARK,
3808};
3809
3810static const unsigned int sdhi2_data8_pins[] = {
3811 /* D[0:7] */
3812 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3813 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3814 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3815 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3816};
3817
3818static const unsigned int sdhi2_data8_mux[] = {
3819 SD2_DAT0_MARK, SD2_DAT1_MARK,
3820 SD2_DAT2_MARK, SD2_DAT3_MARK,
3821 SD2_DAT4_MARK, SD2_DAT5_MARK,
3822 SD2_DAT6_MARK, SD2_DAT7_MARK,
3823};
3824
3825static const unsigned int sdhi2_ctrl_pins[] = {
3826 /* CLK, CMD */
3827 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3828};
3829
3830static const unsigned int sdhi2_ctrl_mux[] = {
3831 SD2_CLK_MARK, SD2_CMD_MARK,
3832};
3833
3834static const unsigned int sdhi2_cd_a_pins[] = {
3835 /* CD */
3836 RCAR_GP_PIN(4, 13),
3837};
3838
3839static const unsigned int sdhi2_cd_a_mux[] = {
3840 SD2_CD_A_MARK,
3841};
3842
3843static const unsigned int sdhi2_cd_b_pins[] = {
3844 /* CD */
3845 RCAR_GP_PIN(5, 10),
3846};
3847
3848static const unsigned int sdhi2_cd_b_mux[] = {
3849 SD2_CD_B_MARK,
3850};
3851
3852static const unsigned int sdhi2_wp_a_pins[] = {
3853 /* WP */
3854 RCAR_GP_PIN(4, 14),
3855};
3856
3857static const unsigned int sdhi2_wp_a_mux[] = {
3858 SD2_WP_A_MARK,
3859};
3860
3861static const unsigned int sdhi2_wp_b_pins[] = {
3862 /* WP */
3863 RCAR_GP_PIN(5, 11),
3864};
3865
3866static const unsigned int sdhi2_wp_b_mux[] = {
3867 SD2_WP_B_MARK,
3868};
3869
3870static const unsigned int sdhi2_ds_pins[] = {
3871 /* DS */
3872 RCAR_GP_PIN(4, 6),
3873};
3874
3875static const unsigned int sdhi2_ds_mux[] = {
3876 SD2_DS_MARK,
3877};
3878
3879/* - SDHI3 ------------------------------------------------------------------ */
3880static const unsigned int sdhi3_data1_pins[] = {
3881 /* D0 */
3882 RCAR_GP_PIN(4, 9),
3883};
3884
3885static const unsigned int sdhi3_data1_mux[] = {
3886 SD3_DAT0_MARK,
3887};
3888
3889static const unsigned int sdhi3_data4_pins[] = {
3890 /* D[0:3] */
3891 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3892 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3893};
3894
3895static const unsigned int sdhi3_data4_mux[] = {
3896 SD3_DAT0_MARK, SD3_DAT1_MARK,
3897 SD3_DAT2_MARK, SD3_DAT3_MARK,
3898};
3899
3900static const unsigned int sdhi3_data8_pins[] = {
3901 /* D[0:7] */
3902 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3903 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3904 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3905 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3906};
3907
3908static const unsigned int sdhi3_data8_mux[] = {
3909 SD3_DAT0_MARK, SD3_DAT1_MARK,
3910 SD3_DAT2_MARK, SD3_DAT3_MARK,
3911 SD3_DAT4_MARK, SD3_DAT5_MARK,
3912 SD3_DAT6_MARK, SD3_DAT7_MARK,
3913};
3914
3915static const unsigned int sdhi3_ctrl_pins[] = {
3916 /* CLK, CMD */
3917 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3918};
3919
3920static const unsigned int sdhi3_ctrl_mux[] = {
3921 SD3_CLK_MARK, SD3_CMD_MARK,
3922};
3923
3924static const unsigned int sdhi3_cd_pins[] = {
3925 /* CD */
3926 RCAR_GP_PIN(4, 15),
3927};
3928
3929static const unsigned int sdhi3_cd_mux[] = {
3930 SD3_CD_MARK,
3931};
3932
3933static const unsigned int sdhi3_wp_pins[] = {
3934 /* WP */
3935 RCAR_GP_PIN(4, 16),
3936};
3937
3938static const unsigned int sdhi3_wp_mux[] = {
3939 SD3_WP_MARK,
3940};
3941
3942static const unsigned int sdhi3_ds_pins[] = {
3943 /* DS */
3944 RCAR_GP_PIN(4, 17),
3945};
3946
3947static const unsigned int sdhi3_ds_mux[] = {
3948 SD3_DS_MARK,
3949};
3950
3951/* - SSI -------------------------------------------------------------------- */
3952static const unsigned int ssi0_data_pins[] = {
3953 /* SDATA */
3954 RCAR_GP_PIN(6, 2),
3955};
3956static const unsigned int ssi0_data_mux[] = {
3957 SSI_SDATA0_MARK,
3958};
3959static const unsigned int ssi01239_ctrl_pins[] = {
3960 /* SCK, WS */
3961 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3962};
3963static const unsigned int ssi01239_ctrl_mux[] = {
3964 SSI_SCK01239_MARK, SSI_WS01239_MARK,
3965};
3966static const unsigned int ssi1_data_a_pins[] = {
3967 /* SDATA */
3968 RCAR_GP_PIN(6, 3),
3969};
3970static const unsigned int ssi1_data_a_mux[] = {
3971 SSI_SDATA1_A_MARK,
3972};
3973static const unsigned int ssi1_data_b_pins[] = {
3974 /* SDATA */
3975 RCAR_GP_PIN(5, 12),
3976};
3977static const unsigned int ssi1_data_b_mux[] = {
3978 SSI_SDATA1_B_MARK,
3979};
3980static const unsigned int ssi1_ctrl_a_pins[] = {
3981 /* SCK, WS */
3982 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3983};
3984static const unsigned int ssi1_ctrl_a_mux[] = {
3985 SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3986};
3987static const unsigned int ssi1_ctrl_b_pins[] = {
3988 /* SCK, WS */
3989 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3990};
3991static const unsigned int ssi1_ctrl_b_mux[] = {
3992 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3993};
3994static const unsigned int ssi2_data_a_pins[] = {
3995 /* SDATA */
3996 RCAR_GP_PIN(6, 4),
3997};
3998static const unsigned int ssi2_data_a_mux[] = {
3999 SSI_SDATA2_A_MARK,
4000};
4001static const unsigned int ssi2_data_b_pins[] = {
4002 /* SDATA */
4003 RCAR_GP_PIN(5, 13),
4004};
4005static const unsigned int ssi2_data_b_mux[] = {
4006 SSI_SDATA2_B_MARK,
4007};
4008static const unsigned int ssi2_ctrl_a_pins[] = {
4009 /* SCK, WS */
4010 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
4011};
4012static const unsigned int ssi2_ctrl_a_mux[] = {
4013 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
4014};
4015static const unsigned int ssi2_ctrl_b_pins[] = {
4016 /* SCK, WS */
4017 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
4018};
4019static const unsigned int ssi2_ctrl_b_mux[] = {
4020 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
4021};
4022static const unsigned int ssi3_data_pins[] = {
4023 /* SDATA */
4024 RCAR_GP_PIN(6, 7),
4025};
4026static const unsigned int ssi3_data_mux[] = {
4027 SSI_SDATA3_MARK,
4028};
4029static const unsigned int ssi349_ctrl_pins[] = {
4030 /* SCK, WS */
4031 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
4032};
4033static const unsigned int ssi349_ctrl_mux[] = {
4034 SSI_SCK349_MARK, SSI_WS349_MARK,
4035};
4036static const unsigned int ssi4_data_pins[] = {
4037 /* SDATA */
4038 RCAR_GP_PIN(6, 10),
4039};
4040static const unsigned int ssi4_data_mux[] = {
4041 SSI_SDATA4_MARK,
4042};
4043static const unsigned int ssi4_ctrl_pins[] = {
4044 /* SCK, WS */
4045 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
4046};
4047static const unsigned int ssi4_ctrl_mux[] = {
4048 SSI_SCK4_MARK, SSI_WS4_MARK,
4049};
4050static const unsigned int ssi5_data_pins[] = {
4051 /* SDATA */
4052 RCAR_GP_PIN(6, 13),
4053};
4054static const unsigned int ssi5_data_mux[] = {
4055 SSI_SDATA5_MARK,
4056};
4057static const unsigned int ssi5_ctrl_pins[] = {
4058 /* SCK, WS */
4059 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
4060};
4061static const unsigned int ssi5_ctrl_mux[] = {
4062 SSI_SCK5_MARK, SSI_WS5_MARK,
4063};
4064static const unsigned int ssi6_data_pins[] = {
4065 /* SDATA */
4066 RCAR_GP_PIN(6, 16),
4067};
4068static const unsigned int ssi6_data_mux[] = {
4069 SSI_SDATA6_MARK,
4070};
4071static const unsigned int ssi6_ctrl_pins[] = {
4072 /* SCK, WS */
4073 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
4074};
4075static const unsigned int ssi6_ctrl_mux[] = {
4076 SSI_SCK6_MARK, SSI_WS6_MARK,
4077};
4078static const unsigned int ssi7_data_pins[] = {
4079 /* SDATA */
4080 RCAR_GP_PIN(6, 19),
4081};
4082static const unsigned int ssi7_data_mux[] = {
4083 SSI_SDATA7_MARK,
4084};
4085static const unsigned int ssi78_ctrl_pins[] = {
4086 /* SCK, WS */
4087 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
4088};
4089static const unsigned int ssi78_ctrl_mux[] = {
4090 SSI_SCK78_MARK, SSI_WS78_MARK,
4091};
4092static const unsigned int ssi8_data_pins[] = {
4093 /* SDATA */
4094 RCAR_GP_PIN(6, 20),
4095};
4096static const unsigned int ssi8_data_mux[] = {
4097 SSI_SDATA8_MARK,
4098};
4099static const unsigned int ssi9_data_a_pins[] = {
4100 /* SDATA */
4101 RCAR_GP_PIN(6, 21),
4102};
4103static const unsigned int ssi9_data_a_mux[] = {
4104 SSI_SDATA9_A_MARK,
4105};
4106static const unsigned int ssi9_data_b_pins[] = {
4107 /* SDATA */
4108 RCAR_GP_PIN(5, 14),
4109};
4110static const unsigned int ssi9_data_b_mux[] = {
4111 SSI_SDATA9_B_MARK,
4112};
4113static const unsigned int ssi9_ctrl_a_pins[] = {
4114 /* SCK, WS */
4115 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
4116};
4117static const unsigned int ssi9_ctrl_a_mux[] = {
4118 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
4119};
4120static const unsigned int ssi9_ctrl_b_pins[] = {
4121 /* SCK, WS */
4122 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
4123};
4124static const unsigned int ssi9_ctrl_b_mux[] = {
4125 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
4126};
4127
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4128/* - TMU -------------------------------------------------------------------- */
4129static const unsigned int tmu_tclk1_a_pins[] = {
4130 /* TCLK */
4131 RCAR_GP_PIN(6, 23),
4132};
4133
4134static const unsigned int tmu_tclk1_a_mux[] = {
4135 TCLK1_A_MARK,
4136};
4137
4138static const unsigned int tmu_tclk1_b_pins[] = {
4139 /* TCLK */
4140 RCAR_GP_PIN(5, 19),
4141};
4142
4143static const unsigned int tmu_tclk1_b_mux[] = {
4144 TCLK1_B_MARK,
4145};
4146
4147static const unsigned int tmu_tclk2_a_pins[] = {
4148 /* TCLK */
4149 RCAR_GP_PIN(6, 19),
4150};
4151
4152static const unsigned int tmu_tclk2_a_mux[] = {
4153 TCLK2_A_MARK,
4154};
4155
4156static const unsigned int tmu_tclk2_b_pins[] = {
4157 /* TCLK */
4158 RCAR_GP_PIN(6, 28),
4159};
4160
4161static const unsigned int tmu_tclk2_b_mux[] = {
4162 TCLK2_B_MARK,
4163};
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4164
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]4165/* - TPU ------------------------------------------------------------------- */
4166static const unsigned int tpu_to0_pins[] = {
4167 /* TPU0TO0 */
4168 RCAR_GP_PIN(6, 28),
4169};
4170static const unsigned int tpu_to0_mux[] = {
4171 TPU0TO0_MARK,
4172};
4173static const unsigned int tpu_to1_pins[] = {
4174 /* TPU0TO1 */
4175 RCAR_GP_PIN(6, 29),
4176};
4177static const unsigned int tpu_to1_mux[] = {
4178 TPU0TO1_MARK,
4179};
4180static const unsigned int tpu_to2_pins[] = {
4181 /* TPU0TO2 */
4182 RCAR_GP_PIN(6, 30),
4183};
4184static const unsigned int tpu_to2_mux[] = {
4185 TPU0TO2_MARK,
4186};
4187static const unsigned int tpu_to3_pins[] = {
4188 /* TPU0TO3 */
4189 RCAR_GP_PIN(6, 31),
4190};
4191static const unsigned int tpu_to3_mux[] = {
4192 TPU0TO3_MARK,
4193};
4194
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4195/* - USB0 ------------------------------------------------------------------- */
4196static const unsigned int usb0_pins[] = {
4197 /* PWEN, OVC */
4198 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
4199};
4200
4201static const unsigned int usb0_mux[] = {
4202 USB0_PWEN_MARK, USB0_OVC_MARK,
4203};
4204
4205/* - USB1 ------------------------------------------------------------------- */
4206static const unsigned int usb1_pins[] = {
4207 /* PWEN, OVC */
4208 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
4209};
4210
4211static const unsigned int usb1_mux[] = {
4212 USB1_PWEN_MARK, USB1_OVC_MARK,
4213};
4214
4215/* - USB30 ------------------------------------------------------------------ */
4216static const unsigned int usb30_pins[] = {
4217 /* PWEN, OVC */
4218 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
4219};
4220
4221static const unsigned int usb30_mux[] = {
4222 USB30_PWEN_MARK, USB30_OVC_MARK,
4223};
4224
4225/* - VIN4 ------------------------------------------------------------------- */
4226static const unsigned int vin4_data18_a_pins[] = {
4227 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
4228 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
4229 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
4230 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4231 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4232 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4233 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4234 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4235 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4236};
4237
4238static const unsigned int vin4_data18_a_mux[] = {
4239 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4240 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4241 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4242 VI4_DATA10_MARK, VI4_DATA11_MARK,
4243 VI4_DATA12_MARK, VI4_DATA13_MARK,
4244 VI4_DATA14_MARK, VI4_DATA15_MARK,
4245 VI4_DATA18_MARK, VI4_DATA19_MARK,
4246 VI4_DATA20_MARK, VI4_DATA21_MARK,
4247 VI4_DATA22_MARK, VI4_DATA23_MARK,
4248};
4249
4250static const union vin_data vin4_data_a_pins = {
4251 .data24 = {
4252 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
4253 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
4254 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
4255 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
4256 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4257 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4258 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4259 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4260 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4261 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4262 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4263 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4264 },
4265};
4266
4267static const union vin_data vin4_data_a_mux = {
4268 .data24 = {
4269 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
4270 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4271 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4272 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4273 VI4_DATA8_MARK, VI4_DATA9_MARK,
4274 VI4_DATA10_MARK, VI4_DATA11_MARK,
4275 VI4_DATA12_MARK, VI4_DATA13_MARK,
4276 VI4_DATA14_MARK, VI4_DATA15_MARK,
4277 VI4_DATA16_MARK, VI4_DATA17_MARK,
4278 VI4_DATA18_MARK, VI4_DATA19_MARK,
4279 VI4_DATA20_MARK, VI4_DATA21_MARK,
4280 VI4_DATA22_MARK, VI4_DATA23_MARK,
4281 },
4282};
4283
4284static const unsigned int vin4_data18_b_pins[] = {
4285 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4286 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4287 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4288 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4289 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4290 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4291 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4292 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4293 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4294};
4295
4296static const unsigned int vin4_data18_b_mux[] = {
4297 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4298 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4299 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4300 VI4_DATA10_MARK, VI4_DATA11_MARK,
4301 VI4_DATA12_MARK, VI4_DATA13_MARK,
4302 VI4_DATA14_MARK, VI4_DATA15_MARK,
4303 VI4_DATA18_MARK, VI4_DATA19_MARK,
4304 VI4_DATA20_MARK, VI4_DATA21_MARK,
4305 VI4_DATA22_MARK, VI4_DATA23_MARK,
4306};
4307
4308static const union vin_data vin4_data_b_pins = {
4309 .data24 = {
4310 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
4311 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4312 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4313 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4314 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4315 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4316 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4317 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4318 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4319 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4320 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4321 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4322 },
4323};
4324
4325static const union vin_data vin4_data_b_mux = {
4326 .data24 = {
4327 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
4328 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4329 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4330 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4331 VI4_DATA8_MARK, VI4_DATA9_MARK,
4332 VI4_DATA10_MARK, VI4_DATA11_MARK,
4333 VI4_DATA12_MARK, VI4_DATA13_MARK,
4334 VI4_DATA14_MARK, VI4_DATA15_MARK,
4335 VI4_DATA16_MARK, VI4_DATA17_MARK,
4336 VI4_DATA18_MARK, VI4_DATA19_MARK,
4337 VI4_DATA20_MARK, VI4_DATA21_MARK,
4338 VI4_DATA22_MARK, VI4_DATA23_MARK,
4339 },
4340};
4341
4342static const unsigned int vin4_sync_pins[] = {
4343 /* VSYNC_N, HSYNC_N */
4344 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
4345};
4346
4347static const unsigned int vin4_sync_mux[] = {
4348 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
4349};
4350
4351static const unsigned int vin4_field_pins[] = {
4352 RCAR_GP_PIN(1, 16),
4353};
4354
4355static const unsigned int vin4_field_mux[] = {
4356 VI4_FIELD_MARK,
4357};
4358
4359static const unsigned int vin4_clkenb_pins[] = {
4360 RCAR_GP_PIN(1, 19),
4361};
4362
4363static const unsigned int vin4_clkenb_mux[] = {
4364 VI4_CLKENB_MARK,
4365};
4366
4367static const unsigned int vin4_clk_pins[] = {
4368 RCAR_GP_PIN(1, 27),
4369};
4370
4371static const unsigned int vin4_clk_mux[] = {
4372 VI4_CLK_MARK,
4373};
4374
4375/* - VIN5 ------------------------------------------------------------------- */
4376static const union vin_data16 vin5_data_pins = {
4377 .data16 = {
4378 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4379 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4380 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4381 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4382 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4383 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4384 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4385 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4386 },
4387};
4388
4389static const union vin_data16 vin5_data_mux = {
4390 .data16 = {
4391 VI5_DATA0_MARK, VI5_DATA1_MARK,
4392 VI5_DATA2_MARK, VI5_DATA3_MARK,
4393 VI5_DATA4_MARK, VI5_DATA5_MARK,
4394 VI5_DATA6_MARK, VI5_DATA7_MARK,
4395 VI5_DATA8_MARK, VI5_DATA9_MARK,
4396 VI5_DATA10_MARK, VI5_DATA11_MARK,
4397 VI5_DATA12_MARK, VI5_DATA13_MARK,
4398 VI5_DATA14_MARK, VI5_DATA15_MARK,
4399 },
4400};
4401
4402static const unsigned int vin5_sync_pins[] = {
4403 /* VSYNC_N, HSYNC_N */
4404 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
4405};
4406
4407static const unsigned int vin5_sync_mux[] = {
4408 VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
4409};
4410
4411static const unsigned int vin5_field_pins[] = {
4412 RCAR_GP_PIN(1, 11),
4413};
4414
4415static const unsigned int vin5_field_mux[] = {
4416 VI5_FIELD_MARK,
4417};
4418
4419static const unsigned int vin5_clkenb_pins[] = {
4420 RCAR_GP_PIN(1, 20),
4421};
4422
4423static const unsigned int vin5_clkenb_mux[] = {
4424 VI5_CLKENB_MARK,
4425};
4426
4427static const unsigned int vin5_clk_pins[] = {
4428 RCAR_GP_PIN(1, 21),
4429};
4430
4431static const unsigned int vin5_clk_mux[] = {
4432 VI5_CLK_MARK,
4433};
4434
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]4435static const struct {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame^]4436 struct sh_pfc_pin_group common[324];
Biju Das0a362702020-10-28 10:34:24 +0000[diff] [blame]4437#ifdef CONFIG_PINCTRL_PFC_R8A77965
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]4438 struct sh_pfc_pin_group automotive[30];
Biju Das0a362702020-10-28 10:34:24 +0000[diff] [blame]4439#endif
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]4440} pinmux_groups = {
4441 .common = {
4442 SH_PFC_PIN_GROUP(audio_clk_a_a),
4443 SH_PFC_PIN_GROUP(audio_clk_a_b),
4444 SH_PFC_PIN_GROUP(audio_clk_a_c),
4445 SH_PFC_PIN_GROUP(audio_clk_b_a),
4446 SH_PFC_PIN_GROUP(audio_clk_b_b),
4447 SH_PFC_PIN_GROUP(audio_clk_c_a),
4448 SH_PFC_PIN_GROUP(audio_clk_c_b),
4449 SH_PFC_PIN_GROUP(audio_clkout_a),
4450 SH_PFC_PIN_GROUP(audio_clkout_b),
4451 SH_PFC_PIN_GROUP(audio_clkout_c),
4452 SH_PFC_PIN_GROUP(audio_clkout_d),
4453 SH_PFC_PIN_GROUP(audio_clkout1_a),
4454 SH_PFC_PIN_GROUP(audio_clkout1_b),
4455 SH_PFC_PIN_GROUP(audio_clkout2_a),
4456 SH_PFC_PIN_GROUP(audio_clkout2_b),
4457 SH_PFC_PIN_GROUP(audio_clkout3_a),
4458 SH_PFC_PIN_GROUP(audio_clkout3_b),
4459 SH_PFC_PIN_GROUP(avb_link),
4460 SH_PFC_PIN_GROUP(avb_magic),
4461 SH_PFC_PIN_GROUP(avb_phy_int),
4462 SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
4463 SH_PFC_PIN_GROUP(avb_mdio),
4464 SH_PFC_PIN_GROUP(avb_mii),
4465 SH_PFC_PIN_GROUP(avb_avtp_pps),
4466 SH_PFC_PIN_GROUP(avb_avtp_match_a),
4467 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
4468 SH_PFC_PIN_GROUP(avb_avtp_match_b),
4469 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
4470 SH_PFC_PIN_GROUP(can0_data_a),
4471 SH_PFC_PIN_GROUP(can0_data_b),
4472 SH_PFC_PIN_GROUP(can1_data),
4473 SH_PFC_PIN_GROUP(can_clk),
4474 SH_PFC_PIN_GROUP(canfd0_data_a),
4475 SH_PFC_PIN_GROUP(canfd0_data_b),
4476 SH_PFC_PIN_GROUP(canfd1_data),
4477 SH_PFC_PIN_GROUP(du_rgb666),
4478 SH_PFC_PIN_GROUP(du_rgb888),
4479 SH_PFC_PIN_GROUP(du_clk_out_0),
4480 SH_PFC_PIN_GROUP(du_clk_out_1),
4481 SH_PFC_PIN_GROUP(du_sync),
4482 SH_PFC_PIN_GROUP(du_oddf),
4483 SH_PFC_PIN_GROUP(du_cde),
4484 SH_PFC_PIN_GROUP(du_disp),
4485 SH_PFC_PIN_GROUP(hscif0_data),
4486 SH_PFC_PIN_GROUP(hscif0_clk),
4487 SH_PFC_PIN_GROUP(hscif0_ctrl),
4488 SH_PFC_PIN_GROUP(hscif1_data_a),
4489 SH_PFC_PIN_GROUP(hscif1_clk_a),
4490 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
4491 SH_PFC_PIN_GROUP(hscif1_data_b),
4492 SH_PFC_PIN_GROUP(hscif1_clk_b),
4493 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
4494 SH_PFC_PIN_GROUP(hscif2_data_a),
4495 SH_PFC_PIN_GROUP(hscif2_clk_a),
4496 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
4497 SH_PFC_PIN_GROUP(hscif2_data_b),
4498 SH_PFC_PIN_GROUP(hscif2_clk_b),
4499 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4500 SH_PFC_PIN_GROUP(hscif2_data_c),
4501 SH_PFC_PIN_GROUP(hscif2_clk_c),
4502 SH_PFC_PIN_GROUP(hscif2_ctrl_c),
4503 SH_PFC_PIN_GROUP(hscif3_data_a),
4504 SH_PFC_PIN_GROUP(hscif3_clk),
4505 SH_PFC_PIN_GROUP(hscif3_ctrl),
4506 SH_PFC_PIN_GROUP(hscif3_data_b),
4507 SH_PFC_PIN_GROUP(hscif3_data_c),
4508 SH_PFC_PIN_GROUP(hscif3_data_d),
4509 SH_PFC_PIN_GROUP(hscif4_data_a),
4510 SH_PFC_PIN_GROUP(hscif4_clk),
4511 SH_PFC_PIN_GROUP(hscif4_ctrl),
4512 SH_PFC_PIN_GROUP(hscif4_data_b),
4513 SH_PFC_PIN_GROUP(i2c0),
4514 SH_PFC_PIN_GROUP(i2c1_a),
4515 SH_PFC_PIN_GROUP(i2c1_b),
4516 SH_PFC_PIN_GROUP(i2c2_a),
4517 SH_PFC_PIN_GROUP(i2c2_b),
4518 SH_PFC_PIN_GROUP(i2c3),
4519 SH_PFC_PIN_GROUP(i2c5),
4520 SH_PFC_PIN_GROUP(i2c6_a),
4521 SH_PFC_PIN_GROUP(i2c6_b),
4522 SH_PFC_PIN_GROUP(i2c6_c),
4523 SH_PFC_PIN_GROUP(intc_ex_irq0),
4524 SH_PFC_PIN_GROUP(intc_ex_irq1),
4525 SH_PFC_PIN_GROUP(intc_ex_irq2),
4526 SH_PFC_PIN_GROUP(intc_ex_irq3),
4527 SH_PFC_PIN_GROUP(intc_ex_irq4),
4528 SH_PFC_PIN_GROUP(intc_ex_irq5),
4529 SH_PFC_PIN_GROUP(msiof0_clk),
4530 SH_PFC_PIN_GROUP(msiof0_sync),
4531 SH_PFC_PIN_GROUP(msiof0_ss1),
4532 SH_PFC_PIN_GROUP(msiof0_ss2),
4533 SH_PFC_PIN_GROUP(msiof0_txd),
4534 SH_PFC_PIN_GROUP(msiof0_rxd),
4535 SH_PFC_PIN_GROUP(msiof1_clk_a),
4536 SH_PFC_PIN_GROUP(msiof1_sync_a),
4537 SH_PFC_PIN_GROUP(msiof1_ss1_a),
4538 SH_PFC_PIN_GROUP(msiof1_ss2_a),
4539 SH_PFC_PIN_GROUP(msiof1_txd_a),
4540 SH_PFC_PIN_GROUP(msiof1_rxd_a),
4541 SH_PFC_PIN_GROUP(msiof1_clk_b),
4542 SH_PFC_PIN_GROUP(msiof1_sync_b),
4543 SH_PFC_PIN_GROUP(msiof1_ss1_b),
4544 SH_PFC_PIN_GROUP(msiof1_ss2_b),
4545 SH_PFC_PIN_GROUP(msiof1_txd_b),
4546 SH_PFC_PIN_GROUP(msiof1_rxd_b),
4547 SH_PFC_PIN_GROUP(msiof1_clk_c),
4548 SH_PFC_PIN_GROUP(msiof1_sync_c),
4549 SH_PFC_PIN_GROUP(msiof1_ss1_c),
4550 SH_PFC_PIN_GROUP(msiof1_ss2_c),
4551 SH_PFC_PIN_GROUP(msiof1_txd_c),
4552 SH_PFC_PIN_GROUP(msiof1_rxd_c),
4553 SH_PFC_PIN_GROUP(msiof1_clk_d),
4554 SH_PFC_PIN_GROUP(msiof1_sync_d),
4555 SH_PFC_PIN_GROUP(msiof1_ss1_d),
4556 SH_PFC_PIN_GROUP(msiof1_ss2_d),
4557 SH_PFC_PIN_GROUP(msiof1_txd_d),
4558 SH_PFC_PIN_GROUP(msiof1_rxd_d),
4559 SH_PFC_PIN_GROUP(msiof1_clk_e),
4560 SH_PFC_PIN_GROUP(msiof1_sync_e),
4561 SH_PFC_PIN_GROUP(msiof1_ss1_e),
4562 SH_PFC_PIN_GROUP(msiof1_ss2_e),
4563 SH_PFC_PIN_GROUP(msiof1_txd_e),
4564 SH_PFC_PIN_GROUP(msiof1_rxd_e),
4565 SH_PFC_PIN_GROUP(msiof1_clk_f),
4566 SH_PFC_PIN_GROUP(msiof1_sync_f),
4567 SH_PFC_PIN_GROUP(msiof1_ss1_f),
4568 SH_PFC_PIN_GROUP(msiof1_ss2_f),
4569 SH_PFC_PIN_GROUP(msiof1_txd_f),
4570 SH_PFC_PIN_GROUP(msiof1_rxd_f),
4571 SH_PFC_PIN_GROUP(msiof1_clk_g),
4572 SH_PFC_PIN_GROUP(msiof1_sync_g),
4573 SH_PFC_PIN_GROUP(msiof1_ss1_g),
4574 SH_PFC_PIN_GROUP(msiof1_ss2_g),
4575 SH_PFC_PIN_GROUP(msiof1_txd_g),
4576 SH_PFC_PIN_GROUP(msiof1_rxd_g),
4577 SH_PFC_PIN_GROUP(msiof2_clk_a),
4578 SH_PFC_PIN_GROUP(msiof2_sync_a),
4579 SH_PFC_PIN_GROUP(msiof2_ss1_a),
4580 SH_PFC_PIN_GROUP(msiof2_ss2_a),
4581 SH_PFC_PIN_GROUP(msiof2_txd_a),
4582 SH_PFC_PIN_GROUP(msiof2_rxd_a),
4583 SH_PFC_PIN_GROUP(msiof2_clk_b),
4584 SH_PFC_PIN_GROUP(msiof2_sync_b),
4585 SH_PFC_PIN_GROUP(msiof2_ss1_b),
4586 SH_PFC_PIN_GROUP(msiof2_ss2_b),
4587 SH_PFC_PIN_GROUP(msiof2_txd_b),
4588 SH_PFC_PIN_GROUP(msiof2_rxd_b),
4589 SH_PFC_PIN_GROUP(msiof2_clk_c),
4590 SH_PFC_PIN_GROUP(msiof2_sync_c),
4591 SH_PFC_PIN_GROUP(msiof2_ss1_c),
4592 SH_PFC_PIN_GROUP(msiof2_ss2_c),
4593 SH_PFC_PIN_GROUP(msiof2_txd_c),
4594 SH_PFC_PIN_GROUP(msiof2_rxd_c),
4595 SH_PFC_PIN_GROUP(msiof2_clk_d),
4596 SH_PFC_PIN_GROUP(msiof2_sync_d),
4597 SH_PFC_PIN_GROUP(msiof2_ss1_d),
4598 SH_PFC_PIN_GROUP(msiof2_ss2_d),
4599 SH_PFC_PIN_GROUP(msiof2_txd_d),
4600 SH_PFC_PIN_GROUP(msiof2_rxd_d),
4601 SH_PFC_PIN_GROUP(msiof3_clk_a),
4602 SH_PFC_PIN_GROUP(msiof3_sync_a),
4603 SH_PFC_PIN_GROUP(msiof3_ss1_a),
4604 SH_PFC_PIN_GROUP(msiof3_ss2_a),
4605 SH_PFC_PIN_GROUP(msiof3_txd_a),
4606 SH_PFC_PIN_GROUP(msiof3_rxd_a),
4607 SH_PFC_PIN_GROUP(msiof3_clk_b),
4608 SH_PFC_PIN_GROUP(msiof3_sync_b),
4609 SH_PFC_PIN_GROUP(msiof3_ss1_b),
4610 SH_PFC_PIN_GROUP(msiof3_ss2_b),
4611 SH_PFC_PIN_GROUP(msiof3_txd_b),
4612 SH_PFC_PIN_GROUP(msiof3_rxd_b),
4613 SH_PFC_PIN_GROUP(msiof3_clk_c),
4614 SH_PFC_PIN_GROUP(msiof3_sync_c),
4615 SH_PFC_PIN_GROUP(msiof3_txd_c),
4616 SH_PFC_PIN_GROUP(msiof3_rxd_c),
4617 SH_PFC_PIN_GROUP(msiof3_clk_d),
4618 SH_PFC_PIN_GROUP(msiof3_sync_d),
4619 SH_PFC_PIN_GROUP(msiof3_ss1_d),
4620 SH_PFC_PIN_GROUP(msiof3_txd_d),
4621 SH_PFC_PIN_GROUP(msiof3_rxd_d),
4622 SH_PFC_PIN_GROUP(msiof3_clk_e),
4623 SH_PFC_PIN_GROUP(msiof3_sync_e),
4624 SH_PFC_PIN_GROUP(msiof3_ss1_e),
4625 SH_PFC_PIN_GROUP(msiof3_ss2_e),
4626 SH_PFC_PIN_GROUP(msiof3_txd_e),
4627 SH_PFC_PIN_GROUP(msiof3_rxd_e),
4628 SH_PFC_PIN_GROUP(pwm0),
4629 SH_PFC_PIN_GROUP(pwm1_a),
4630 SH_PFC_PIN_GROUP(pwm1_b),
4631 SH_PFC_PIN_GROUP(pwm2_a),
4632 SH_PFC_PIN_GROUP(pwm2_b),
4633 SH_PFC_PIN_GROUP(pwm3_a),
4634 SH_PFC_PIN_GROUP(pwm3_b),
4635 SH_PFC_PIN_GROUP(pwm4_a),
4636 SH_PFC_PIN_GROUP(pwm4_b),
4637 SH_PFC_PIN_GROUP(pwm5_a),
4638 SH_PFC_PIN_GROUP(pwm5_b),
4639 SH_PFC_PIN_GROUP(pwm6_a),
4640 SH_PFC_PIN_GROUP(pwm6_b),
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame^]4641 SH_PFC_PIN_GROUP(qspi0_ctrl),
4642 SH_PFC_PIN_GROUP(qspi0_data2),
4643 SH_PFC_PIN_GROUP(qspi0_data4),
4644 SH_PFC_PIN_GROUP(qspi1_ctrl),
4645 SH_PFC_PIN_GROUP(qspi1_data2),
4646 SH_PFC_PIN_GROUP(qspi1_data4),
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]4647 SH_PFC_PIN_GROUP(sata0_devslp_a),
4648 SH_PFC_PIN_GROUP(sata0_devslp_b),
4649 SH_PFC_PIN_GROUP(scif0_data),
4650 SH_PFC_PIN_GROUP(scif0_clk),
4651 SH_PFC_PIN_GROUP(scif0_ctrl),
4652 SH_PFC_PIN_GROUP(scif1_data_a),
4653 SH_PFC_PIN_GROUP(scif1_clk),
4654 SH_PFC_PIN_GROUP(scif1_ctrl),
4655 SH_PFC_PIN_GROUP(scif1_data_b),
4656 SH_PFC_PIN_GROUP(scif2_data_a),
4657 SH_PFC_PIN_GROUP(scif2_clk),
4658 SH_PFC_PIN_GROUP(scif2_data_b),
4659 SH_PFC_PIN_GROUP(scif3_data_a),
4660 SH_PFC_PIN_GROUP(scif3_clk),
4661 SH_PFC_PIN_GROUP(scif3_ctrl),
4662 SH_PFC_PIN_GROUP(scif3_data_b),
4663 SH_PFC_PIN_GROUP(scif4_data_a),
4664 SH_PFC_PIN_GROUP(scif4_clk_a),
4665 SH_PFC_PIN_GROUP(scif4_ctrl_a),
4666 SH_PFC_PIN_GROUP(scif4_data_b),
4667 SH_PFC_PIN_GROUP(scif4_clk_b),
4668 SH_PFC_PIN_GROUP(scif4_ctrl_b),
4669 SH_PFC_PIN_GROUP(scif4_data_c),
4670 SH_PFC_PIN_GROUP(scif4_clk_c),
4671 SH_PFC_PIN_GROUP(scif4_ctrl_c),
4672 SH_PFC_PIN_GROUP(scif5_data_a),
4673 SH_PFC_PIN_GROUP(scif5_clk_a),
4674 SH_PFC_PIN_GROUP(scif5_data_b),
4675 SH_PFC_PIN_GROUP(scif5_clk_b),
4676 SH_PFC_PIN_GROUP(scif_clk_a),
4677 SH_PFC_PIN_GROUP(scif_clk_b),
4678 SH_PFC_PIN_GROUP(sdhi0_data1),
4679 SH_PFC_PIN_GROUP(sdhi0_data4),
4680 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4681 SH_PFC_PIN_GROUP(sdhi0_cd),
4682 SH_PFC_PIN_GROUP(sdhi0_wp),
4683 SH_PFC_PIN_GROUP(sdhi1_data1),
4684 SH_PFC_PIN_GROUP(sdhi1_data4),
4685 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4686 SH_PFC_PIN_GROUP(sdhi1_cd),
4687 SH_PFC_PIN_GROUP(sdhi1_wp),
4688 SH_PFC_PIN_GROUP(sdhi2_data1),
4689 SH_PFC_PIN_GROUP(sdhi2_data4),
4690 SH_PFC_PIN_GROUP(sdhi2_data8),
4691 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4692 SH_PFC_PIN_GROUP(sdhi2_cd_a),
4693 SH_PFC_PIN_GROUP(sdhi2_wp_a),
4694 SH_PFC_PIN_GROUP(sdhi2_cd_b),
4695 SH_PFC_PIN_GROUP(sdhi2_wp_b),
4696 SH_PFC_PIN_GROUP(sdhi2_ds),
4697 SH_PFC_PIN_GROUP(sdhi3_data1),
4698 SH_PFC_PIN_GROUP(sdhi3_data4),
4699 SH_PFC_PIN_GROUP(sdhi3_data8),
4700 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4701 SH_PFC_PIN_GROUP(sdhi3_cd),
4702 SH_PFC_PIN_GROUP(sdhi3_wp),
4703 SH_PFC_PIN_GROUP(sdhi3_ds),
4704 SH_PFC_PIN_GROUP(ssi0_data),
4705 SH_PFC_PIN_GROUP(ssi01239_ctrl),
4706 SH_PFC_PIN_GROUP(ssi1_data_a),
4707 SH_PFC_PIN_GROUP(ssi1_data_b),
4708 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4709 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4710 SH_PFC_PIN_GROUP(ssi2_data_a),
4711 SH_PFC_PIN_GROUP(ssi2_data_b),
4712 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4713 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4714 SH_PFC_PIN_GROUP(ssi3_data),
4715 SH_PFC_PIN_GROUP(ssi349_ctrl),
4716 SH_PFC_PIN_GROUP(ssi4_data),
4717 SH_PFC_PIN_GROUP(ssi4_ctrl),
4718 SH_PFC_PIN_GROUP(ssi5_data),
4719 SH_PFC_PIN_GROUP(ssi5_ctrl),
4720 SH_PFC_PIN_GROUP(ssi6_data),
4721 SH_PFC_PIN_GROUP(ssi6_ctrl),
4722 SH_PFC_PIN_GROUP(ssi7_data),
4723 SH_PFC_PIN_GROUP(ssi78_ctrl),
4724 SH_PFC_PIN_GROUP(ssi8_data),
4725 SH_PFC_PIN_GROUP(ssi9_data_a),
4726 SH_PFC_PIN_GROUP(ssi9_data_b),
4727 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4728 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4729 SH_PFC_PIN_GROUP(tmu_tclk1_a),
4730 SH_PFC_PIN_GROUP(tmu_tclk1_b),
4731 SH_PFC_PIN_GROUP(tmu_tclk2_a),
4732 SH_PFC_PIN_GROUP(tmu_tclk2_b),
4733 SH_PFC_PIN_GROUP(tpu_to0),
4734 SH_PFC_PIN_GROUP(tpu_to1),
4735 SH_PFC_PIN_GROUP(tpu_to2),
4736 SH_PFC_PIN_GROUP(tpu_to3),
4737 SH_PFC_PIN_GROUP(usb0),
4738 SH_PFC_PIN_GROUP(usb1),
4739 SH_PFC_PIN_GROUP(usb30),
4740 VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
4741 VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
4742 VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
4743 VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
4744 SH_PFC_PIN_GROUP(vin4_data18_a),
4745 VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
4746 VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
4747 VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
4748 VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
4749 VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
4750 VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
4751 SH_PFC_PIN_GROUP(vin4_data18_b),
4752 VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
4753 VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
4754 SH_PFC_PIN_GROUP(vin4_sync),
4755 SH_PFC_PIN_GROUP(vin4_field),
4756 SH_PFC_PIN_GROUP(vin4_clkenb),
4757 SH_PFC_PIN_GROUP(vin4_clk),
4758 VIN_DATA_PIN_GROUP(vin5_data, 8),
4759 VIN_DATA_PIN_GROUP(vin5_data, 10),
4760 VIN_DATA_PIN_GROUP(vin5_data, 12),
4761 VIN_DATA_PIN_GROUP(vin5_data, 16),
4762 SH_PFC_PIN_GROUP(vin5_sync),
4763 SH_PFC_PIN_GROUP(vin5_field),
4764 SH_PFC_PIN_GROUP(vin5_clkenb),
4765 SH_PFC_PIN_GROUP(vin5_clk),
4766 },
Biju Das0a362702020-10-28 10:34:24 +0000[diff] [blame]4767#ifdef CONFIG_PINCTRL_PFC_R8A77965
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]4768 .automotive = {
4769 SH_PFC_PIN_GROUP(drif0_ctrl_a),
4770 SH_PFC_PIN_GROUP(drif0_data0_a),
4771 SH_PFC_PIN_GROUP(drif0_data1_a),
4772 SH_PFC_PIN_GROUP(drif0_ctrl_b),
4773 SH_PFC_PIN_GROUP(drif0_data0_b),
4774 SH_PFC_PIN_GROUP(drif0_data1_b),
4775 SH_PFC_PIN_GROUP(drif0_ctrl_c),
4776 SH_PFC_PIN_GROUP(drif0_data0_c),
4777 SH_PFC_PIN_GROUP(drif0_data1_c),
4778 SH_PFC_PIN_GROUP(drif1_ctrl_a),
4779 SH_PFC_PIN_GROUP(drif1_data0_a),
4780 SH_PFC_PIN_GROUP(drif1_data1_a),
4781 SH_PFC_PIN_GROUP(drif1_ctrl_b),
4782 SH_PFC_PIN_GROUP(drif1_data0_b),
4783 SH_PFC_PIN_GROUP(drif1_data1_b),
4784 SH_PFC_PIN_GROUP(drif1_ctrl_c),
4785 SH_PFC_PIN_GROUP(drif1_data0_c),
4786 SH_PFC_PIN_GROUP(drif1_data1_c),
4787 SH_PFC_PIN_GROUP(drif2_ctrl_a),
4788 SH_PFC_PIN_GROUP(drif2_data0_a),
4789 SH_PFC_PIN_GROUP(drif2_data1_a),
4790 SH_PFC_PIN_GROUP(drif2_ctrl_b),
4791 SH_PFC_PIN_GROUP(drif2_data0_b),
4792 SH_PFC_PIN_GROUP(drif2_data1_b),
4793 SH_PFC_PIN_GROUP(drif3_ctrl_a),
4794 SH_PFC_PIN_GROUP(drif3_data0_a),
4795 SH_PFC_PIN_GROUP(drif3_data1_a),
4796 SH_PFC_PIN_GROUP(drif3_ctrl_b),
4797 SH_PFC_PIN_GROUP(drif3_data0_b),
4798 SH_PFC_PIN_GROUP(drif3_data1_b),
4799 }
Biju Das0a362702020-10-28 10:34:24 +0000[diff] [blame]4800#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4801};
4802
4803static const char * const audio_clk_groups[] = {
4804 "audio_clk_a_a",
4805 "audio_clk_a_b",
4806 "audio_clk_a_c",
4807 "audio_clk_b_a",
4808 "audio_clk_b_b",
4809 "audio_clk_c_a",
4810 "audio_clk_c_b",
4811 "audio_clkout_a",
4812 "audio_clkout_b",
4813 "audio_clkout_c",
4814 "audio_clkout_d",
4815 "audio_clkout1_a",
4816 "audio_clkout1_b",
4817 "audio_clkout2_a",
4818 "audio_clkout2_b",
4819 "audio_clkout3_a",
4820 "audio_clkout3_b",
4821};
4822
4823static const char * const avb_groups[] = {
4824 "avb_link",
4825 "avb_magic",
4826 "avb_phy_int",
4827 "avb_mdc", /* Deprecated, please use "avb_mdio" instead */
4828 "avb_mdio",
4829 "avb_mii",
4830 "avb_avtp_pps",
4831 "avb_avtp_match_a",
4832 "avb_avtp_capture_a",
4833 "avb_avtp_match_b",
4834 "avb_avtp_capture_b",
4835};
4836
4837static const char * const can0_groups[] = {
4838 "can0_data_a",
4839 "can0_data_b",
4840};
4841
4842static const char * const can1_groups[] = {
4843 "can1_data",
4844};
4845
4846static const char * const can_clk_groups[] = {
4847 "can_clk",
4848};
4849
4850static const char * const canfd0_groups[] = {
4851 "canfd0_data_a",
4852 "canfd0_data_b",
4853};
4854
4855static const char * const canfd1_groups[] = {
4856 "canfd1_data",
4857};
4858
Biju Das0a362702020-10-28 10:34:24 +0000[diff] [blame]4859#ifdef CONFIG_PINCTRL_PFC_R8A77965
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4860static const char * const drif0_groups[] = {
4861 "drif0_ctrl_a",
4862 "drif0_data0_a",
4863 "drif0_data1_a",
4864 "drif0_ctrl_b",
4865 "drif0_data0_b",
4866 "drif0_data1_b",
4867 "drif0_ctrl_c",
4868 "drif0_data0_c",
4869 "drif0_data1_c",
4870};
4871
4872static const char * const drif1_groups[] = {
4873 "drif1_ctrl_a",
4874 "drif1_data0_a",
4875 "drif1_data1_a",
4876 "drif1_ctrl_b",
4877 "drif1_data0_b",
4878 "drif1_data1_b",
4879 "drif1_ctrl_c",
4880 "drif1_data0_c",
4881 "drif1_data1_c",
4882};
4883
4884static const char * const drif2_groups[] = {
4885 "drif2_ctrl_a",
4886 "drif2_data0_a",
4887 "drif2_data1_a",
4888 "drif2_ctrl_b",
4889 "drif2_data0_b",
4890 "drif2_data1_b",
4891};
4892
4893static const char * const drif3_groups[] = {
4894 "drif3_ctrl_a",
4895 "drif3_data0_a",
4896 "drif3_data1_a",
4897 "drif3_ctrl_b",
4898 "drif3_data0_b",
4899 "drif3_data1_b",
4900};
Biju Das0a362702020-10-28 10:34:24 +0000[diff] [blame]4901#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4902
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4903static const char * const du_groups[] = {
4904 "du_rgb666",
4905 "du_rgb888",
4906 "du_clk_out_0",
4907 "du_clk_out_1",
4908 "du_sync",
4909 "du_oddf",
4910 "du_cde",
4911 "du_disp",
4912};
4913
4914static const char * const hscif0_groups[] = {
4915 "hscif0_data",
4916 "hscif0_clk",
4917 "hscif0_ctrl",
4918};
4919
4920static const char * const hscif1_groups[] = {
4921 "hscif1_data_a",
4922 "hscif1_clk_a",
4923 "hscif1_ctrl_a",
4924 "hscif1_data_b",
4925 "hscif1_clk_b",
4926 "hscif1_ctrl_b",
4927};
4928
4929static const char * const hscif2_groups[] = {
4930 "hscif2_data_a",
4931 "hscif2_clk_a",
4932 "hscif2_ctrl_a",
4933 "hscif2_data_b",
4934 "hscif2_clk_b",
4935 "hscif2_ctrl_b",
4936 "hscif2_data_c",
4937 "hscif2_clk_c",
4938 "hscif2_ctrl_c",
4939};
4940
4941static const char * const hscif3_groups[] = {
4942 "hscif3_data_a",
4943 "hscif3_clk",
4944 "hscif3_ctrl",
4945 "hscif3_data_b",
4946 "hscif3_data_c",
4947 "hscif3_data_d",
4948};
4949
4950static const char * const hscif4_groups[] = {
4951 "hscif4_data_a",
4952 "hscif4_clk",
4953 "hscif4_ctrl",
4954 "hscif4_data_b",
4955};
4956
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]4957static const char * const i2c0_groups[] = {
4958 "i2c0",
4959};
4960
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4961static const char * const i2c1_groups[] = {
4962 "i2c1_a",
4963 "i2c1_b",
4964};
4965
4966static const char * const i2c2_groups[] = {
4967 "i2c2_a",
4968 "i2c2_b",
4969};
4970
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]4971static const char * const i2c3_groups[] = {
4972 "i2c3",
4973};
4974
4975static const char * const i2c5_groups[] = {
4976 "i2c5",
4977};
4978
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4979static const char * const i2c6_groups[] = {
4980 "i2c6_a",
4981 "i2c6_b",
4982 "i2c6_c",
4983};
4984
4985static const char * const intc_ex_groups[] = {
4986 "intc_ex_irq0",
4987 "intc_ex_irq1",
4988 "intc_ex_irq2",
4989 "intc_ex_irq3",
4990 "intc_ex_irq4",
4991 "intc_ex_irq5",
4992};
4993
4994static const char * const msiof0_groups[] = {
4995 "msiof0_clk",
4996 "msiof0_sync",
4997 "msiof0_ss1",
4998 "msiof0_ss2",
4999 "msiof0_txd",
5000 "msiof0_rxd",
5001};
5002
5003static const char * const msiof1_groups[] = {
5004 "msiof1_clk_a",
5005 "msiof1_sync_a",
5006 "msiof1_ss1_a",
5007 "msiof1_ss2_a",
5008 "msiof1_txd_a",
5009 "msiof1_rxd_a",
5010 "msiof1_clk_b",
5011 "msiof1_sync_b",
5012 "msiof1_ss1_b",
5013 "msiof1_ss2_b",
5014 "msiof1_txd_b",
5015 "msiof1_rxd_b",
5016 "msiof1_clk_c",
5017 "msiof1_sync_c",
5018 "msiof1_ss1_c",
5019 "msiof1_ss2_c",
5020 "msiof1_txd_c",
5021 "msiof1_rxd_c",
5022 "msiof1_clk_d",
5023 "msiof1_sync_d",
5024 "msiof1_ss1_d",
5025 "msiof1_ss2_d",
5026 "msiof1_txd_d",
5027 "msiof1_rxd_d",
5028 "msiof1_clk_e",
5029 "msiof1_sync_e",
5030 "msiof1_ss1_e",
5031 "msiof1_ss2_e",
5032 "msiof1_txd_e",
5033 "msiof1_rxd_e",
5034 "msiof1_clk_f",
5035 "msiof1_sync_f",
5036 "msiof1_ss1_f",
5037 "msiof1_ss2_f",
5038 "msiof1_txd_f",
5039 "msiof1_rxd_f",
5040 "msiof1_clk_g",
5041 "msiof1_sync_g",
5042 "msiof1_ss1_g",
5043 "msiof1_ss2_g",
5044 "msiof1_txd_g",
5045 "msiof1_rxd_g",
5046};
5047
5048static const char * const msiof2_groups[] = {
5049 "msiof2_clk_a",
5050 "msiof2_sync_a",
5051 "msiof2_ss1_a",
5052 "msiof2_ss2_a",
5053 "msiof2_txd_a",
5054 "msiof2_rxd_a",
5055 "msiof2_clk_b",
5056 "msiof2_sync_b",
5057 "msiof2_ss1_b",
5058 "msiof2_ss2_b",
5059 "msiof2_txd_b",
5060 "msiof2_rxd_b",
5061 "msiof2_clk_c",
5062 "msiof2_sync_c",
5063 "msiof2_ss1_c",
5064 "msiof2_ss2_c",
5065 "msiof2_txd_c",
5066 "msiof2_rxd_c",
5067 "msiof2_clk_d",
5068 "msiof2_sync_d",
5069 "msiof2_ss1_d",
5070 "msiof2_ss2_d",
5071 "msiof2_txd_d",
5072 "msiof2_rxd_d",
5073};
5074
5075static const char * const msiof3_groups[] = {
5076 "msiof3_clk_a",
5077 "msiof3_sync_a",
5078 "msiof3_ss1_a",
5079 "msiof3_ss2_a",
5080 "msiof3_txd_a",
5081 "msiof3_rxd_a",
5082 "msiof3_clk_b",
5083 "msiof3_sync_b",
5084 "msiof3_ss1_b",
5085 "msiof3_ss2_b",
5086 "msiof3_txd_b",
5087 "msiof3_rxd_b",
5088 "msiof3_clk_c",
5089 "msiof3_sync_c",
5090 "msiof3_txd_c",
5091 "msiof3_rxd_c",
5092 "msiof3_clk_d",
5093 "msiof3_sync_d",
5094 "msiof3_ss1_d",
5095 "msiof3_txd_d",
5096 "msiof3_rxd_d",
5097 "msiof3_clk_e",
5098 "msiof3_sync_e",
5099 "msiof3_ss1_e",
5100 "msiof3_ss2_e",
5101 "msiof3_txd_e",
5102 "msiof3_rxd_e",
5103};
5104
5105static const char * const pwm0_groups[] = {
5106 "pwm0",
5107};
5108
5109static const char * const pwm1_groups[] = {
5110 "pwm1_a",
5111 "pwm1_b",
5112};
5113
5114static const char * const pwm2_groups[] = {
5115 "pwm2_a",
5116 "pwm2_b",
5117};
5118
5119static const char * const pwm3_groups[] = {
5120 "pwm3_a",
5121 "pwm3_b",
5122};
5123
5124static const char * const pwm4_groups[] = {
5125 "pwm4_a",
5126 "pwm4_b",
5127};
5128
5129static const char * const pwm5_groups[] = {
5130 "pwm5_a",
5131 "pwm5_b",
5132};
5133
5134static const char * const pwm6_groups[] = {
5135 "pwm6_a",
5136 "pwm6_b",
5137};
5138
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame^]5139static const char * const qspi0_groups[] = {
5140 "qspi0_ctrl",
5141 "qspi0_data2",
5142 "qspi0_data4",
5143};
5144
5145static const char * const qspi1_groups[] = {
5146 "qspi1_ctrl",
5147 "qspi1_data2",
5148 "qspi1_data4",
5149};
5150
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5151static const char * const sata0_groups[] = {
5152 "sata0_devslp_a",
5153 "sata0_devslp_b",
5154};
5155
5156static const char * const scif0_groups[] = {
5157 "scif0_data",
5158 "scif0_clk",
5159 "scif0_ctrl",
5160};
5161
5162static const char * const scif1_groups[] = {
5163 "scif1_data_a",
5164 "scif1_clk",
5165 "scif1_ctrl",
5166 "scif1_data_b",
5167};
5168static const char * const scif2_groups[] = {
5169 "scif2_data_a",
5170 "scif2_clk",
5171 "scif2_data_b",
5172};
5173
5174static const char * const scif3_groups[] = {
5175 "scif3_data_a",
5176 "scif3_clk",
5177 "scif3_ctrl",
5178 "scif3_data_b",
5179};
5180
5181static const char * const scif4_groups[] = {
5182 "scif4_data_a",
5183 "scif4_clk_a",
5184 "scif4_ctrl_a",
5185 "scif4_data_b",
5186 "scif4_clk_b",
5187 "scif4_ctrl_b",
5188 "scif4_data_c",
5189 "scif4_clk_c",
5190 "scif4_ctrl_c",
5191};
5192
5193static const char * const scif5_groups[] = {
5194 "scif5_data_a",
5195 "scif5_clk_a",
5196 "scif5_data_b",
5197 "scif5_clk_b",
5198};
5199
5200static const char * const scif_clk_groups[] = {
5201 "scif_clk_a",
5202 "scif_clk_b",
5203};
5204
5205static const char * const sdhi0_groups[] = {
5206 "sdhi0_data1",
5207 "sdhi0_data4",
5208 "sdhi0_ctrl",
5209 "sdhi0_cd",
5210 "sdhi0_wp",
5211};
5212
5213static const char * const sdhi1_groups[] = {
5214 "sdhi1_data1",
5215 "sdhi1_data4",
5216 "sdhi1_ctrl",
5217 "sdhi1_cd",
5218 "sdhi1_wp",
5219};
5220
5221static const char * const sdhi2_groups[] = {
5222 "sdhi2_data1",
5223 "sdhi2_data4",
5224 "sdhi2_data8",
5225 "sdhi2_ctrl",
5226 "sdhi2_cd_a",
5227 "sdhi2_wp_a",
5228 "sdhi2_cd_b",
5229 "sdhi2_wp_b",
5230 "sdhi2_ds",
5231};
5232
5233static const char * const sdhi3_groups[] = {
5234 "sdhi3_data1",
5235 "sdhi3_data4",
5236 "sdhi3_data8",
5237 "sdhi3_ctrl",
5238 "sdhi3_cd",
5239 "sdhi3_wp",
5240 "sdhi3_ds",
5241};
5242
5243static const char * const ssi_groups[] = {
5244 "ssi0_data",
5245 "ssi01239_ctrl",
5246 "ssi1_data_a",
5247 "ssi1_data_b",
5248 "ssi1_ctrl_a",
5249 "ssi1_ctrl_b",
5250 "ssi2_data_a",
5251 "ssi2_data_b",
5252 "ssi2_ctrl_a",
5253 "ssi2_ctrl_b",
5254 "ssi3_data",
5255 "ssi349_ctrl",
5256 "ssi4_data",
5257 "ssi4_ctrl",
5258 "ssi5_data",
5259 "ssi5_ctrl",
5260 "ssi6_data",
5261 "ssi6_ctrl",
5262 "ssi7_data",
5263 "ssi78_ctrl",
5264 "ssi8_data",
5265 "ssi9_data_a",
5266 "ssi9_data_b",
5267 "ssi9_ctrl_a",
5268 "ssi9_ctrl_b",
5269};
5270
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]5271static const char * const tmu_groups[] = {
5272 "tmu_tclk1_a",
5273 "tmu_tclk1_b",
5274 "tmu_tclk2_a",
5275 "tmu_tclk2_b",
5276};
5277
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]5278static const char * const tpu_groups[] = {
5279 "tpu_to0",
5280 "tpu_to1",
5281 "tpu_to2",
5282 "tpu_to3",
5283};
5284
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5285static const char * const usb0_groups[] = {
5286 "usb0",
5287};
5288
5289static const char * const usb1_groups[] = {
5290 "usb1",
5291};
5292
5293static const char * const usb30_groups[] = {
5294 "usb30",
5295};
5296
5297static const char * const vin4_groups[] = {
5298 "vin4_data8_a",
5299 "vin4_data10_a",
5300 "vin4_data12_a",
5301 "vin4_data16_a",
5302 "vin4_data18_a",
5303 "vin4_data20_a",
5304 "vin4_data24_a",
5305 "vin4_data8_b",
5306 "vin4_data10_b",
5307 "vin4_data12_b",
5308 "vin4_data16_b",
5309 "vin4_data18_b",
5310 "vin4_data20_b",
5311 "vin4_data24_b",
5312 "vin4_sync",
5313 "vin4_field",
5314 "vin4_clkenb",
5315 "vin4_clk",
5316};
5317
5318static const char * const vin5_groups[] = {
5319 "vin5_data8",
5320 "vin5_data10",
5321 "vin5_data12",
5322 "vin5_data16",
5323 "vin5_sync",
5324 "vin5_field",
5325 "vin5_clkenb",
5326 "vin5_clk",
5327};
5328
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]5329static const struct {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame^]5330 struct sh_pfc_function common[53];
Biju Das0a362702020-10-28 10:34:24 +0000[diff] [blame]5331#ifdef CONFIG_PINCTRL_PFC_R8A77965
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]5332 struct sh_pfc_function automotive[4];
Biju Das0a362702020-10-28 10:34:24 +0000[diff] [blame]5333#endif
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]5334} pinmux_functions = {
5335 .common = {
5336 SH_PFC_FUNCTION(audio_clk),
5337 SH_PFC_FUNCTION(avb),
5338 SH_PFC_FUNCTION(can0),
5339 SH_PFC_FUNCTION(can1),
5340 SH_PFC_FUNCTION(can_clk),
5341 SH_PFC_FUNCTION(canfd0),
5342 SH_PFC_FUNCTION(canfd1),
5343 SH_PFC_FUNCTION(du),
5344 SH_PFC_FUNCTION(hscif0),
5345 SH_PFC_FUNCTION(hscif1),
5346 SH_PFC_FUNCTION(hscif2),
5347 SH_PFC_FUNCTION(hscif3),
5348 SH_PFC_FUNCTION(hscif4),
5349 SH_PFC_FUNCTION(i2c0),
5350 SH_PFC_FUNCTION(i2c1),
5351 SH_PFC_FUNCTION(i2c2),
5352 SH_PFC_FUNCTION(i2c3),
5353 SH_PFC_FUNCTION(i2c5),
5354 SH_PFC_FUNCTION(i2c6),
5355 SH_PFC_FUNCTION(intc_ex),
5356 SH_PFC_FUNCTION(msiof0),
5357 SH_PFC_FUNCTION(msiof1),
5358 SH_PFC_FUNCTION(msiof2),
5359 SH_PFC_FUNCTION(msiof3),
5360 SH_PFC_FUNCTION(pwm0),
5361 SH_PFC_FUNCTION(pwm1),
5362 SH_PFC_FUNCTION(pwm2),
5363 SH_PFC_FUNCTION(pwm3),
5364 SH_PFC_FUNCTION(pwm4),
5365 SH_PFC_FUNCTION(pwm5),
5366 SH_PFC_FUNCTION(pwm6),
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame^]5367 SH_PFC_FUNCTION(qspi0),
5368 SH_PFC_FUNCTION(qspi1),
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]5369 SH_PFC_FUNCTION(sata0),
5370 SH_PFC_FUNCTION(scif0),
5371 SH_PFC_FUNCTION(scif1),
5372 SH_PFC_FUNCTION(scif2),
5373 SH_PFC_FUNCTION(scif3),
5374 SH_PFC_FUNCTION(scif4),
5375 SH_PFC_FUNCTION(scif5),
5376 SH_PFC_FUNCTION(scif_clk),
5377 SH_PFC_FUNCTION(sdhi0),
5378 SH_PFC_FUNCTION(sdhi1),
5379 SH_PFC_FUNCTION(sdhi2),
5380 SH_PFC_FUNCTION(sdhi3),
5381 SH_PFC_FUNCTION(ssi),
5382 SH_PFC_FUNCTION(tmu),
5383 SH_PFC_FUNCTION(tpu),
5384 SH_PFC_FUNCTION(usb0),
5385 SH_PFC_FUNCTION(usb1),
5386 SH_PFC_FUNCTION(usb30),
5387 SH_PFC_FUNCTION(vin4),
5388 SH_PFC_FUNCTION(vin5),
5389 },
Biju Das0a362702020-10-28 10:34:24 +0000[diff] [blame]5390#ifdef CONFIG_PINCTRL_PFC_R8A77965
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]5391 .automotive = {
5392 SH_PFC_FUNCTION(drif0),
5393 SH_PFC_FUNCTION(drif1),
5394 SH_PFC_FUNCTION(drif2),
5395 SH_PFC_FUNCTION(drif3),
5396 }
Biju Das0a362702020-10-28 10:34:24 +0000[diff] [blame]5397#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5398};
5399
5400static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5401#define F_(x, y) FN_##y
5402#define FM(x) FN_##x
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5403 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5404 0, 0,
5405 0, 0,
5406 0, 0,
5407 0, 0,
5408 0, 0,
5409 0, 0,
5410 0, 0,
5411 0, 0,
5412 0, 0,
5413 0, 0,
5414 0, 0,
5415 0, 0,
5416 0, 0,
5417 0, 0,
5418 0, 0,
5419 0, 0,
5420 GP_0_15_FN, GPSR0_15,
5421 GP_0_14_FN, GPSR0_14,
5422 GP_0_13_FN, GPSR0_13,
5423 GP_0_12_FN, GPSR0_12,
5424 GP_0_11_FN, GPSR0_11,
5425 GP_0_10_FN, GPSR0_10,
5426 GP_0_9_FN, GPSR0_9,
5427 GP_0_8_FN, GPSR0_8,
5428 GP_0_7_FN, GPSR0_7,
5429 GP_0_6_FN, GPSR0_6,
5430 GP_0_5_FN, GPSR0_5,
5431 GP_0_4_FN, GPSR0_4,
5432 GP_0_3_FN, GPSR0_3,
5433 GP_0_2_FN, GPSR0_2,
5434 GP_0_1_FN, GPSR0_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5435 GP_0_0_FN, GPSR0_0, ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5436 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5437 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5438 0, 0,
5439 0, 0,
5440 0, 0,
5441 GP_1_28_FN, GPSR1_28,
5442 GP_1_27_FN, GPSR1_27,
5443 GP_1_26_FN, GPSR1_26,
5444 GP_1_25_FN, GPSR1_25,
5445 GP_1_24_FN, GPSR1_24,
5446 GP_1_23_FN, GPSR1_23,
5447 GP_1_22_FN, GPSR1_22,
5448 GP_1_21_FN, GPSR1_21,
5449 GP_1_20_FN, GPSR1_20,
5450 GP_1_19_FN, GPSR1_19,
5451 GP_1_18_FN, GPSR1_18,
5452 GP_1_17_FN, GPSR1_17,
5453 GP_1_16_FN, GPSR1_16,
5454 GP_1_15_FN, GPSR1_15,
5455 GP_1_14_FN, GPSR1_14,
5456 GP_1_13_FN, GPSR1_13,
5457 GP_1_12_FN, GPSR1_12,
5458 GP_1_11_FN, GPSR1_11,
5459 GP_1_10_FN, GPSR1_10,
5460 GP_1_9_FN, GPSR1_9,
5461 GP_1_8_FN, GPSR1_8,
5462 GP_1_7_FN, GPSR1_7,
5463 GP_1_6_FN, GPSR1_6,
5464 GP_1_5_FN, GPSR1_5,
5465 GP_1_4_FN, GPSR1_4,
5466 GP_1_3_FN, GPSR1_3,
5467 GP_1_2_FN, GPSR1_2,
5468 GP_1_1_FN, GPSR1_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5469 GP_1_0_FN, GPSR1_0, ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5470 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5471 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5472 0, 0,
5473 0, 0,
5474 0, 0,
5475 0, 0,
5476 0, 0,
5477 0, 0,
5478 0, 0,
5479 0, 0,
5480 0, 0,
5481 0, 0,
5482 0, 0,
5483 0, 0,
5484 0, 0,
5485 0, 0,
5486 0, 0,
5487 0, 0,
5488 0, 0,
5489 GP_2_14_FN, GPSR2_14,
5490 GP_2_13_FN, GPSR2_13,
5491 GP_2_12_FN, GPSR2_12,
5492 GP_2_11_FN, GPSR2_11,
5493 GP_2_10_FN, GPSR2_10,
5494 GP_2_9_FN, GPSR2_9,
5495 GP_2_8_FN, GPSR2_8,
5496 GP_2_7_FN, GPSR2_7,
5497 GP_2_6_FN, GPSR2_6,
5498 GP_2_5_FN, GPSR2_5,
5499 GP_2_4_FN, GPSR2_4,
5500 GP_2_3_FN, GPSR2_3,
5501 GP_2_2_FN, GPSR2_2,
5502 GP_2_1_FN, GPSR2_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5503 GP_2_0_FN, GPSR2_0, ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5504 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5505 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5506 0, 0,
5507 0, 0,
5508 0, 0,
5509 0, 0,
5510 0, 0,
5511 0, 0,
5512 0, 0,
5513 0, 0,
5514 0, 0,
5515 0, 0,
5516 0, 0,
5517 0, 0,
5518 0, 0,
5519 0, 0,
5520 0, 0,
5521 0, 0,
5522 GP_3_15_FN, GPSR3_15,
5523 GP_3_14_FN, GPSR3_14,
5524 GP_3_13_FN, GPSR3_13,
5525 GP_3_12_FN, GPSR3_12,
5526 GP_3_11_FN, GPSR3_11,
5527 GP_3_10_FN, GPSR3_10,
5528 GP_3_9_FN, GPSR3_9,
5529 GP_3_8_FN, GPSR3_8,
5530 GP_3_7_FN, GPSR3_7,
5531 GP_3_6_FN, GPSR3_6,
5532 GP_3_5_FN, GPSR3_5,
5533 GP_3_4_FN, GPSR3_4,
5534 GP_3_3_FN, GPSR3_3,
5535 GP_3_2_FN, GPSR3_2,
5536 GP_3_1_FN, GPSR3_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5537 GP_3_0_FN, GPSR3_0, ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5538 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5539 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5540 0, 0,
5541 0, 0,
5542 0, 0,
5543 0, 0,
5544 0, 0,
5545 0, 0,
5546 0, 0,
5547 0, 0,
5548 0, 0,
5549 0, 0,
5550 0, 0,
5551 0, 0,
5552 0, 0,
5553 0, 0,
5554 GP_4_17_FN, GPSR4_17,
5555 GP_4_16_FN, GPSR4_16,
5556 GP_4_15_FN, GPSR4_15,
5557 GP_4_14_FN, GPSR4_14,
5558 GP_4_13_FN, GPSR4_13,
5559 GP_4_12_FN, GPSR4_12,
5560 GP_4_11_FN, GPSR4_11,
5561 GP_4_10_FN, GPSR4_10,
5562 GP_4_9_FN, GPSR4_9,
5563 GP_4_8_FN, GPSR4_8,
5564 GP_4_7_FN, GPSR4_7,
5565 GP_4_6_FN, GPSR4_6,
5566 GP_4_5_FN, GPSR4_5,
5567 GP_4_4_FN, GPSR4_4,
5568 GP_4_3_FN, GPSR4_3,
5569 GP_4_2_FN, GPSR4_2,
5570 GP_4_1_FN, GPSR4_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5571 GP_4_0_FN, GPSR4_0, ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5572 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5573 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5574 0, 0,
5575 0, 0,
5576 0, 0,
5577 0, 0,
5578 0, 0,
5579 0, 0,
5580 GP_5_25_FN, GPSR5_25,
5581 GP_5_24_FN, GPSR5_24,
5582 GP_5_23_FN, GPSR5_23,
5583 GP_5_22_FN, GPSR5_22,
5584 GP_5_21_FN, GPSR5_21,
5585 GP_5_20_FN, GPSR5_20,
5586 GP_5_19_FN, GPSR5_19,
5587 GP_5_18_FN, GPSR5_18,
5588 GP_5_17_FN, GPSR5_17,
5589 GP_5_16_FN, GPSR5_16,
5590 GP_5_15_FN, GPSR5_15,
5591 GP_5_14_FN, GPSR5_14,
5592 GP_5_13_FN, GPSR5_13,
5593 GP_5_12_FN, GPSR5_12,
5594 GP_5_11_FN, GPSR5_11,
5595 GP_5_10_FN, GPSR5_10,
5596 GP_5_9_FN, GPSR5_9,
5597 GP_5_8_FN, GPSR5_8,
5598 GP_5_7_FN, GPSR5_7,
5599 GP_5_6_FN, GPSR5_6,
5600 GP_5_5_FN, GPSR5_5,
5601 GP_5_4_FN, GPSR5_4,
5602 GP_5_3_FN, GPSR5_3,
5603 GP_5_2_FN, GPSR5_2,
5604 GP_5_1_FN, GPSR5_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5605 GP_5_0_FN, GPSR5_0, ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5606 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5607 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5608 GP_6_31_FN, GPSR6_31,
5609 GP_6_30_FN, GPSR6_30,
5610 GP_6_29_FN, GPSR6_29,
5611 GP_6_28_FN, GPSR6_28,
5612 GP_6_27_FN, GPSR6_27,
5613 GP_6_26_FN, GPSR6_26,
5614 GP_6_25_FN, GPSR6_25,
5615 GP_6_24_FN, GPSR6_24,
5616 GP_6_23_FN, GPSR6_23,
5617 GP_6_22_FN, GPSR6_22,
5618 GP_6_21_FN, GPSR6_21,
5619 GP_6_20_FN, GPSR6_20,
5620 GP_6_19_FN, GPSR6_19,
5621 GP_6_18_FN, GPSR6_18,
5622 GP_6_17_FN, GPSR6_17,
5623 GP_6_16_FN, GPSR6_16,
5624 GP_6_15_FN, GPSR6_15,
5625 GP_6_14_FN, GPSR6_14,
5626 GP_6_13_FN, GPSR6_13,
5627 GP_6_12_FN, GPSR6_12,
5628 GP_6_11_FN, GPSR6_11,
5629 GP_6_10_FN, GPSR6_10,
5630 GP_6_9_FN, GPSR6_9,
5631 GP_6_8_FN, GPSR6_8,
5632 GP_6_7_FN, GPSR6_7,
5633 GP_6_6_FN, GPSR6_6,
5634 GP_6_5_FN, GPSR6_5,
5635 GP_6_4_FN, GPSR6_4,
5636 GP_6_3_FN, GPSR6_3,
5637 GP_6_2_FN, GPSR6_2,
5638 GP_6_1_FN, GPSR6_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5639 GP_6_0_FN, GPSR6_0, ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5640 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5641 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5642 0, 0,
5643 0, 0,
5644 0, 0,
5645 0, 0,
5646 0, 0,
5647 0, 0,
5648 0, 0,
5649 0, 0,
5650 0, 0,
5651 0, 0,
5652 0, 0,
5653 0, 0,
5654 0, 0,
5655 0, 0,
5656 0, 0,
5657 0, 0,
5658 0, 0,
5659 0, 0,
5660 0, 0,
5661 0, 0,
5662 0, 0,
5663 0, 0,
5664 0, 0,
5665 0, 0,
5666 0, 0,
5667 0, 0,
5668 0, 0,
5669 0, 0,
5670 GP_7_3_FN, GPSR7_3,
5671 GP_7_2_FN, GPSR7_2,
5672 GP_7_1_FN, GPSR7_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5673 GP_7_0_FN, GPSR7_0, ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5674 },
5675#undef F_
5676#undef FM
5677
5678#define F_(x, y) x,
5679#define FM(x) FN_##x,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5680 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5681 IP0_31_28
5682 IP0_27_24
5683 IP0_23_20
5684 IP0_19_16
5685 IP0_15_12
5686 IP0_11_8
5687 IP0_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5688 IP0_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5689 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5690 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5691 IP1_31_28
5692 IP1_27_24
5693 IP1_23_20
5694 IP1_19_16
5695 IP1_15_12
5696 IP1_11_8
5697 IP1_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5698 IP1_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5699 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5700 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5701 IP2_31_28
5702 IP2_27_24
5703 IP2_23_20
5704 IP2_19_16
5705 IP2_15_12
5706 IP2_11_8
5707 IP2_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5708 IP2_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5709 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5710 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5711 IP3_31_28
5712 IP3_27_24
5713 IP3_23_20
5714 IP3_19_16
5715 IP3_15_12
5716 IP3_11_8
5717 IP3_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5718 IP3_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5719 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5720 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5721 IP4_31_28
5722 IP4_27_24
5723 IP4_23_20
5724 IP4_19_16
5725 IP4_15_12
5726 IP4_11_8
5727 IP4_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5728 IP4_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5729 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5730 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5731 IP5_31_28
5732 IP5_27_24
5733 IP5_23_20
5734 IP5_19_16
5735 IP5_15_12
5736 IP5_11_8
5737 IP5_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5738 IP5_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5739 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5740 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5741 IP6_31_28
5742 IP6_27_24
5743 IP6_23_20
5744 IP6_19_16
5745 IP6_15_12
5746 IP6_11_8
5747 IP6_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5748 IP6_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5749 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5750 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5751 IP7_31_28
5752 IP7_27_24
5753 IP7_23_20
5754 IP7_19_16
5755 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5756 IP7_11_8
5757 IP7_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5758 IP7_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5759 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5760 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5761 IP8_31_28
5762 IP8_27_24
5763 IP8_23_20
5764 IP8_19_16
5765 IP8_15_12
5766 IP8_11_8
5767 IP8_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5768 IP8_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5769 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5770 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5771 IP9_31_28
5772 IP9_27_24
5773 IP9_23_20
5774 IP9_19_16
5775 IP9_15_12
5776 IP9_11_8
5777 IP9_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5778 IP9_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5779 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5780 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5781 IP10_31_28
5782 IP10_27_24
5783 IP10_23_20
5784 IP10_19_16
5785 IP10_15_12
5786 IP10_11_8
5787 IP10_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5788 IP10_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5789 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5790 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5791 IP11_31_28
5792 IP11_27_24
5793 IP11_23_20
5794 IP11_19_16
5795 IP11_15_12
5796 IP11_11_8
5797 IP11_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5798 IP11_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5799 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5800 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5801 IP12_31_28
5802 IP12_27_24
5803 IP12_23_20
5804 IP12_19_16
5805 IP12_15_12
5806 IP12_11_8
5807 IP12_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5808 IP12_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5809 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5810 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5811 IP13_31_28
5812 IP13_27_24
5813 IP13_23_20
5814 IP13_19_16
5815 IP13_15_12
5816 IP13_11_8
5817 IP13_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5818 IP13_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5819 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5820 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5821 IP14_31_28
5822 IP14_27_24
5823 IP14_23_20
5824 IP14_19_16
5825 IP14_15_12
5826 IP14_11_8
5827 IP14_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5828 IP14_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5829 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5830 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5831 IP15_31_28
5832 IP15_27_24
5833 IP15_23_20
5834 IP15_19_16
5835 IP15_15_12
5836 IP15_11_8
5837 IP15_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5838 IP15_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5839 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5840 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5841 IP16_31_28
5842 IP16_27_24
5843 IP16_23_20
5844 IP16_19_16
5845 IP16_15_12
5846 IP16_11_8
5847 IP16_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5848 IP16_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5849 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5850 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5851 IP17_31_28
5852 IP17_27_24
5853 IP17_23_20
5854 IP17_19_16
5855 IP17_15_12
5856 IP17_11_8
5857 IP17_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5858 IP17_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5859 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5860 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5861 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5862 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5863 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5864 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5865 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5866 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5867 IP18_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5868 IP18_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5869 },
5870#undef F_
5871#undef FM
5872
5873#define F_(x, y) x,
5874#define FM(x) FN_##x,
5875 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5876 GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2,
5877 1, 1, 1, 2, 2, 1, 2, 3),
5878 GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5879 MOD_SEL0_31_30_29
5880 MOD_SEL0_28_27
5881 MOD_SEL0_26_25_24
5882 MOD_SEL0_23
5883 MOD_SEL0_22
5884 MOD_SEL0_21
5885 MOD_SEL0_20
5886 MOD_SEL0_19
5887 MOD_SEL0_18_17
5888 MOD_SEL0_16
5889 0, 0, /* RESERVED 15 */
5890 MOD_SEL0_14_13
5891 MOD_SEL0_12
5892 MOD_SEL0_11
5893 MOD_SEL0_10
5894 MOD_SEL0_9_8
5895 MOD_SEL0_7_6
5896 MOD_SEL0_5
5897 MOD_SEL0_4_3
5898 /* RESERVED 2, 1, 0 */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5899 0, 0, 0, 0, 0, 0, 0, 0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5900 },
5901 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5902 GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
5903 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
5904 GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5905 MOD_SEL1_31_30
5906 MOD_SEL1_29_28_27
5907 MOD_SEL1_26
5908 MOD_SEL1_25_24
5909 MOD_SEL1_23_22_21
5910 MOD_SEL1_20
5911 MOD_SEL1_19
5912 MOD_SEL1_18_17
5913 MOD_SEL1_16
5914 MOD_SEL1_15_14
5915 MOD_SEL1_13
5916 MOD_SEL1_12
5917 MOD_SEL1_11
5918 MOD_SEL1_10
5919 MOD_SEL1_9
5920 0, 0, 0, 0, /* RESERVED 8, 7 */
5921 MOD_SEL1_6
5922 MOD_SEL1_5
5923 MOD_SEL1_4
5924 MOD_SEL1_3
5925 MOD_SEL1_2
5926 MOD_SEL1_1
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5927 MOD_SEL1_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5928 },
5929 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5930 GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
5931 1, 4, 4, 4, 3, 1),
5932 GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5933 MOD_SEL2_31
5934 MOD_SEL2_30
5935 MOD_SEL2_29
5936 MOD_SEL2_28_27
5937 MOD_SEL2_26
5938 MOD_SEL2_25_24_23
5939 MOD_SEL2_22
5940 MOD_SEL2_21
5941 MOD_SEL2_20
5942 MOD_SEL2_19
5943 MOD_SEL2_18
5944 MOD_SEL2_17
5945 /* RESERVED 16 */
5946 0, 0,
5947 /* RESERVED 15, 14, 13, 12 */
5948 0, 0, 0, 0, 0, 0, 0, 0,
5949 0, 0, 0, 0, 0, 0, 0, 0,
5950 /* RESERVED 11, 10, 9, 8 */
5951 0, 0, 0, 0, 0, 0, 0, 0,
5952 0, 0, 0, 0, 0, 0, 0, 0,
5953 /* RESERVED 7, 6, 5, 4 */
5954 0, 0, 0, 0, 0, 0, 0, 0,
5955 0, 0, 0, 0, 0, 0, 0, 0,
5956 /* RESERVED 3, 2, 1 */
5957 0, 0, 0, 0, 0, 0, 0, 0,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5958 MOD_SEL2_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5959 },
5960 { },
5961};
5962
5963static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5964 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame^]5965 { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */
5966 { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */
5967 { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */
5968 { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */
5969 { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */
5970 { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */
5971 { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */
5972 { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5973 } },
5974 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame^]5975 { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */
5976 { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */
5977 { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */
5978 { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */
5979 { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */
5980 { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */
5981 { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */
5982 { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5983 } },
5984 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame^]5985 { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
5986 { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */
5987 { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */
5988 { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */
5989 { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */
5990 { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */
5991 { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */
5992 { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5993 } },
5994 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame^]5995 { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */
5996 { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */
5997 { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */
5998 { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */
5999 { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */
6000 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
6001 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
6002 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6003 } },
6004 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
6005 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
6006 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
6007 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
6008 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
6009 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
6010 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
6011 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
6012 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
6013 } },
6014 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
6015 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
6016 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
6017 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
6018 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
6019 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
6020 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
6021 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
6022 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
6023 } },
6024 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
6025 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
6026 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
6027 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
6028 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
6029 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
6030 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
6031 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
6032 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
6033 } },
6034 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
6035 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
6036 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
6037 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
6038 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
6039 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
6040 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
6041 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
6042 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
6043 } },
6044 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
6045 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
6046 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
6047 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
6048 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
6049 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
6050 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
6051 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
6052 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
6053 } },
6054 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
6055 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame^]6056 { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6057 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
6058 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
6059 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
6060 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
6061 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
6062 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
6063 } },
6064 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
6065 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
6066 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
6067 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
6068 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
6069 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
6070 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
6071 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
6072 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
6073 } },
6074 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame^]6075 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
6076 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
6077 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
6078 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
6079 { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
6080 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
6081 { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */
6082 { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6083 } },
6084 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame^]6085 { PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */
6086 { PIN_FSCLKST, 20, 2 }, /* FSCLKST */
6087 { PIN_TMS, 4, 2 }, /* TMS */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6088 } },
6089 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame^]6090 { PIN_TDO, 28, 2 }, /* TDO */
6091 { PIN_ASEBRK, 24, 2 }, /* ASEBRK */
6092 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
6093 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
6094 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
6095 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
6096 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
6097 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6098 } },
6099 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
6100 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
6101 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
6102 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
6103 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
6104 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
6105 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
6106 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
6107 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
6108 } },
6109 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
6110 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
6111 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
6112 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
6113 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
6114 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
6115 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
6116 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
6117 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
6118 } },
6119 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
6120 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
6121 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
6122 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
6123 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
6124 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
6125 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
6126 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
6127 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
6128 } },
6129 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
6130 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
6131 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
6132 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
6133 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
6134 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
6135 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
6136 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
6137 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
6138 } },
6139 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
6140 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
6141 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
6142 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
6143 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
6144 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
6145 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
6146 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
6147 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
6148 } },
6149 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
6150 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
6151 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
6152 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
6153 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
6154 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
6155 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
6156 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
6157 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
6158 } },
6159 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
6160 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
6161 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
6162 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
6163 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
6164 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
6165 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame^]6166 { PIN_MLB_REF, 4, 3 }, /* MLB_REF */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6167 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
6168 } },
6169 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
6170 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
6171 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
6172 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
6173 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
6174 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
6175 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
6176 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
6177 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
6178 } },
6179 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
6180 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
6181 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
6182 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
6183 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
6184 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
6185 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
6186 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
6187 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
6188 } },
6189 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
6190 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
6191 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
6192 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
6193 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
6194 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
6195 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
6196 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
6197 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
6198 } },
6199 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
6200 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
6201 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
6202 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
6203 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
6204 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
6205 { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30 */
6206 { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31 */
6207 } },
6208 { },
6209};
6210
6211enum ioctrl_regs {
6212 POCCTRL,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]6213 TDSELCTRL,
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6214};
6215
6216static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
6217 [POCCTRL] = { 0xe6060380, },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]6218 [TDSELCTRL] = { 0xe60603c0, },
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6219 { /* sentinel */ },
6220};
6221
6222static int r8a77965_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
6223{
6224 int bit = -EINVAL;
6225
6226 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
6227
6228 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
6229 bit = pin & 0x1f;
6230
6231 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
6232 bit = (pin & 0x1f) + 12;
6233
6234 return bit;
6235}
6236
6237static const struct pinmux_bias_reg pinmux_bias_regs[] = {
6238 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame^]6239 [ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */
6240 [ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */
6241 [ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */
6242 [ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */
6243 [ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */
6244 [ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */
6245 [ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */
6246 [ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */
6247 [ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */
6248 [ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */
6249 [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */
6250 [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */
6251 [12] = PIN_RPC_INT_N, /* RPC_INT# */
6252 [13] = PIN_RPC_WP_N, /* RPC_WP# */
6253 [14] = PIN_RPC_RESET_N, /* RPC_RESET# */
6254 [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */
6255 [16] = PIN_AVB_RXC, /* AVB_RXC */
6256 [17] = PIN_AVB_RD0, /* AVB_RD0 */
6257 [18] = PIN_AVB_RD1, /* AVB_RD1 */
6258 [19] = PIN_AVB_RD2, /* AVB_RD2 */
6259 [20] = PIN_AVB_RD3, /* AVB_RD3 */
6260 [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */
6261 [22] = PIN_AVB_TXC, /* AVB_TXC */
6262 [23] = PIN_AVB_TD0, /* AVB_TD0 */
6263 [24] = PIN_AVB_TD1, /* AVB_TD1 */
6264 [25] = PIN_AVB_TD2, /* AVB_TD2 */
6265 [26] = PIN_AVB_TD3, /* AVB_TD3 */
6266 [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */
6267 [28] = PIN_AVB_MDIO, /* AVB_MDIO */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6268 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
6269 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
6270 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
6271 } },
6272 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
6273 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
6274 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
6275 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
6276 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
6277 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
6278 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
6279 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
6280 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
6281 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
6282 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
6283 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
6284 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
6285 [12] = RCAR_GP_PIN(1, 0), /* A0 */
6286 [13] = RCAR_GP_PIN(1, 1), /* A1 */
6287 [14] = RCAR_GP_PIN(1, 2), /* A2 */
6288 [15] = RCAR_GP_PIN(1, 3), /* A3 */
6289 [16] = RCAR_GP_PIN(1, 4), /* A4 */
6290 [17] = RCAR_GP_PIN(1, 5), /* A5 */
6291 [18] = RCAR_GP_PIN(1, 6), /* A6 */
6292 [19] = RCAR_GP_PIN(1, 7), /* A7 */
6293 [20] = RCAR_GP_PIN(1, 8), /* A8 */
6294 [21] = RCAR_GP_PIN(1, 9), /* A9 */
6295 [22] = RCAR_GP_PIN(1, 10), /* A10 */
6296 [23] = RCAR_GP_PIN(1, 11), /* A11 */
6297 [24] = RCAR_GP_PIN(1, 12), /* A12 */
6298 [25] = RCAR_GP_PIN(1, 13), /* A13 */
6299 [26] = RCAR_GP_PIN(1, 14), /* A14 */
6300 [27] = RCAR_GP_PIN(1, 15), /* A15 */
6301 [28] = RCAR_GP_PIN(1, 16), /* A16 */
6302 [29] = RCAR_GP_PIN(1, 17), /* A17 */
6303 [30] = RCAR_GP_PIN(1, 18), /* A18 */
6304 [31] = RCAR_GP_PIN(1, 19), /* A19 */
6305 } },
6306 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
6307 [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */
6308 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
6309 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */
6310 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
6311 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
6312 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
6313 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
6314 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
6315 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame^]6316 [ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6317 [10] = RCAR_GP_PIN(0, 0), /* D0 */
6318 [11] = RCAR_GP_PIN(0, 1), /* D1 */
6319 [12] = RCAR_GP_PIN(0, 2), /* D2 */
6320 [13] = RCAR_GP_PIN(0, 3), /* D3 */
6321 [14] = RCAR_GP_PIN(0, 4), /* D4 */
6322 [15] = RCAR_GP_PIN(0, 5), /* D5 */
6323 [16] = RCAR_GP_PIN(0, 6), /* D6 */
6324 [17] = RCAR_GP_PIN(0, 7), /* D7 */
6325 [18] = RCAR_GP_PIN(0, 8), /* D8 */
6326 [19] = RCAR_GP_PIN(0, 9), /* D9 */
6327 [20] = RCAR_GP_PIN(0, 10), /* D10 */
6328 [21] = RCAR_GP_PIN(0, 11), /* D11 */
6329 [22] = RCAR_GP_PIN(0, 12), /* D12 */
6330 [23] = RCAR_GP_PIN(0, 13), /* D13 */
6331 [24] = RCAR_GP_PIN(0, 14), /* D14 */
6332 [25] = RCAR_GP_PIN(0, 15), /* D15 */
6333 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
6334 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]6335 [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6336 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame^]6337 [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */
6338 [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6339 } },
6340 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame^]6341 [ 0] = SH_PFC_PIN_NONE,
6342 [ 1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */
6343 [ 2] = PIN_FSCLKST, /* FSCLKST */
6344 [ 3] = PIN_EXTALR, /* EXTALR*/
6345 [ 4] = PIN_TRST_N, /* TRST# */
6346 [ 5] = PIN_TCK, /* TCK */
6347 [ 6] = PIN_TMS, /* TMS */
6348 [ 7] = PIN_TDI, /* TDI */
6349 [ 8] = SH_PFC_PIN_NONE,
6350 [ 9] = PIN_ASEBRK, /* ASEBRK */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6351 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
6352 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
6353 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
6354 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
6355 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
6356 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
6357 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
6358 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
6359 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
6360 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
6361 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
6362 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
6363 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
6364 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
6365 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
6366 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
6367 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
6368 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
6369 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
6370 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
6371 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
6372 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
6373 } },
6374 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
6375 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
6376 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
6377 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
6378 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
6379 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
6380 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
6381 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
6382 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
6383 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
6384 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
6385 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
6386 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
6387 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
6388 [13] = RCAR_GP_PIN(5, 1), /* RX0 */
6389 [14] = RCAR_GP_PIN(5, 2), /* TX0 */
6390 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
6391 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
6392 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
6393 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
6394 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
6395 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
6396 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
6397 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
6398 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
6399 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
6400 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */
6401 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */
6402 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
6403 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
6404 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
6405 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
6406 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
6407 } },
6408 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
6409 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
6410 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
6411 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
6412 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
6413 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
6414 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame^]6415 [ 6] = PIN_MLB_REF, /* MLB_REF */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6416 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
6417 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
6418 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
6419 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
6420 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
6421 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
6422 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
6423 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
6424 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
6425 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
6426 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
6427 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
6428 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
6429 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
6430 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
6431 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
6432 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
6433 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
6434 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
6435 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
6436 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
6437 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
6438 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
6439 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
6440 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
6441 } },
6442 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
6443 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
6444 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
6445 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
6446 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
6447 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
6448 [ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */
6449 [ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */
Marek Vasut0e8e9892021-04-26 22:04:11 +0200[diff] [blame^]6450 [ 7] = SH_PFC_PIN_NONE,
6451 [ 8] = SH_PFC_PIN_NONE,
6452 [ 9] = SH_PFC_PIN_NONE,
6453 [10] = SH_PFC_PIN_NONE,
6454 [11] = SH_PFC_PIN_NONE,
6455 [12] = SH_PFC_PIN_NONE,
6456 [13] = SH_PFC_PIN_NONE,
6457 [14] = SH_PFC_PIN_NONE,
6458 [15] = SH_PFC_PIN_NONE,
6459 [16] = SH_PFC_PIN_NONE,
6460 [17] = SH_PFC_PIN_NONE,
6461 [18] = SH_PFC_PIN_NONE,
6462 [19] = SH_PFC_PIN_NONE,
6463 [20] = SH_PFC_PIN_NONE,
6464 [21] = SH_PFC_PIN_NONE,
6465 [22] = SH_PFC_PIN_NONE,
6466 [23] = SH_PFC_PIN_NONE,
6467 [24] = SH_PFC_PIN_NONE,
6468 [25] = SH_PFC_PIN_NONE,
6469 [26] = SH_PFC_PIN_NONE,
6470 [27] = SH_PFC_PIN_NONE,
6471 [28] = SH_PFC_PIN_NONE,
6472 [29] = SH_PFC_PIN_NONE,
6473 [30] = SH_PFC_PIN_NONE,
6474 [31] = SH_PFC_PIN_NONE,
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6475 } },
6476 { /* sentinel */ },
6477};
6478
6479static unsigned int r8a77965_pinmux_get_bias(struct sh_pfc *pfc,
6480 unsigned int pin)
6481{
6482 const struct pinmux_bias_reg *reg;
6483 unsigned int bit;
6484
6485 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
6486 if (!reg)
6487 return PIN_CONFIG_BIAS_DISABLE;
6488
6489 if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
6490 return PIN_CONFIG_BIAS_DISABLE;
6491 else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
6492 return PIN_CONFIG_BIAS_PULL_UP;
6493 else
6494 return PIN_CONFIG_BIAS_PULL_DOWN;
6495}
6496
6497static void r8a77965_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
6498 unsigned int bias)
6499{
6500 const struct pinmux_bias_reg *reg;
6501 u32 enable, updown;
6502 unsigned int bit;
6503
6504 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
6505 if (!reg)
6506 return;
6507
6508 enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
6509 if (bias != PIN_CONFIG_BIAS_DISABLE)
6510 enable |= BIT(bit);
6511
6512 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
6513 if (bias == PIN_CONFIG_BIAS_PULL_UP)
6514 updown |= BIT(bit);
6515
6516 sh_pfc_write(pfc, reg->pud, updown);
6517 sh_pfc_write(pfc, reg->puen, enable);
6518}
6519
6520static const struct sh_pfc_soc_operations r8a77965_pinmux_ops = {
6521 .pin_to_pocctrl = r8a77965_pin_to_pocctrl,
6522 .get_bias = r8a77965_pinmux_get_bias,
6523 .set_bias = r8a77965_pinmux_set_bias,
6524};
6525
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]6526#ifdef CONFIG_PINCTRL_PFC_R8A774B1
6527const struct sh_pfc_soc_info r8a774b1_pinmux_info = {
6528 .name = "r8a774b1_pfc",
6529 .ops = &r8a77965_pinmux_ops,
6530 .unlock_reg = 0xe6060000, /* PMMR */
6531
6532 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6533
6534 .pins = pinmux_pins,
6535 .nr_pins = ARRAY_SIZE(pinmux_pins),
6536 .groups = pinmux_groups.common,
6537 .nr_groups = ARRAY_SIZE(pinmux_groups.common),
6538 .functions = pinmux_functions.common,
6539 .nr_functions = ARRAY_SIZE(pinmux_functions.common),
6540
6541 .cfg_regs = pinmux_config_regs,
6542 .drive_regs = pinmux_drive_regs,
6543 .bias_regs = pinmux_bias_regs,
6544 .ioctrl_regs = pinmux_ioctrl_regs,
6545
6546 .pinmux_data = pinmux_data,
6547 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6548};
6549#endif
6550
6551#ifdef CONFIG_PINCTRL_PFC_R8A77965
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6552const struct sh_pfc_soc_info r8a77965_pinmux_info = {
6553 .name = "r8a77965_pfc",
6554 .ops = &r8a77965_pinmux_ops,
6555 .unlock_reg = 0xe6060000, /* PMMR */
6556
6557 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6558
6559 .pins = pinmux_pins,
6560 .nr_pins = ARRAY_SIZE(pinmux_pins),
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]6561 .groups = pinmux_groups.common,
6562 .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6563 ARRAY_SIZE(pinmux_groups.automotive),
6564 .functions = pinmux_functions.common,
6565 .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6566 ARRAY_SIZE(pinmux_functions.automotive),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6567
6568 .cfg_regs = pinmux_config_regs,
6569 .drive_regs = pinmux_drive_regs,
6570 .bias_regs = pinmux_bias_regs,
6571 .ioctrl_regs = pinmux_ioctrl_regs,
6572
6573 .pinmux_data = pinmux_data,
6574 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6575};
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]6576#endif