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git01.mediatek.com / filogic / uboot / 0a36270bb0ed9caf990730acfac29478db4332b8 / . / drivers / pinctrl / renesas / pfc-r8a77965.c
blob: d143750c2dd47724048802646ebd9b9b237e4324 [file] [log] [blame]
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * R8A77965 processor support - PFC hardware block.
4 *
5 * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]6 * Copyright (C) 2016-2019 Renesas Electronics Corp.
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]7 *
8 * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
9 *
10 * R-Car Gen3 processor support - PFC hardware block.
11 *
12 * Copyright (C) 2015 Renesas Electronics Corporation
13 */
14
15#include <common.h>
16#include <dm.h>
17#include <errno.h>
18#include <dm/pinctrl.h>
19#include <linux/kernel.h>
20
21#include "sh_pfc.h"
22
23#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
24 SH_PFC_PIN_CFG_PULL_UP | \
25 SH_PFC_PIN_CFG_PULL_DOWN)
26
27#define CPU_ALL_PORT(fn, sfx) \
28 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
31 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
32 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
34 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
35 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
36 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
37 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
38 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
39 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
40/*
41 * F_() : just information
42 * FM() : macro for FN_xxx / xxx_MARK
43 */
44
45/* GPSR0 */
46#define GPSR0_15 F_(D15, IP7_11_8)
47#define GPSR0_14 F_(D14, IP7_7_4)
48#define GPSR0_13 F_(D13, IP7_3_0)
49#define GPSR0_12 F_(D12, IP6_31_28)
50#define GPSR0_11 F_(D11, IP6_27_24)
51#define GPSR0_10 F_(D10, IP6_23_20)
52#define GPSR0_9 F_(D9, IP6_19_16)
53#define GPSR0_8 F_(D8, IP6_15_12)
54#define GPSR0_7 F_(D7, IP6_11_8)
55#define GPSR0_6 F_(D6, IP6_7_4)
56#define GPSR0_5 F_(D5, IP6_3_0)
57#define GPSR0_4 F_(D4, IP5_31_28)
58#define GPSR0_3 F_(D3, IP5_27_24)
59#define GPSR0_2 F_(D2, IP5_23_20)
60#define GPSR0_1 F_(D1, IP5_19_16)
61#define GPSR0_0 F_(D0, IP5_15_12)
62
63/* GPSR1 */
64#define GPSR1_28 FM(CLKOUT)
65#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
66#define GPSR1_26 F_(WE1_N, IP5_7_4)
67#define GPSR1_25 F_(WE0_N, IP5_3_0)
68#define GPSR1_24 F_(RD_WR_N, IP4_31_28)
69#define GPSR1_23 F_(RD_N, IP4_27_24)
70#define GPSR1_22 F_(BS_N, IP4_23_20)
71#define GPSR1_21 F_(CS1_N, IP4_19_16)
72#define GPSR1_20 F_(CS0_N, IP4_15_12)
73#define GPSR1_19 F_(A19, IP4_11_8)
74#define GPSR1_18 F_(A18, IP4_7_4)
75#define GPSR1_17 F_(A17, IP4_3_0)
76#define GPSR1_16 F_(A16, IP3_31_28)
77#define GPSR1_15 F_(A15, IP3_27_24)
78#define GPSR1_14 F_(A14, IP3_23_20)
79#define GPSR1_13 F_(A13, IP3_19_16)
80#define GPSR1_12 F_(A12, IP3_15_12)
81#define GPSR1_11 F_(A11, IP3_11_8)
82#define GPSR1_10 F_(A10, IP3_7_4)
83#define GPSR1_9 F_(A9, IP3_3_0)
84#define GPSR1_8 F_(A8, IP2_31_28)
85#define GPSR1_7 F_(A7, IP2_27_24)
86#define GPSR1_6 F_(A6, IP2_23_20)
87#define GPSR1_5 F_(A5, IP2_19_16)
88#define GPSR1_4 F_(A4, IP2_15_12)
89#define GPSR1_3 F_(A3, IP2_11_8)
90#define GPSR1_2 F_(A2, IP2_7_4)
91#define GPSR1_1 F_(A1, IP2_3_0)
92#define GPSR1_0 F_(A0, IP1_31_28)
93
94/* GPSR2 */
95#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
96#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
97#define GPSR2_12 F_(AVB_LINK, IP0_15_12)
98#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
99#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
100#define GPSR2_9 F_(AVB_MDC, IP0_3_0)
101#define GPSR2_8 F_(PWM2_A, IP1_27_24)
102#define GPSR2_7 F_(PWM1_A, IP1_23_20)
103#define GPSR2_6 F_(PWM0, IP1_19_16)
104#define GPSR2_5 F_(IRQ5, IP1_15_12)
105#define GPSR2_4 F_(IRQ4, IP1_11_8)
106#define GPSR2_3 F_(IRQ3, IP1_7_4)
107#define GPSR2_2 F_(IRQ2, IP1_3_0)
108#define GPSR2_1 F_(IRQ1, IP0_31_28)
109#define GPSR2_0 F_(IRQ0, IP0_27_24)
110
111/* GPSR3 */
112#define GPSR3_15 F_(SD1_WP, IP11_23_20)
113#define GPSR3_14 F_(SD1_CD, IP11_19_16)
114#define GPSR3_13 F_(SD0_WP, IP11_15_12)
115#define GPSR3_12 F_(SD0_CD, IP11_11_8)
116#define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
117#define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
118#define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
119#define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
120#define GPSR3_7 F_(SD1_CMD, IP8_15_12)
121#define GPSR3_6 F_(SD1_CLK, IP8_11_8)
122#define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
123#define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
124#define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
125#define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
126#define GPSR3_1 F_(SD0_CMD, IP7_23_20)
127#define GPSR3_0 F_(SD0_CLK, IP7_19_16)
128
129/* GPSR4 */
130#define GPSR4_17 F_(SD3_DS, IP11_7_4)
131#define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
132#define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
133#define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
134#define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
135#define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
136#define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
137#define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
138#define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
139#define GPSR4_8 F_(SD3_CMD, IP10_3_0)
140#define GPSR4_7 F_(SD3_CLK, IP9_31_28)
141#define GPSR4_6 F_(SD2_DS, IP9_27_24)
142#define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
143#define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
144#define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
145#define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
146#define GPSR4_1 F_(SD2_CMD, IP9_7_4)
147#define GPSR4_0 F_(SD2_CLK, IP9_3_0)
148
149/* GPSR5 */
150#define GPSR5_25 F_(MLB_DAT, IP14_19_16)
151#define GPSR5_24 F_(MLB_SIG, IP14_15_12)
152#define GPSR5_23 F_(MLB_CLK, IP14_11_8)
153#define GPSR5_22 FM(MSIOF0_RXD)
154#define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
155#define GPSR5_20 FM(MSIOF0_TXD)
156#define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
157#define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
158#define GPSR5_17 FM(MSIOF0_SCK)
159#define GPSR5_16 F_(HRTS0_N, IP13_27_24)
160#define GPSR5_15 F_(HCTS0_N, IP13_23_20)
161#define GPSR5_14 F_(HTX0, IP13_19_16)
162#define GPSR5_13 F_(HRX0, IP13_15_12)
163#define GPSR5_12 F_(HSCK0, IP13_11_8)
164#define GPSR5_11 F_(RX2_A, IP13_7_4)
165#define GPSR5_10 F_(TX2_A, IP13_3_0)
166#define GPSR5_9 F_(SCK2, IP12_31_28)
167#define GPSR5_8 F_(RTS1_N, IP12_27_24)
168#define GPSR5_7 F_(CTS1_N, IP12_23_20)
169#define GPSR5_6 F_(TX1_A, IP12_19_16)
170#define GPSR5_5 F_(RX1_A, IP12_15_12)
171#define GPSR5_4 F_(RTS0_N, IP12_11_8)
172#define GPSR5_3 F_(CTS0_N, IP12_7_4)
173#define GPSR5_2 F_(TX0, IP12_3_0)
174#define GPSR5_1 F_(RX0, IP11_31_28)
175#define GPSR5_0 F_(SCK0, IP11_27_24)
176
177/* GPSR6 */
178#define GPSR6_31 F_(GP6_31, IP18_7_4)
179#define GPSR6_30 F_(GP6_30, IP18_3_0)
180#define GPSR6_29 F_(USB30_OVC, IP17_31_28)
181#define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
182#define GPSR6_27 F_(USB1_OVC, IP17_23_20)
183#define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
184#define GPSR6_25 F_(USB0_OVC, IP17_15_12)
185#define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
186#define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
187#define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
188#define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
189#define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
190#define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
191#define GPSR6_18 F_(SSI_WS78, IP16_19_16)
192#define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
193#define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
194#define GPSR6_15 F_(SSI_WS6, IP16_7_4)
195#define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
196#define GPSR6_13 FM(SSI_SDATA5)
197#define GPSR6_12 FM(SSI_WS5)
198#define GPSR6_11 FM(SSI_SCK5)
199#define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
200#define GPSR6_9 F_(SSI_WS4, IP15_27_24)
201#define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
202#define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
203#define GPSR6_6 F_(SSI_WS349, IP15_15_12)
204#define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
205#define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
206#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
207#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
208#define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
209#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
210
211/* GPSR7 */
212#define GPSR7_3 FM(GP7_03)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]213#define GPSR7_2 FM(GP7_02)
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]214#define GPSR7_1 FM(AVS2)
215#define GPSR7_0 FM(AVS1)
216
217
218/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
219#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232#define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233#define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246
247/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
248#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257#define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277
278/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
279#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300#define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301#define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302#define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311#define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313
314/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
315#define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316#define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317#define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318#define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322#define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326#define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333#define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334#define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335#define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
336#define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337#define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338#define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339#define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340#define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341#define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342#define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343
344/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
345#define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346#define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347#define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348#define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349#define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350#define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351#define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352#define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353#define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354#define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355#define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356#define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357#define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358#define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
361#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]362#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]363#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
364#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
365#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
366#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
367#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
368#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
369#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
370#define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
371#define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
372
373#define PINMUX_GPSR \
374\
375 GPSR6_31 \
376 GPSR6_30 \
377 GPSR6_29 \
378 GPSR1_28 GPSR6_28 \
379 GPSR1_27 GPSR6_27 \
380 GPSR1_26 GPSR6_26 \
381 GPSR1_25 GPSR5_25 GPSR6_25 \
382 GPSR1_24 GPSR5_24 GPSR6_24 \
383 GPSR1_23 GPSR5_23 GPSR6_23 \
384 GPSR1_22 GPSR5_22 GPSR6_22 \
385 GPSR1_21 GPSR5_21 GPSR6_21 \
386 GPSR1_20 GPSR5_20 GPSR6_20 \
387 GPSR1_19 GPSR5_19 GPSR6_19 \
388 GPSR1_18 GPSR5_18 GPSR6_18 \
389 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
390 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
391GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
392GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
393GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
394GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
395GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
396GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
397GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
398GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
399GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
400GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
401GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
402GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
403GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
404GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
405GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
406GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
407
408#define PINMUX_IPSR \
409\
410FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
411FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
412FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
413FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
414FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
415FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
416FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
417FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
418\
419FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
420FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
421FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
422FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
423FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
424FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
425FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
426FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
427\
428FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
429FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
430FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
431FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
432FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
433FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
434FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
435FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
436\
437FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
438FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
439FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
440FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
441FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
442FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
443FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
444FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
445\
446FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
447FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
448FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
449FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
450FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
451FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
452FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
453FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
454
455/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
456#define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
457#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
458#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
459#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
460#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
461#define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
462#define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
463#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
464#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
465#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
466#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
467#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
468#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
469#define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
470#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
471#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
472#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]473#define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3)
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]474
475/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
476#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
477#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
478#define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
479#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
480#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
481#define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
482#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
483#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
484#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
485#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
486#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
487#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
488#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
489#define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
490#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
491#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
492#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
493#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
494#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
495#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
496#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
497#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
498
499/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
500#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
501#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
502#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
503#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
504#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
505#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]506#define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1)
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]507#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
508#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
509#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]510#define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1)
511#define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1)
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]512#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
513
514#define PINMUX_MOD_SELS \
515\
516MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
517 MOD_SEL2_30 \
518 MOD_SEL1_29_28_27 MOD_SEL2_29 \
519MOD_SEL0_28_27 MOD_SEL2_28_27 \
520MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
521 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
522MOD_SEL0_23 MOD_SEL1_23_22_21 \
523MOD_SEL0_22 MOD_SEL2_22 \
524MOD_SEL0_21 MOD_SEL2_21 \
525MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
526MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
527MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
528 MOD_SEL2_17 \
529MOD_SEL0_16 MOD_SEL1_16 \
530 MOD_SEL1_15_14 \
531MOD_SEL0_14_13 \
532 MOD_SEL1_13 \
533MOD_SEL0_12 MOD_SEL1_12 \
534MOD_SEL0_11 MOD_SEL1_11 \
535MOD_SEL0_10 MOD_SEL1_10 \
536MOD_SEL0_9_8 MOD_SEL1_9 \
537MOD_SEL0_7_6 \
538 MOD_SEL1_6 \
539MOD_SEL0_5 MOD_SEL1_5 \
540MOD_SEL0_4_3 MOD_SEL1_4 \
541 MOD_SEL1_3 \
542 MOD_SEL1_2 \
543 MOD_SEL1_1 \
544 MOD_SEL1_0 MOD_SEL2_0
545
546/*
547 * These pins are not able to be muxed but have other properties
548 * that can be set, such as drive-strength or pull-up/pull-down enable.
549 */
550#define PINMUX_STATIC \
551 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
552 FM(QSPI0_IO2) FM(QSPI0_IO3) \
553 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
554 FM(QSPI1_IO2) FM(QSPI1_IO3) \
555 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
556 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
557 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
558 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
559 FM(PRESETOUT) \
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]560 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN3) \
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]561 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
562
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]563#define PINMUX_PHYS \
564 FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
565
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]566enum {
567 PINMUX_RESERVED = 0,
568
569 PINMUX_DATA_BEGIN,
570 GP_ALL(DATA),
571 PINMUX_DATA_END,
572
573#define F_(x, y)
574#define FM(x) FN_##x,
575 PINMUX_FUNCTION_BEGIN,
576 GP_ALL(FN),
577 PINMUX_GPSR
578 PINMUX_IPSR
579 PINMUX_MOD_SELS
580 PINMUX_FUNCTION_END,
581#undef F_
582#undef FM
583
584#define F_(x, y)
585#define FM(x) x##_MARK,
586 PINMUX_MARK_BEGIN,
587 PINMUX_GPSR
588 PINMUX_IPSR
589 PINMUX_MOD_SELS
590 PINMUX_STATIC
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]591 PINMUX_PHYS
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]592 PINMUX_MARK_END,
593#undef F_
594#undef FM
595};
596
597static const u16 pinmux_data[] = {
598 PINMUX_DATA_GP_ALL(),
599
600 PINMUX_SINGLE(AVS1),
601 PINMUX_SINGLE(AVS2),
602 PINMUX_SINGLE(CLKOUT),
603 PINMUX_SINGLE(GP7_03),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]604 PINMUX_SINGLE(GP7_02),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]605 PINMUX_SINGLE(MSIOF0_RXD),
606 PINMUX_SINGLE(MSIOF0_SCK),
607 PINMUX_SINGLE(MSIOF0_TXD),
608 PINMUX_SINGLE(SSI_SCK5),
609 PINMUX_SINGLE(SSI_SDATA5),
610 PINMUX_SINGLE(SSI_WS5),
611
612 /* IPSR0 */
613 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
614 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
615
616 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
617 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
618 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
619
620 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
621 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
622 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
623
624 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
625 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
626 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
627 PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A),
628
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]629 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
630 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
631 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
632 PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]633
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]634 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
635 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
636 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
637 PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]638
639 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
640 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
641 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
642 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
643 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
644 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
645 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
646
647 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
648 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
649 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
650 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
651 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
652 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
653 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
654
655 /* IPSR1 */
656 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
657 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
658 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
659 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
660 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
661 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
662
663 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
664 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
665 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
666 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
667 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
668 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
669
670 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
671 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
672 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
673 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
674 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
675 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
676
677 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
678 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
679 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
680 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
681 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
682 PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B),
683 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
684
685 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
686 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
687 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
688 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
689
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]690 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
691 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
692 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
693 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]694 PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]695
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]696 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
697 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
698 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
699 PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]700
701 PINMUX_IPSR_GPSR(IP1_31_28, A0),
702 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
703 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
704 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
705 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
706 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
707
708 /* IPSR2 */
709 PINMUX_IPSR_GPSR(IP2_3_0, A1),
710 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
711 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
712 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
713 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
714 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
715
716 PINMUX_IPSR_GPSR(IP2_7_4, A2),
717 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
718 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
719 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
720 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
721 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
722
723 PINMUX_IPSR_GPSR(IP2_11_8, A3),
724 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
725 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
726 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
727 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
728 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
729
730 PINMUX_IPSR_GPSR(IP2_15_12, A4),
731 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
732 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
733 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
734 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
735 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
736
737 PINMUX_IPSR_GPSR(IP2_19_16, A5),
738 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
739 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
740 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
741 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
742 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
743 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
744
745 PINMUX_IPSR_GPSR(IP2_23_20, A6),
746 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
747 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
748 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
749 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
750 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
751 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
752
753 PINMUX_IPSR_GPSR(IP2_27_24, A7),
754 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
755 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
756 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
757 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
758 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
759 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
760
761 PINMUX_IPSR_GPSR(IP2_31_28, A8),
762 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
763 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
764 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
765 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
766 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
767 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
768
769 /* IPSR3 */
770 PINMUX_IPSR_GPSR(IP3_3_0, A9),
771 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
772 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
773 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
774
775 PINMUX_IPSR_GPSR(IP3_7_4, A10),
776 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
777 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
778 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
779
780 PINMUX_IPSR_GPSR(IP3_11_8, A11),
781 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
782 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
783 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
784 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
785 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
786 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
787 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
788 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
789
790 PINMUX_IPSR_GPSR(IP3_15_12, A12),
791 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
792 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
793 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
794 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
795 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
796
797 PINMUX_IPSR_GPSR(IP3_19_16, A13),
798 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
799 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
800 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
801 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
802 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
803
804 PINMUX_IPSR_GPSR(IP3_23_20, A14),
805 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
806 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
807 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
808 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
809 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
810
811 PINMUX_IPSR_GPSR(IP3_27_24, A15),
812 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
813 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
814 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
815 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
816 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
817
818 PINMUX_IPSR_GPSR(IP3_31_28, A16),
819 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
820 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
821 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
822
823 /* IPSR4 */
824 PINMUX_IPSR_GPSR(IP4_3_0, A17),
825 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
826 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
827 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
828
829 PINMUX_IPSR_GPSR(IP4_7_4, A18),
830 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
831 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
832 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
833
834 PINMUX_IPSR_GPSR(IP4_11_8, A19),
835 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
836 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
837 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
838
839 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
840 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
841
842 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
843 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
844 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
845
846 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
847 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
848 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
849 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
850 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
851 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
852 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
853 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
854
855 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
856 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
857 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
858 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
859 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
860 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
861
862 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
863 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
864 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
865 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
866 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
867 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
868
869 /* IPSR5 */
870 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
871 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
872 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
873 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
874 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
875 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
876 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
877
878 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
879 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
880 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
881 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
882 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
883 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
884 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
885 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
886
887 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
888 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
889 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
890 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
891
892 PINMUX_IPSR_GPSR(IP5_15_12, D0),
893 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
894 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
895 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
896 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
897
898 PINMUX_IPSR_GPSR(IP5_19_16, D1),
899 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
900 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
901 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
902 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
903
904 PINMUX_IPSR_GPSR(IP5_23_20, D2),
905 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
906 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
907 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
908
909 PINMUX_IPSR_GPSR(IP5_27_24, D3),
910 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
911 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
912 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
913
914 PINMUX_IPSR_GPSR(IP5_31_28, D4),
915 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
916 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
917 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
918
919 /* IPSR6 */
920 PINMUX_IPSR_GPSR(IP6_3_0, D5),
921 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
922 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
923 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
924
925 PINMUX_IPSR_GPSR(IP6_7_4, D6),
926 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
927 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
928 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
929
930 PINMUX_IPSR_GPSR(IP6_11_8, D7),
931 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
932 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
933 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
934
935 PINMUX_IPSR_GPSR(IP6_15_12, D8),
936 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
937 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
938 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
939 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
940 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
941
942 PINMUX_IPSR_GPSR(IP6_19_16, D9),
943 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
944 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
945 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
946 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
947
948 PINMUX_IPSR_GPSR(IP6_23_20, D10),
949 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
950 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
951 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
952 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
953 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
954 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
955
956 PINMUX_IPSR_GPSR(IP6_27_24, D11),
957 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
958 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
959 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
960 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
961 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
962 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
963
964 PINMUX_IPSR_GPSR(IP6_31_28, D12),
965 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
966 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
967 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
968 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
969 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
970
971 /* IPSR7 */
972 PINMUX_IPSR_GPSR(IP7_3_0, D13),
973 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
974 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
975 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
976 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
977 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
978
979 PINMUX_IPSR_GPSR(IP7_7_4, D14),
980 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
981 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
982 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
983 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
984 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
985 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
986
987 PINMUX_IPSR_GPSR(IP7_11_8, D15),
988 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
989 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
990 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
991 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
992 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
993 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
994
995 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
996 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
997 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
998
999 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
1000 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
1001 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
1002
1003 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
1004 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
1005 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
1006 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
1007
1008 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
1009 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
1010 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
1011 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
1012
1013 /* IPSR8 */
1014 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
1015 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1016 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1017 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
1018
1019 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1020 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1021 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1022 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
1023
1024 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1025 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1026 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
1027
1028 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1029 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1030 PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1031 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1032 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
1033
1034 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1035 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1036 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1037 PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1038 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1039 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1040
1041 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1042 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1043 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1044 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1045 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1046 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1047
1048 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1049 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1050 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1051 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1052 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1053 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1054
1055 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1056 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1057 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1058 PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1059 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1060 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1061
1062 /* IPSR9 */
1063 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1064 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
1065
1066 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
1067 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
1068
1069 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
1070 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
1071
1072 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1073 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
1074
1075 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1076 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
1077
1078 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1079 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
1080
1081 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1082 PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1083 PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B),
1084
1085 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1086 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
1087
1088 /* IPSR10 */
1089 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
1090 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
1091
1092 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
1093 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
1094
1095 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1096 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
1097
1098 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
1099 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
1100
1101 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
1102 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
1103
1104 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
1105 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
1106 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
1107
1108 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
1109 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
1110 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
1111
1112 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
1113 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
1114 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
1115
1116 /* IPSR11 */
1117 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
1118 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
1119 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
1120
1121 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
1122 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1123
1124 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1125 PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDF_0),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1126 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1127 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1128
1129 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1130 PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDF_0),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1131 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1132
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1133 PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0),
1134 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0),
1135 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1136 PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1137
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1138 PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0),
1139 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0),
1140 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1141 PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1142
1143 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1144 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1145 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1146 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADGC_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1147 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1148 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1149 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1150 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1151 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
1152 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
1153
1154 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
1155 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
1156 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
1157 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1158 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
1159
1160 /* IPSR12 */
1161 PINMUX_IPSR_GPSR(IP12_3_0, TX0),
1162 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
1163 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1164 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1165 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
1166
1167 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
1168 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1169 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1170 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1171 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1172 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1173 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1174 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1175
1176 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
1177 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1178 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1179 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1180 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1181 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1182 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1183 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1184
1185 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
1186 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
1187 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1188 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1189 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1190
1191 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
1192 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
1193 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1194 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1195 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
1196
1197 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
1198 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1199 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1200 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1201 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1202 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1203 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1204
1205 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N),
1206 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1207 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1208 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1209 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1210 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
1211 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1212
1213 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
1214 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
1215 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1216 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1217 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1218 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1219 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
1220
1221 /* IPSR13 */
1222 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
1223 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
1224 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1225 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1226 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
1227 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
1228
1229 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1230 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1231 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1232 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1233 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1234 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
1235
1236 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1237 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1238 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADGB_0),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1239 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
1240 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1241 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1242 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1243 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
1244
1245 PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
1246 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
1247 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1),
1248 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1249 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1250 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
1251
1252 PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
1253 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
1254 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1),
1255 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1256 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1257 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
1258
1259 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
1260 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
1261 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
1262 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0),
1263 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1264 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1265 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1266 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
1267
1268 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
1269 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
1270 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
1271 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0),
1272 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1273 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
1274 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
1275
1276 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
1277 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
1278 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
1279 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
1280
1281 /* IPSR14 */
1282 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1283 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1284 PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0),
1285 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADGA_2),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1286 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
1287 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1288 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
1289 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1),
1290
1291 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1292 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1293 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1294 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADGC_0),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1295 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
1296 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1297 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
1298 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1299
1300 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1301 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1302 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
1303
1304 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
1305 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
1306 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1307 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
1308
1309 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
1310 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
1311 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1312
1313 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
1314 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1315
1316 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
1317 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1318
1319 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
1320 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1321
1322 /* IPSR15 */
1323 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0),
1324
1325 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0),
1326 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1),
1327
1328 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
1329 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1330 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1331
1332 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
1333 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1334 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1335 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1336
1337 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
1338 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1339 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1340 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
1341 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1342 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
1343 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
1344
1345 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
1346 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
1347 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1348 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1349 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1350 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1351 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1352
1353 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
1354 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
1355 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1356 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1357 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1358 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1359 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1360
1361 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
1362 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
1363 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1364 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1365 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1366 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
1367 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
1368
1369 /* IPSR16 */
1370 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
1371 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1372
1373 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
1374 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
1375
1376 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1377 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1378 PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A),
1379
1380 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
1381 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
1382 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1383 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
1384 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1385 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1386 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1387
1388 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
1389 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
1390 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1391 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1392 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1393 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1394 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1395
1396 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
1397 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1398 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1399 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1400 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1401 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1402 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
1403 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
1404
1405 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1406 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1407 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1408 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1409 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1410 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
1411 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
1412
1413 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0),
1414 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
1415 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1416 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
1417 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1),
1418 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1419 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1420 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
1421
1422 /* IPSR17 */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1423 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADGA_0),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1424
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]1425 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADGB_1),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1426 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
1427 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1428 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
1429 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0),
1430
1431 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1432 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1433 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
1434 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1435 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
1436 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1437 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
1438
1439 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
1440 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
1441 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
1442 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
1443 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
1444 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
1445
1446 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
1447 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
1448 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0),
1449 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
1450 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1451 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
1452 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1453 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1454 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
1455
1456 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
1457 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
1458 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0),
1459 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1460 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1461 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
1462 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1463 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
1464 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
1465
1466 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
1467 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
1468 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1),
1469 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1470 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
1471 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1472 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
1473 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
1474 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1475 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1476 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
1477
1478 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
1479 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
1480 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1),
1481 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1482 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1483 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1484 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
1485 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
1486 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1487
1488 /* IPSR18 */
1489 PINMUX_IPSR_GPSR(IP18_3_0, GP6_30),
1490 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
1491 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1),
1492 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1493 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1494 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1495 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
1496 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1497 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1498
1499 PINMUX_IPSR_GPSR(IP18_7_4, GP6_31),
1500 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
1501 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1),
1502 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1503 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1504 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1505 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
1506 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1507 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
1508
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1509/*
1510 * Static pins can not be muxed between different functions but
1511 * still need mark entries in the pinmux list. Add each static
1512 * pin to the list without an associated function. The sh-pfc
1513 * core will do the right thing and skip trying to mux the pin
1514 * while still applying configuration to it.
1515 */
1516#define FM(x) PINMUX_DATA(x##_MARK, 0),
1517 PINMUX_STATIC
1518#undef FM
1519};
1520
1521/*
1522 * R8A77965 has 8 banks with 32 GPIOs in each => 256 GPIOs.
1523 * Physical layout rows: A - AW, cols: 1 - 39.
1524 */
1525#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1526#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1527#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1528#define PIN_NONE U16_MAX
1529
1530static const struct sh_pfc_pin pinmux_pins[] = {
1531 PINMUX_GPIO_GP_ALL(),
1532
1533 /*
1534 * Pins not associated with a GPIO port.
1535 *
1536 * The pin positions are different between different r8a77965
1537 * packages, all that is needed for the pfc driver is a unique
1538 * number for each pin. To this end use the pin layout from
1539 * R-Car M3SiP to calculate a unique number for each pin.
1540 */
1541 SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
1542 SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
1543 SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1544 SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1545 SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1546 SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1547 SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1548 SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1549 SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1550 SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1551 SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1552 SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1553 SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1554 SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1555 SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
1556 SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1557 SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
1558 SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
1559 SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
1560 SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
1561 SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
1562 SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
1563 SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
1564 SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
1565 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
1566 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
1567 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
1568 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
1569 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
1570 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST, CFG_FLAGS),
1571 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1572 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
1573 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
1574 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
1575 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1576 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]1577 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1578 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1579 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1580 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1581 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1582 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
1583};
1584
1585/* - AUDIO CLOCK ------------------------------------------------------------ */
1586static const unsigned int audio_clk_a_a_pins[] = {
1587 /* CLK A */
1588 RCAR_GP_PIN(6, 22),
1589};
1590static const unsigned int audio_clk_a_a_mux[] = {
1591 AUDIO_CLKA_A_MARK,
1592};
1593static const unsigned int audio_clk_a_b_pins[] = {
1594 /* CLK A */
1595 RCAR_GP_PIN(5, 4),
1596};
1597static const unsigned int audio_clk_a_b_mux[] = {
1598 AUDIO_CLKA_B_MARK,
1599};
1600static const unsigned int audio_clk_a_c_pins[] = {
1601 /* CLK A */
1602 RCAR_GP_PIN(5, 19),
1603};
1604static const unsigned int audio_clk_a_c_mux[] = {
1605 AUDIO_CLKA_C_MARK,
1606};
1607static const unsigned int audio_clk_b_a_pins[] = {
1608 /* CLK B */
1609 RCAR_GP_PIN(5, 12),
1610};
1611static const unsigned int audio_clk_b_a_mux[] = {
1612 AUDIO_CLKB_A_MARK,
1613};
1614static const unsigned int audio_clk_b_b_pins[] = {
1615 /* CLK B */
1616 RCAR_GP_PIN(6, 23),
1617};
1618static const unsigned int audio_clk_b_b_mux[] = {
1619 AUDIO_CLKB_B_MARK,
1620};
1621static const unsigned int audio_clk_c_a_pins[] = {
1622 /* CLK C */
1623 RCAR_GP_PIN(5, 21),
1624};
1625static const unsigned int audio_clk_c_a_mux[] = {
1626 AUDIO_CLKC_A_MARK,
1627};
1628static const unsigned int audio_clk_c_b_pins[] = {
1629 /* CLK C */
1630 RCAR_GP_PIN(5, 0),
1631};
1632static const unsigned int audio_clk_c_b_mux[] = {
1633 AUDIO_CLKC_B_MARK,
1634};
1635static const unsigned int audio_clkout_a_pins[] = {
1636 /* CLKOUT */
1637 RCAR_GP_PIN(5, 18),
1638};
1639static const unsigned int audio_clkout_a_mux[] = {
1640 AUDIO_CLKOUT_A_MARK,
1641};
1642static const unsigned int audio_clkout_b_pins[] = {
1643 /* CLKOUT */
1644 RCAR_GP_PIN(6, 28),
1645};
1646static const unsigned int audio_clkout_b_mux[] = {
1647 AUDIO_CLKOUT_B_MARK,
1648};
1649static const unsigned int audio_clkout_c_pins[] = {
1650 /* CLKOUT */
1651 RCAR_GP_PIN(5, 3),
1652};
1653static const unsigned int audio_clkout_c_mux[] = {
1654 AUDIO_CLKOUT_C_MARK,
1655};
1656static const unsigned int audio_clkout_d_pins[] = {
1657 /* CLKOUT */
1658 RCAR_GP_PIN(5, 21),
1659};
1660static const unsigned int audio_clkout_d_mux[] = {
1661 AUDIO_CLKOUT_D_MARK,
1662};
1663static const unsigned int audio_clkout1_a_pins[] = {
1664 /* CLKOUT1 */
1665 RCAR_GP_PIN(5, 15),
1666};
1667static const unsigned int audio_clkout1_a_mux[] = {
1668 AUDIO_CLKOUT1_A_MARK,
1669};
1670static const unsigned int audio_clkout1_b_pins[] = {
1671 /* CLKOUT1 */
1672 RCAR_GP_PIN(6, 29),
1673};
1674static const unsigned int audio_clkout1_b_mux[] = {
1675 AUDIO_CLKOUT1_B_MARK,
1676};
1677static const unsigned int audio_clkout2_a_pins[] = {
1678 /* CLKOUT2 */
1679 RCAR_GP_PIN(5, 16),
1680};
1681static const unsigned int audio_clkout2_a_mux[] = {
1682 AUDIO_CLKOUT2_A_MARK,
1683};
1684static const unsigned int audio_clkout2_b_pins[] = {
1685 /* CLKOUT2 */
1686 RCAR_GP_PIN(6, 30),
1687};
1688static const unsigned int audio_clkout2_b_mux[] = {
1689 AUDIO_CLKOUT2_B_MARK,
1690};
1691
1692static const unsigned int audio_clkout3_a_pins[] = {
1693 /* CLKOUT3 */
1694 RCAR_GP_PIN(5, 19),
1695};
1696static const unsigned int audio_clkout3_a_mux[] = {
1697 AUDIO_CLKOUT3_A_MARK,
1698};
1699static const unsigned int audio_clkout3_b_pins[] = {
1700 /* CLKOUT3 */
1701 RCAR_GP_PIN(6, 31),
1702};
1703static const unsigned int audio_clkout3_b_mux[] = {
1704 AUDIO_CLKOUT3_B_MARK,
1705};
1706
1707/* - EtherAVB --------------------------------------------------------------- */
1708static const unsigned int avb_link_pins[] = {
1709 /* AVB_LINK */
1710 RCAR_GP_PIN(2, 12),
1711};
1712static const unsigned int avb_link_mux[] = {
1713 AVB_LINK_MARK,
1714};
1715static const unsigned int avb_magic_pins[] = {
1716 /* AVB_MAGIC_ */
1717 RCAR_GP_PIN(2, 10),
1718};
1719static const unsigned int avb_magic_mux[] = {
1720 AVB_MAGIC_MARK,
1721};
1722static const unsigned int avb_phy_int_pins[] = {
1723 /* AVB_PHY_INT */
1724 RCAR_GP_PIN(2, 11),
1725};
1726static const unsigned int avb_phy_int_mux[] = {
1727 AVB_PHY_INT_MARK,
1728};
1729static const unsigned int avb_mdio_pins[] = {
1730 /* AVB_MDC, AVB_MDIO */
1731 RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
1732};
1733static const unsigned int avb_mdio_mux[] = {
1734 AVB_MDC_MARK, AVB_MDIO_MARK,
1735};
1736static const unsigned int avb_mii_pins[] = {
1737 /*
1738 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1739 * AVB_TD1, AVB_TD2, AVB_TD3,
1740 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1741 * AVB_RD1, AVB_RD2, AVB_RD3,
1742 * AVB_TXCREFCLK
1743 */
1744 PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1745 PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1746 PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1747 PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1748 PIN_NUMBER('A', 12),
1749
1750};
1751static const unsigned int avb_mii_mux[] = {
1752 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1753 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1754 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1755 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1756 AVB_TXCREFCLK_MARK,
1757};
1758static const unsigned int avb_avtp_pps_pins[] = {
1759 /* AVB_AVTP_PPS */
1760 RCAR_GP_PIN(2, 6),
1761};
1762static const unsigned int avb_avtp_pps_mux[] = {
1763 AVB_AVTP_PPS_MARK,
1764};
1765static const unsigned int avb_avtp_match_a_pins[] = {
1766 /* AVB_AVTP_MATCH_A */
1767 RCAR_GP_PIN(2, 13),
1768};
1769static const unsigned int avb_avtp_match_a_mux[] = {
1770 AVB_AVTP_MATCH_A_MARK,
1771};
1772static const unsigned int avb_avtp_capture_a_pins[] = {
1773 /* AVB_AVTP_CAPTURE_A */
1774 RCAR_GP_PIN(2, 14),
1775};
1776static const unsigned int avb_avtp_capture_a_mux[] = {
1777 AVB_AVTP_CAPTURE_A_MARK,
1778};
1779static const unsigned int avb_avtp_match_b_pins[] = {
1780 /* AVB_AVTP_MATCH_B */
1781 RCAR_GP_PIN(1, 8),
1782};
1783static const unsigned int avb_avtp_match_b_mux[] = {
1784 AVB_AVTP_MATCH_B_MARK,
1785};
1786static const unsigned int avb_avtp_capture_b_pins[] = {
1787 /* AVB_AVTP_CAPTURE_B */
1788 RCAR_GP_PIN(1, 11),
1789};
1790static const unsigned int avb_avtp_capture_b_mux[] = {
1791 AVB_AVTP_CAPTURE_B_MARK,
1792};
1793
1794/* - CAN ------------------------------------------------------------------ */
1795static const unsigned int can0_data_a_pins[] = {
1796 /* TX, RX */
1797 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1798};
1799
1800static const unsigned int can0_data_a_mux[] = {
1801 CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1802};
1803
1804static const unsigned int can0_data_b_pins[] = {
1805 /* TX, RX */
1806 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1807};
1808
1809static const unsigned int can0_data_b_mux[] = {
1810 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1811};
1812
1813static const unsigned int can1_data_pins[] = {
1814 /* TX, RX */
1815 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1816};
1817
1818static const unsigned int can1_data_mux[] = {
1819 CAN1_TX_MARK, CAN1_RX_MARK,
1820};
1821
1822/* - CAN Clock -------------------------------------------------------------- */
1823static const unsigned int can_clk_pins[] = {
1824 /* CLK */
1825 RCAR_GP_PIN(1, 25),
1826};
1827
1828static const unsigned int can_clk_mux[] = {
1829 CAN_CLK_MARK,
1830};
1831
1832/* - CAN FD --------------------------------------------------------------- */
1833static const unsigned int canfd0_data_a_pins[] = {
1834 /* TX, RX */
1835 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1836};
1837
1838static const unsigned int canfd0_data_a_mux[] = {
1839 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
1840};
1841
1842static const unsigned int canfd0_data_b_pins[] = {
1843 /* TX, RX */
1844 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1845};
1846
1847static const unsigned int canfd0_data_b_mux[] = {
1848 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
1849};
1850
1851static const unsigned int canfd1_data_pins[] = {
1852 /* TX, RX */
1853 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1854};
1855
1856static const unsigned int canfd1_data_mux[] = {
1857 CANFD1_TX_MARK, CANFD1_RX_MARK,
1858};
1859
Biju Das0a362702020-10-28 10:34:24 +0000[diff] [blame^]1860#ifdef CONFIG_PINCTRL_PFC_R8A77965
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]1861/* - DRIF0 --------------------------------------------------------------- */
1862static const unsigned int drif0_ctrl_a_pins[] = {
1863 /* CLK, SYNC */
1864 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1865};
1866
1867static const unsigned int drif0_ctrl_a_mux[] = {
1868 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1869};
1870
1871static const unsigned int drif0_data0_a_pins[] = {
1872 /* D0 */
1873 RCAR_GP_PIN(6, 10),
1874};
1875
1876static const unsigned int drif0_data0_a_mux[] = {
1877 RIF0_D0_A_MARK,
1878};
1879
1880static const unsigned int drif0_data1_a_pins[] = {
1881 /* D1 */
1882 RCAR_GP_PIN(6, 7),
1883};
1884
1885static const unsigned int drif0_data1_a_mux[] = {
1886 RIF0_D1_A_MARK,
1887};
1888
1889static const unsigned int drif0_ctrl_b_pins[] = {
1890 /* CLK, SYNC */
1891 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1892};
1893
1894static const unsigned int drif0_ctrl_b_mux[] = {
1895 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1896};
1897
1898static const unsigned int drif0_data0_b_pins[] = {
1899 /* D0 */
1900 RCAR_GP_PIN(5, 1),
1901};
1902
1903static const unsigned int drif0_data0_b_mux[] = {
1904 RIF0_D0_B_MARK,
1905};
1906
1907static const unsigned int drif0_data1_b_pins[] = {
1908 /* D1 */
1909 RCAR_GP_PIN(5, 2),
1910};
1911
1912static const unsigned int drif0_data1_b_mux[] = {
1913 RIF0_D1_B_MARK,
1914};
1915
1916static const unsigned int drif0_ctrl_c_pins[] = {
1917 /* CLK, SYNC */
1918 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1919};
1920
1921static const unsigned int drif0_ctrl_c_mux[] = {
1922 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1923};
1924
1925static const unsigned int drif0_data0_c_pins[] = {
1926 /* D0 */
1927 RCAR_GP_PIN(5, 13),
1928};
1929
1930static const unsigned int drif0_data0_c_mux[] = {
1931 RIF0_D0_C_MARK,
1932};
1933
1934static const unsigned int drif0_data1_c_pins[] = {
1935 /* D1 */
1936 RCAR_GP_PIN(5, 14),
1937};
1938
1939static const unsigned int drif0_data1_c_mux[] = {
1940 RIF0_D1_C_MARK,
1941};
1942
1943/* - DRIF1 --------------------------------------------------------------- */
1944static const unsigned int drif1_ctrl_a_pins[] = {
1945 /* CLK, SYNC */
1946 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1947};
1948
1949static const unsigned int drif1_ctrl_a_mux[] = {
1950 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1951};
1952
1953static const unsigned int drif1_data0_a_pins[] = {
1954 /* D0 */
1955 RCAR_GP_PIN(6, 19),
1956};
1957
1958static const unsigned int drif1_data0_a_mux[] = {
1959 RIF1_D0_A_MARK,
1960};
1961
1962static const unsigned int drif1_data1_a_pins[] = {
1963 /* D1 */
1964 RCAR_GP_PIN(6, 20),
1965};
1966
1967static const unsigned int drif1_data1_a_mux[] = {
1968 RIF1_D1_A_MARK,
1969};
1970
1971static const unsigned int drif1_ctrl_b_pins[] = {
1972 /* CLK, SYNC */
1973 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1974};
1975
1976static const unsigned int drif1_ctrl_b_mux[] = {
1977 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1978};
1979
1980static const unsigned int drif1_data0_b_pins[] = {
1981 /* D0 */
1982 RCAR_GP_PIN(5, 7),
1983};
1984
1985static const unsigned int drif1_data0_b_mux[] = {
1986 RIF1_D0_B_MARK,
1987};
1988
1989static const unsigned int drif1_data1_b_pins[] = {
1990 /* D1 */
1991 RCAR_GP_PIN(5, 8),
1992};
1993
1994static const unsigned int drif1_data1_b_mux[] = {
1995 RIF1_D1_B_MARK,
1996};
1997
1998static const unsigned int drif1_ctrl_c_pins[] = {
1999 /* CLK, SYNC */
2000 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
2001};
2002
2003static const unsigned int drif1_ctrl_c_mux[] = {
2004 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
2005};
2006
2007static const unsigned int drif1_data0_c_pins[] = {
2008 /* D0 */
2009 RCAR_GP_PIN(5, 6),
2010};
2011
2012static const unsigned int drif1_data0_c_mux[] = {
2013 RIF1_D0_C_MARK,
2014};
2015
2016static const unsigned int drif1_data1_c_pins[] = {
2017 /* D1 */
2018 RCAR_GP_PIN(5, 10),
2019};
2020
2021static const unsigned int drif1_data1_c_mux[] = {
2022 RIF1_D1_C_MARK,
2023};
2024
2025/* - DRIF2 --------------------------------------------------------------- */
2026static const unsigned int drif2_ctrl_a_pins[] = {
2027 /* CLK, SYNC */
2028 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2029};
2030
2031static const unsigned int drif2_ctrl_a_mux[] = {
2032 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
2033};
2034
2035static const unsigned int drif2_data0_a_pins[] = {
2036 /* D0 */
2037 RCAR_GP_PIN(6, 7),
2038};
2039
2040static const unsigned int drif2_data0_a_mux[] = {
2041 RIF2_D0_A_MARK,
2042};
2043
2044static const unsigned int drif2_data1_a_pins[] = {
2045 /* D1 */
2046 RCAR_GP_PIN(6, 10),
2047};
2048
2049static const unsigned int drif2_data1_a_mux[] = {
2050 RIF2_D1_A_MARK,
2051};
2052
2053static const unsigned int drif2_ctrl_b_pins[] = {
2054 /* CLK, SYNC */
2055 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
2056};
2057
2058static const unsigned int drif2_ctrl_b_mux[] = {
2059 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
2060};
2061
2062static const unsigned int drif2_data0_b_pins[] = {
2063 /* D0 */
2064 RCAR_GP_PIN(6, 30),
2065};
2066
2067static const unsigned int drif2_data0_b_mux[] = {
2068 RIF2_D0_B_MARK,
2069};
2070
2071static const unsigned int drif2_data1_b_pins[] = {
2072 /* D1 */
2073 RCAR_GP_PIN(6, 31),
2074};
2075
2076static const unsigned int drif2_data1_b_mux[] = {
2077 RIF2_D1_B_MARK,
2078};
2079
2080/* - DRIF3 --------------------------------------------------------------- */
2081static const unsigned int drif3_ctrl_a_pins[] = {
2082 /* CLK, SYNC */
2083 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2084};
2085
2086static const unsigned int drif3_ctrl_a_mux[] = {
2087 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
2088};
2089
2090static const unsigned int drif3_data0_a_pins[] = {
2091 /* D0 */
2092 RCAR_GP_PIN(6, 19),
2093};
2094
2095static const unsigned int drif3_data0_a_mux[] = {
2096 RIF3_D0_A_MARK,
2097};
2098
2099static const unsigned int drif3_data1_a_pins[] = {
2100 /* D1 */
2101 RCAR_GP_PIN(6, 20),
2102};
2103
2104static const unsigned int drif3_data1_a_mux[] = {
2105 RIF3_D1_A_MARK,
2106};
2107
2108static const unsigned int drif3_ctrl_b_pins[] = {
2109 /* CLK, SYNC */
2110 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2111};
2112
2113static const unsigned int drif3_ctrl_b_mux[] = {
2114 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
2115};
2116
2117static const unsigned int drif3_data0_b_pins[] = {
2118 /* D0 */
2119 RCAR_GP_PIN(6, 28),
2120};
2121
2122static const unsigned int drif3_data0_b_mux[] = {
2123 RIF3_D0_B_MARK,
2124};
2125
2126static const unsigned int drif3_data1_b_pins[] = {
2127 /* D1 */
2128 RCAR_GP_PIN(6, 29),
2129};
2130
2131static const unsigned int drif3_data1_b_mux[] = {
2132 RIF3_D1_B_MARK,
2133};
Biju Das0a362702020-10-28 10:34:24 +0000[diff] [blame^]2134#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]2135
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2136/* - DU --------------------------------------------------------------------- */
2137static const unsigned int du_rgb666_pins[] = {
2138 /* R[7:2], G[7:2], B[7:2] */
2139 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2140 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2141 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2142 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2143 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2144 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2145};
2146
2147static const unsigned int du_rgb666_mux[] = {
2148 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2149 DU_DR3_MARK, DU_DR2_MARK,
2150 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2151 DU_DG3_MARK, DU_DG2_MARK,
2152 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2153 DU_DB3_MARK, DU_DB2_MARK,
2154};
2155
2156static const unsigned int du_rgb888_pins[] = {
2157 /* R[7:0], G[7:0], B[7:0] */
2158 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2159 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2160 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
2161 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2162 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2163 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2164 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2165 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2166 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2167};
2168
2169static const unsigned int du_rgb888_mux[] = {
2170 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2171 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2172 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2173 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2174 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2175 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2176};
2177
2178static const unsigned int du_clk_out_0_pins[] = {
2179 /* CLKOUT */
2180 RCAR_GP_PIN(1, 27),
2181};
2182
2183static const unsigned int du_clk_out_0_mux[] = {
2184 DU_DOTCLKOUT0_MARK
2185};
2186
2187static const unsigned int du_clk_out_1_pins[] = {
2188 /* CLKOUT */
2189 RCAR_GP_PIN(2, 3),
2190};
2191
2192static const unsigned int du_clk_out_1_mux[] = {
2193 DU_DOTCLKOUT1_MARK
2194};
2195
2196static const unsigned int du_sync_pins[] = {
2197 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2198 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2199};
2200
2201static const unsigned int du_sync_mux[] = {
2202 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2203};
2204
2205static const unsigned int du_oddf_pins[] = {
2206 /* EXDISP/EXODDF/EXCDE */
2207 RCAR_GP_PIN(2, 2),
2208};
2209
2210static const unsigned int du_oddf_mux[] = {
2211 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2212};
2213
2214static const unsigned int du_cde_pins[] = {
2215 /* CDE */
2216 RCAR_GP_PIN(2, 0),
2217};
2218
2219static const unsigned int du_cde_mux[] = {
2220 DU_CDE_MARK,
2221};
2222
2223static const unsigned int du_disp_pins[] = {
2224 /* DISP */
2225 RCAR_GP_PIN(2, 1),
2226};
2227
2228static const unsigned int du_disp_mux[] = {
2229 DU_DISP_MARK,
2230};
2231
2232/* - HSCIF0 ----------------------------------------------------------------- */
2233static const unsigned int hscif0_data_pins[] = {
2234 /* RX, TX */
2235 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2236};
2237
2238static const unsigned int hscif0_data_mux[] = {
2239 HRX0_MARK, HTX0_MARK,
2240};
2241
2242static const unsigned int hscif0_clk_pins[] = {
2243 /* SCK */
2244 RCAR_GP_PIN(5, 12),
2245};
2246
2247static const unsigned int hscif0_clk_mux[] = {
2248 HSCK0_MARK,
2249};
2250
2251static const unsigned int hscif0_ctrl_pins[] = {
2252 /* RTS, CTS */
2253 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2254};
2255
2256static const unsigned int hscif0_ctrl_mux[] = {
2257 HRTS0_N_MARK, HCTS0_N_MARK,
2258};
2259
2260/* - HSCIF1 ----------------------------------------------------------------- */
2261static const unsigned int hscif1_data_a_pins[] = {
2262 /* RX, TX */
2263 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2264};
2265
2266static const unsigned int hscif1_data_a_mux[] = {
2267 HRX1_A_MARK, HTX1_A_MARK,
2268};
2269
2270static const unsigned int hscif1_clk_a_pins[] = {
2271 /* SCK */
2272 RCAR_GP_PIN(6, 21),
2273};
2274
2275static const unsigned int hscif1_clk_a_mux[] = {
2276 HSCK1_A_MARK,
2277};
2278
2279static const unsigned int hscif1_ctrl_a_pins[] = {
2280 /* RTS, CTS */
2281 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2282};
2283
2284static const unsigned int hscif1_ctrl_a_mux[] = {
2285 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2286};
2287
2288static const unsigned int hscif1_data_b_pins[] = {
2289 /* RX, TX */
2290 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2291};
2292
2293static const unsigned int hscif1_data_b_mux[] = {
2294 HRX1_B_MARK, HTX1_B_MARK,
2295};
2296
2297static const unsigned int hscif1_clk_b_pins[] = {
2298 /* SCK */
2299 RCAR_GP_PIN(5, 0),
2300};
2301
2302static const unsigned int hscif1_clk_b_mux[] = {
2303 HSCK1_B_MARK,
2304};
2305
2306static const unsigned int hscif1_ctrl_b_pins[] = {
2307 /* RTS, CTS */
2308 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2309};
2310
2311static const unsigned int hscif1_ctrl_b_mux[] = {
2312 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2313};
2314
2315/* - HSCIF2 ----------------------------------------------------------------- */
2316static const unsigned int hscif2_data_a_pins[] = {
2317 /* RX, TX */
2318 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2319};
2320
2321static const unsigned int hscif2_data_a_mux[] = {
2322 HRX2_A_MARK, HTX2_A_MARK,
2323};
2324
2325static const unsigned int hscif2_clk_a_pins[] = {
2326 /* SCK */
2327 RCAR_GP_PIN(6, 10),
2328};
2329
2330static const unsigned int hscif2_clk_a_mux[] = {
2331 HSCK2_A_MARK,
2332};
2333
2334static const unsigned int hscif2_ctrl_a_pins[] = {
2335 /* RTS, CTS */
2336 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2337};
2338
2339static const unsigned int hscif2_ctrl_a_mux[] = {
2340 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2341};
2342
2343static const unsigned int hscif2_data_b_pins[] = {
2344 /* RX, TX */
2345 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2346};
2347
2348static const unsigned int hscif2_data_b_mux[] = {
2349 HRX2_B_MARK, HTX2_B_MARK,
2350};
2351
2352static const unsigned int hscif2_clk_b_pins[] = {
2353 /* SCK */
2354 RCAR_GP_PIN(6, 21),
2355};
2356
2357static const unsigned int hscif2_clk_b_mux[] = {
2358 HSCK2_B_MARK,
2359};
2360
2361static const unsigned int hscif2_ctrl_b_pins[] = {
2362 /* RTS, CTS */
2363 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2364};
2365
2366static const unsigned int hscif2_ctrl_b_mux[] = {
2367 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2368};
2369
2370static const unsigned int hscif2_data_c_pins[] = {
2371 /* RX, TX */
2372 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2373};
2374
2375static const unsigned int hscif2_data_c_mux[] = {
2376 HRX2_C_MARK, HTX2_C_MARK,
2377};
2378
2379static const unsigned int hscif2_clk_c_pins[] = {
2380 /* SCK */
2381 RCAR_GP_PIN(6, 24),
2382};
2383
2384static const unsigned int hscif2_clk_c_mux[] = {
2385 HSCK2_C_MARK,
2386};
2387
2388static const unsigned int hscif2_ctrl_c_pins[] = {
2389 /* RTS, CTS */
2390 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2391};
2392
2393static const unsigned int hscif2_ctrl_c_mux[] = {
2394 HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2395};
2396
2397/* - HSCIF3 ----------------------------------------------------------------- */
2398static const unsigned int hscif3_data_a_pins[] = {
2399 /* RX, TX */
2400 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2401};
2402
2403static const unsigned int hscif3_data_a_mux[] = {
2404 HRX3_A_MARK, HTX3_A_MARK,
2405};
2406
2407static const unsigned int hscif3_clk_pins[] = {
2408 /* SCK */
2409 RCAR_GP_PIN(1, 22),
2410};
2411
2412static const unsigned int hscif3_clk_mux[] = {
2413 HSCK3_MARK,
2414};
2415
2416static const unsigned int hscif3_ctrl_pins[] = {
2417 /* RTS, CTS */
2418 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2419};
2420
2421static const unsigned int hscif3_ctrl_mux[] = {
2422 HRTS3_N_MARK, HCTS3_N_MARK,
2423};
2424
2425static const unsigned int hscif3_data_b_pins[] = {
2426 /* RX, TX */
2427 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2428};
2429
2430static const unsigned int hscif3_data_b_mux[] = {
2431 HRX3_B_MARK, HTX3_B_MARK,
2432};
2433
2434static const unsigned int hscif3_data_c_pins[] = {
2435 /* RX, TX */
2436 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2437};
2438
2439static const unsigned int hscif3_data_c_mux[] = {
2440 HRX3_C_MARK, HTX3_C_MARK,
2441};
2442
2443static const unsigned int hscif3_data_d_pins[] = {
2444 /* RX, TX */
2445 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2446};
2447
2448static const unsigned int hscif3_data_d_mux[] = {
2449 HRX3_D_MARK, HTX3_D_MARK,
2450};
2451
2452/* - HSCIF4 ----------------------------------------------------------------- */
2453static const unsigned int hscif4_data_a_pins[] = {
2454 /* RX, TX */
2455 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2456};
2457
2458static const unsigned int hscif4_data_a_mux[] = {
2459 HRX4_A_MARK, HTX4_A_MARK,
2460};
2461
2462static const unsigned int hscif4_clk_pins[] = {
2463 /* SCK */
2464 RCAR_GP_PIN(1, 11),
2465};
2466
2467static const unsigned int hscif4_clk_mux[] = {
2468 HSCK4_MARK,
2469};
2470
2471static const unsigned int hscif4_ctrl_pins[] = {
2472 /* RTS, CTS */
2473 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2474};
2475
2476static const unsigned int hscif4_ctrl_mux[] = {
2477 HRTS4_N_MARK, HCTS4_N_MARK,
2478};
2479
2480static const unsigned int hscif4_data_b_pins[] = {
2481 /* RX, TX */
2482 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2483};
2484
2485static const unsigned int hscif4_data_b_mux[] = {
2486 HRX4_B_MARK, HTX4_B_MARK,
2487};
2488
2489/* - I2C -------------------------------------------------------------------- */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2490static const unsigned int i2c0_pins[] = {
2491 /* SCL, SDA */
2492 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2493};
2494
2495static const unsigned int i2c0_mux[] = {
2496 SCL0_MARK, SDA0_MARK,
2497};
2498
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2499static const unsigned int i2c1_a_pins[] = {
2500 /* SDA, SCL */
2501 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2502};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2503
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2504static const unsigned int i2c1_a_mux[] = {
2505 SDA1_A_MARK, SCL1_A_MARK,
2506};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2507
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2508static const unsigned int i2c1_b_pins[] = {
2509 /* SDA, SCL */
2510 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2511};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2512
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2513static const unsigned int i2c1_b_mux[] = {
2514 SDA1_B_MARK, SCL1_B_MARK,
2515};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2516
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2517static const unsigned int i2c2_a_pins[] = {
2518 /* SDA, SCL */
2519 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2520};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2521
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2522static const unsigned int i2c2_a_mux[] = {
2523 SDA2_A_MARK, SCL2_A_MARK,
2524};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2525
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2526static const unsigned int i2c2_b_pins[] = {
2527 /* SDA, SCL */
2528 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2529};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2530
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2531static const unsigned int i2c2_b_mux[] = {
2532 SDA2_B_MARK, SCL2_B_MARK,
2533};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2534
2535static const unsigned int i2c3_pins[] = {
2536 /* SCL, SDA */
2537 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2538};
2539
2540static const unsigned int i2c3_mux[] = {
2541 SCL3_MARK, SDA3_MARK,
2542};
2543
2544static const unsigned int i2c5_pins[] = {
2545 /* SCL, SDA */
2546 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
2547};
2548
2549static const unsigned int i2c5_mux[] = {
2550 SCL5_MARK, SDA5_MARK,
2551};
2552
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2553static const unsigned int i2c6_a_pins[] = {
2554 /* SDA, SCL */
2555 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2556};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2557
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2558static const unsigned int i2c6_a_mux[] = {
2559 SDA6_A_MARK, SCL6_A_MARK,
2560};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2561
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2562static const unsigned int i2c6_b_pins[] = {
2563 /* SDA, SCL */
2564 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2565};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2566
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2567static const unsigned int i2c6_b_mux[] = {
2568 SDA6_B_MARK, SCL6_B_MARK,
2569};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2570
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2571static const unsigned int i2c6_c_pins[] = {
2572 /* SDA, SCL */
2573 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2574};
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]2575
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]2576static const unsigned int i2c6_c_mux[] = {
2577 SDA6_C_MARK, SCL6_C_MARK,
2578};
2579
2580/* - INTC-EX ---------------------------------------------------------------- */
2581static const unsigned int intc_ex_irq0_pins[] = {
2582 /* IRQ0 */
2583 RCAR_GP_PIN(2, 0),
2584};
2585static const unsigned int intc_ex_irq0_mux[] = {
2586 IRQ0_MARK,
2587};
2588static const unsigned int intc_ex_irq1_pins[] = {
2589 /* IRQ1 */
2590 RCAR_GP_PIN(2, 1),
2591};
2592static const unsigned int intc_ex_irq1_mux[] = {
2593 IRQ1_MARK,
2594};
2595static const unsigned int intc_ex_irq2_pins[] = {
2596 /* IRQ2 */
2597 RCAR_GP_PIN(2, 2),
2598};
2599static const unsigned int intc_ex_irq2_mux[] = {
2600 IRQ2_MARK,
2601};
2602static const unsigned int intc_ex_irq3_pins[] = {
2603 /* IRQ3 */
2604 RCAR_GP_PIN(2, 3),
2605};
2606static const unsigned int intc_ex_irq3_mux[] = {
2607 IRQ3_MARK,
2608};
2609static const unsigned int intc_ex_irq4_pins[] = {
2610 /* IRQ4 */
2611 RCAR_GP_PIN(2, 4),
2612};
2613static const unsigned int intc_ex_irq4_mux[] = {
2614 IRQ4_MARK,
2615};
2616static const unsigned int intc_ex_irq5_pins[] = {
2617 /* IRQ5 */
2618 RCAR_GP_PIN(2, 5),
2619};
2620static const unsigned int intc_ex_irq5_mux[] = {
2621 IRQ5_MARK,
2622};
2623
2624/* - MSIOF0 ----------------------------------------------------------------- */
2625static const unsigned int msiof0_clk_pins[] = {
2626 /* SCK */
2627 RCAR_GP_PIN(5, 17),
2628};
2629static const unsigned int msiof0_clk_mux[] = {
2630 MSIOF0_SCK_MARK,
2631};
2632static const unsigned int msiof0_sync_pins[] = {
2633 /* SYNC */
2634 RCAR_GP_PIN(5, 18),
2635};
2636static const unsigned int msiof0_sync_mux[] = {
2637 MSIOF0_SYNC_MARK,
2638};
2639static const unsigned int msiof0_ss1_pins[] = {
2640 /* SS1 */
2641 RCAR_GP_PIN(5, 19),
2642};
2643static const unsigned int msiof0_ss1_mux[] = {
2644 MSIOF0_SS1_MARK,
2645};
2646static const unsigned int msiof0_ss2_pins[] = {
2647 /* SS2 */
2648 RCAR_GP_PIN(5, 21),
2649};
2650static const unsigned int msiof0_ss2_mux[] = {
2651 MSIOF0_SS2_MARK,
2652};
2653static const unsigned int msiof0_txd_pins[] = {
2654 /* TXD */
2655 RCAR_GP_PIN(5, 20),
2656};
2657static const unsigned int msiof0_txd_mux[] = {
2658 MSIOF0_TXD_MARK,
2659};
2660static const unsigned int msiof0_rxd_pins[] = {
2661 /* RXD */
2662 RCAR_GP_PIN(5, 22),
2663};
2664static const unsigned int msiof0_rxd_mux[] = {
2665 MSIOF0_RXD_MARK,
2666};
2667/* - MSIOF1 ----------------------------------------------------------------- */
2668static const unsigned int msiof1_clk_a_pins[] = {
2669 /* SCK */
2670 RCAR_GP_PIN(6, 8),
2671};
2672static const unsigned int msiof1_clk_a_mux[] = {
2673 MSIOF1_SCK_A_MARK,
2674};
2675static const unsigned int msiof1_sync_a_pins[] = {
2676 /* SYNC */
2677 RCAR_GP_PIN(6, 9),
2678};
2679static const unsigned int msiof1_sync_a_mux[] = {
2680 MSIOF1_SYNC_A_MARK,
2681};
2682static const unsigned int msiof1_ss1_a_pins[] = {
2683 /* SS1 */
2684 RCAR_GP_PIN(6, 5),
2685};
2686static const unsigned int msiof1_ss1_a_mux[] = {
2687 MSIOF1_SS1_A_MARK,
2688};
2689static const unsigned int msiof1_ss2_a_pins[] = {
2690 /* SS2 */
2691 RCAR_GP_PIN(6, 6),
2692};
2693static const unsigned int msiof1_ss2_a_mux[] = {
2694 MSIOF1_SS2_A_MARK,
2695};
2696static const unsigned int msiof1_txd_a_pins[] = {
2697 /* TXD */
2698 RCAR_GP_PIN(6, 7),
2699};
2700static const unsigned int msiof1_txd_a_mux[] = {
2701 MSIOF1_TXD_A_MARK,
2702};
2703static const unsigned int msiof1_rxd_a_pins[] = {
2704 /* RXD */
2705 RCAR_GP_PIN(6, 10),
2706};
2707static const unsigned int msiof1_rxd_a_mux[] = {
2708 MSIOF1_RXD_A_MARK,
2709};
2710static const unsigned int msiof1_clk_b_pins[] = {
2711 /* SCK */
2712 RCAR_GP_PIN(5, 9),
2713};
2714static const unsigned int msiof1_clk_b_mux[] = {
2715 MSIOF1_SCK_B_MARK,
2716};
2717static const unsigned int msiof1_sync_b_pins[] = {
2718 /* SYNC */
2719 RCAR_GP_PIN(5, 3),
2720};
2721static const unsigned int msiof1_sync_b_mux[] = {
2722 MSIOF1_SYNC_B_MARK,
2723};
2724static const unsigned int msiof1_ss1_b_pins[] = {
2725 /* SS1 */
2726 RCAR_GP_PIN(5, 4),
2727};
2728static const unsigned int msiof1_ss1_b_mux[] = {
2729 MSIOF1_SS1_B_MARK,
2730};
2731static const unsigned int msiof1_ss2_b_pins[] = {
2732 /* SS2 */
2733 RCAR_GP_PIN(5, 0),
2734};
2735static const unsigned int msiof1_ss2_b_mux[] = {
2736 MSIOF1_SS2_B_MARK,
2737};
2738static const unsigned int msiof1_txd_b_pins[] = {
2739 /* TXD */
2740 RCAR_GP_PIN(5, 8),
2741};
2742static const unsigned int msiof1_txd_b_mux[] = {
2743 MSIOF1_TXD_B_MARK,
2744};
2745static const unsigned int msiof1_rxd_b_pins[] = {
2746 /* RXD */
2747 RCAR_GP_PIN(5, 7),
2748};
2749static const unsigned int msiof1_rxd_b_mux[] = {
2750 MSIOF1_RXD_B_MARK,
2751};
2752static const unsigned int msiof1_clk_c_pins[] = {
2753 /* SCK */
2754 RCAR_GP_PIN(6, 17),
2755};
2756static const unsigned int msiof1_clk_c_mux[] = {
2757 MSIOF1_SCK_C_MARK,
2758};
2759static const unsigned int msiof1_sync_c_pins[] = {
2760 /* SYNC */
2761 RCAR_GP_PIN(6, 18),
2762};
2763static const unsigned int msiof1_sync_c_mux[] = {
2764 MSIOF1_SYNC_C_MARK,
2765};
2766static const unsigned int msiof1_ss1_c_pins[] = {
2767 /* SS1 */
2768 RCAR_GP_PIN(6, 21),
2769};
2770static const unsigned int msiof1_ss1_c_mux[] = {
2771 MSIOF1_SS1_C_MARK,
2772};
2773static const unsigned int msiof1_ss2_c_pins[] = {
2774 /* SS2 */
2775 RCAR_GP_PIN(6, 27),
2776};
2777static const unsigned int msiof1_ss2_c_mux[] = {
2778 MSIOF1_SS2_C_MARK,
2779};
2780static const unsigned int msiof1_txd_c_pins[] = {
2781 /* TXD */
2782 RCAR_GP_PIN(6, 20),
2783};
2784static const unsigned int msiof1_txd_c_mux[] = {
2785 MSIOF1_TXD_C_MARK,
2786};
2787static const unsigned int msiof1_rxd_c_pins[] = {
2788 /* RXD */
2789 RCAR_GP_PIN(6, 19),
2790};
2791static const unsigned int msiof1_rxd_c_mux[] = {
2792 MSIOF1_RXD_C_MARK,
2793};
2794static const unsigned int msiof1_clk_d_pins[] = {
2795 /* SCK */
2796 RCAR_GP_PIN(5, 12),
2797};
2798static const unsigned int msiof1_clk_d_mux[] = {
2799 MSIOF1_SCK_D_MARK,
2800};
2801static const unsigned int msiof1_sync_d_pins[] = {
2802 /* SYNC */
2803 RCAR_GP_PIN(5, 15),
2804};
2805static const unsigned int msiof1_sync_d_mux[] = {
2806 MSIOF1_SYNC_D_MARK,
2807};
2808static const unsigned int msiof1_ss1_d_pins[] = {
2809 /* SS1 */
2810 RCAR_GP_PIN(5, 16),
2811};
2812static const unsigned int msiof1_ss1_d_mux[] = {
2813 MSIOF1_SS1_D_MARK,
2814};
2815static const unsigned int msiof1_ss2_d_pins[] = {
2816 /* SS2 */
2817 RCAR_GP_PIN(5, 21),
2818};
2819static const unsigned int msiof1_ss2_d_mux[] = {
2820 MSIOF1_SS2_D_MARK,
2821};
2822static const unsigned int msiof1_txd_d_pins[] = {
2823 /* TXD */
2824 RCAR_GP_PIN(5, 14),
2825};
2826static const unsigned int msiof1_txd_d_mux[] = {
2827 MSIOF1_TXD_D_MARK,
2828};
2829static const unsigned int msiof1_rxd_d_pins[] = {
2830 /* RXD */
2831 RCAR_GP_PIN(5, 13),
2832};
2833static const unsigned int msiof1_rxd_d_mux[] = {
2834 MSIOF1_RXD_D_MARK,
2835};
2836static const unsigned int msiof1_clk_e_pins[] = {
2837 /* SCK */
2838 RCAR_GP_PIN(3, 0),
2839};
2840static const unsigned int msiof1_clk_e_mux[] = {
2841 MSIOF1_SCK_E_MARK,
2842};
2843static const unsigned int msiof1_sync_e_pins[] = {
2844 /* SYNC */
2845 RCAR_GP_PIN(3, 1),
2846};
2847static const unsigned int msiof1_sync_e_mux[] = {
2848 MSIOF1_SYNC_E_MARK,
2849};
2850static const unsigned int msiof1_ss1_e_pins[] = {
2851 /* SS1 */
2852 RCAR_GP_PIN(3, 4),
2853};
2854static const unsigned int msiof1_ss1_e_mux[] = {
2855 MSIOF1_SS1_E_MARK,
2856};
2857static const unsigned int msiof1_ss2_e_pins[] = {
2858 /* SS2 */
2859 RCAR_GP_PIN(3, 5),
2860};
2861static const unsigned int msiof1_ss2_e_mux[] = {
2862 MSIOF1_SS2_E_MARK,
2863};
2864static const unsigned int msiof1_txd_e_pins[] = {
2865 /* TXD */
2866 RCAR_GP_PIN(3, 3),
2867};
2868static const unsigned int msiof1_txd_e_mux[] = {
2869 MSIOF1_TXD_E_MARK,
2870};
2871static const unsigned int msiof1_rxd_e_pins[] = {
2872 /* RXD */
2873 RCAR_GP_PIN(3, 2),
2874};
2875static const unsigned int msiof1_rxd_e_mux[] = {
2876 MSIOF1_RXD_E_MARK,
2877};
2878static const unsigned int msiof1_clk_f_pins[] = {
2879 /* SCK */
2880 RCAR_GP_PIN(5, 23),
2881};
2882static const unsigned int msiof1_clk_f_mux[] = {
2883 MSIOF1_SCK_F_MARK,
2884};
2885static const unsigned int msiof1_sync_f_pins[] = {
2886 /* SYNC */
2887 RCAR_GP_PIN(5, 24),
2888};
2889static const unsigned int msiof1_sync_f_mux[] = {
2890 MSIOF1_SYNC_F_MARK,
2891};
2892static const unsigned int msiof1_ss1_f_pins[] = {
2893 /* SS1 */
2894 RCAR_GP_PIN(6, 1),
2895};
2896static const unsigned int msiof1_ss1_f_mux[] = {
2897 MSIOF1_SS1_F_MARK,
2898};
2899static const unsigned int msiof1_ss2_f_pins[] = {
2900 /* SS2 */
2901 RCAR_GP_PIN(6, 2),
2902};
2903static const unsigned int msiof1_ss2_f_mux[] = {
2904 MSIOF1_SS2_F_MARK,
2905};
2906static const unsigned int msiof1_txd_f_pins[] = {
2907 /* TXD */
2908 RCAR_GP_PIN(6, 0),
2909};
2910static const unsigned int msiof1_txd_f_mux[] = {
2911 MSIOF1_TXD_F_MARK,
2912};
2913static const unsigned int msiof1_rxd_f_pins[] = {
2914 /* RXD */
2915 RCAR_GP_PIN(5, 25),
2916};
2917static const unsigned int msiof1_rxd_f_mux[] = {
2918 MSIOF1_RXD_F_MARK,
2919};
2920static const unsigned int msiof1_clk_g_pins[] = {
2921 /* SCK */
2922 RCAR_GP_PIN(3, 6),
2923};
2924static const unsigned int msiof1_clk_g_mux[] = {
2925 MSIOF1_SCK_G_MARK,
2926};
2927static const unsigned int msiof1_sync_g_pins[] = {
2928 /* SYNC */
2929 RCAR_GP_PIN(3, 7),
2930};
2931static const unsigned int msiof1_sync_g_mux[] = {
2932 MSIOF1_SYNC_G_MARK,
2933};
2934static const unsigned int msiof1_ss1_g_pins[] = {
2935 /* SS1 */
2936 RCAR_GP_PIN(3, 10),
2937};
2938static const unsigned int msiof1_ss1_g_mux[] = {
2939 MSIOF1_SS1_G_MARK,
2940};
2941static const unsigned int msiof1_ss2_g_pins[] = {
2942 /* SS2 */
2943 RCAR_GP_PIN(3, 11),
2944};
2945static const unsigned int msiof1_ss2_g_mux[] = {
2946 MSIOF1_SS2_G_MARK,
2947};
2948static const unsigned int msiof1_txd_g_pins[] = {
2949 /* TXD */
2950 RCAR_GP_PIN(3, 9),
2951};
2952static const unsigned int msiof1_txd_g_mux[] = {
2953 MSIOF1_TXD_G_MARK,
2954};
2955static const unsigned int msiof1_rxd_g_pins[] = {
2956 /* RXD */
2957 RCAR_GP_PIN(3, 8),
2958};
2959static const unsigned int msiof1_rxd_g_mux[] = {
2960 MSIOF1_RXD_G_MARK,
2961};
2962/* - MSIOF2 ----------------------------------------------------------------- */
2963static const unsigned int msiof2_clk_a_pins[] = {
2964 /* SCK */
2965 RCAR_GP_PIN(1, 9),
2966};
2967static const unsigned int msiof2_clk_a_mux[] = {
2968 MSIOF2_SCK_A_MARK,
2969};
2970static const unsigned int msiof2_sync_a_pins[] = {
2971 /* SYNC */
2972 RCAR_GP_PIN(1, 8),
2973};
2974static const unsigned int msiof2_sync_a_mux[] = {
2975 MSIOF2_SYNC_A_MARK,
2976};
2977static const unsigned int msiof2_ss1_a_pins[] = {
2978 /* SS1 */
2979 RCAR_GP_PIN(1, 6),
2980};
2981static const unsigned int msiof2_ss1_a_mux[] = {
2982 MSIOF2_SS1_A_MARK,
2983};
2984static const unsigned int msiof2_ss2_a_pins[] = {
2985 /* SS2 */
2986 RCAR_GP_PIN(1, 7),
2987};
2988static const unsigned int msiof2_ss2_a_mux[] = {
2989 MSIOF2_SS2_A_MARK,
2990};
2991static const unsigned int msiof2_txd_a_pins[] = {
2992 /* TXD */
2993 RCAR_GP_PIN(1, 11),
2994};
2995static const unsigned int msiof2_txd_a_mux[] = {
2996 MSIOF2_TXD_A_MARK,
2997};
2998static const unsigned int msiof2_rxd_a_pins[] = {
2999 /* RXD */
3000 RCAR_GP_PIN(1, 10),
3001};
3002static const unsigned int msiof2_rxd_a_mux[] = {
3003 MSIOF2_RXD_A_MARK,
3004};
3005static const unsigned int msiof2_clk_b_pins[] = {
3006 /* SCK */
3007 RCAR_GP_PIN(0, 4),
3008};
3009static const unsigned int msiof2_clk_b_mux[] = {
3010 MSIOF2_SCK_B_MARK,
3011};
3012static const unsigned int msiof2_sync_b_pins[] = {
3013 /* SYNC */
3014 RCAR_GP_PIN(0, 5),
3015};
3016static const unsigned int msiof2_sync_b_mux[] = {
3017 MSIOF2_SYNC_B_MARK,
3018};
3019static const unsigned int msiof2_ss1_b_pins[] = {
3020 /* SS1 */
3021 RCAR_GP_PIN(0, 0),
3022};
3023static const unsigned int msiof2_ss1_b_mux[] = {
3024 MSIOF2_SS1_B_MARK,
3025};
3026static const unsigned int msiof2_ss2_b_pins[] = {
3027 /* SS2 */
3028 RCAR_GP_PIN(0, 1),
3029};
3030static const unsigned int msiof2_ss2_b_mux[] = {
3031 MSIOF2_SS2_B_MARK,
3032};
3033static const unsigned int msiof2_txd_b_pins[] = {
3034 /* TXD */
3035 RCAR_GP_PIN(0, 7),
3036};
3037static const unsigned int msiof2_txd_b_mux[] = {
3038 MSIOF2_TXD_B_MARK,
3039};
3040static const unsigned int msiof2_rxd_b_pins[] = {
3041 /* RXD */
3042 RCAR_GP_PIN(0, 6),
3043};
3044static const unsigned int msiof2_rxd_b_mux[] = {
3045 MSIOF2_RXD_B_MARK,
3046};
3047static const unsigned int msiof2_clk_c_pins[] = {
3048 /* SCK */
3049 RCAR_GP_PIN(2, 12),
3050};
3051static const unsigned int msiof2_clk_c_mux[] = {
3052 MSIOF2_SCK_C_MARK,
3053};
3054static const unsigned int msiof2_sync_c_pins[] = {
3055 /* SYNC */
3056 RCAR_GP_PIN(2, 11),
3057};
3058static const unsigned int msiof2_sync_c_mux[] = {
3059 MSIOF2_SYNC_C_MARK,
3060};
3061static const unsigned int msiof2_ss1_c_pins[] = {
3062 /* SS1 */
3063 RCAR_GP_PIN(2, 10),
3064};
3065static const unsigned int msiof2_ss1_c_mux[] = {
3066 MSIOF2_SS1_C_MARK,
3067};
3068static const unsigned int msiof2_ss2_c_pins[] = {
3069 /* SS2 */
3070 RCAR_GP_PIN(2, 9),
3071};
3072static const unsigned int msiof2_ss2_c_mux[] = {
3073 MSIOF2_SS2_C_MARK,
3074};
3075static const unsigned int msiof2_txd_c_pins[] = {
3076 /* TXD */
3077 RCAR_GP_PIN(2, 14),
3078};
3079static const unsigned int msiof2_txd_c_mux[] = {
3080 MSIOF2_TXD_C_MARK,
3081};
3082static const unsigned int msiof2_rxd_c_pins[] = {
3083 /* RXD */
3084 RCAR_GP_PIN(2, 13),
3085};
3086static const unsigned int msiof2_rxd_c_mux[] = {
3087 MSIOF2_RXD_C_MARK,
3088};
3089static const unsigned int msiof2_clk_d_pins[] = {
3090 /* SCK */
3091 RCAR_GP_PIN(0, 8),
3092};
3093static const unsigned int msiof2_clk_d_mux[] = {
3094 MSIOF2_SCK_D_MARK,
3095};
3096static const unsigned int msiof2_sync_d_pins[] = {
3097 /* SYNC */
3098 RCAR_GP_PIN(0, 9),
3099};
3100static const unsigned int msiof2_sync_d_mux[] = {
3101 MSIOF2_SYNC_D_MARK,
3102};
3103static const unsigned int msiof2_ss1_d_pins[] = {
3104 /* SS1 */
3105 RCAR_GP_PIN(0, 12),
3106};
3107static const unsigned int msiof2_ss1_d_mux[] = {
3108 MSIOF2_SS1_D_MARK,
3109};
3110static const unsigned int msiof2_ss2_d_pins[] = {
3111 /* SS2 */
3112 RCAR_GP_PIN(0, 13),
3113};
3114static const unsigned int msiof2_ss2_d_mux[] = {
3115 MSIOF2_SS2_D_MARK,
3116};
3117static const unsigned int msiof2_txd_d_pins[] = {
3118 /* TXD */
3119 RCAR_GP_PIN(0, 11),
3120};
3121static const unsigned int msiof2_txd_d_mux[] = {
3122 MSIOF2_TXD_D_MARK,
3123};
3124static const unsigned int msiof2_rxd_d_pins[] = {
3125 /* RXD */
3126 RCAR_GP_PIN(0, 10),
3127};
3128static const unsigned int msiof2_rxd_d_mux[] = {
3129 MSIOF2_RXD_D_MARK,
3130};
3131/* - MSIOF3 ----------------------------------------------------------------- */
3132static const unsigned int msiof3_clk_a_pins[] = {
3133 /* SCK */
3134 RCAR_GP_PIN(0, 0),
3135};
3136static const unsigned int msiof3_clk_a_mux[] = {
3137 MSIOF3_SCK_A_MARK,
3138};
3139static const unsigned int msiof3_sync_a_pins[] = {
3140 /* SYNC */
3141 RCAR_GP_PIN(0, 1),
3142};
3143static const unsigned int msiof3_sync_a_mux[] = {
3144 MSIOF3_SYNC_A_MARK,
3145};
3146static const unsigned int msiof3_ss1_a_pins[] = {
3147 /* SS1 */
3148 RCAR_GP_PIN(0, 14),
3149};
3150static const unsigned int msiof3_ss1_a_mux[] = {
3151 MSIOF3_SS1_A_MARK,
3152};
3153static const unsigned int msiof3_ss2_a_pins[] = {
3154 /* SS2 */
3155 RCAR_GP_PIN(0, 15),
3156};
3157static const unsigned int msiof3_ss2_a_mux[] = {
3158 MSIOF3_SS2_A_MARK,
3159};
3160static const unsigned int msiof3_txd_a_pins[] = {
3161 /* TXD */
3162 RCAR_GP_PIN(0, 3),
3163};
3164static const unsigned int msiof3_txd_a_mux[] = {
3165 MSIOF3_TXD_A_MARK,
3166};
3167static const unsigned int msiof3_rxd_a_pins[] = {
3168 /* RXD */
3169 RCAR_GP_PIN(0, 2),
3170};
3171static const unsigned int msiof3_rxd_a_mux[] = {
3172 MSIOF3_RXD_A_MARK,
3173};
3174static const unsigned int msiof3_clk_b_pins[] = {
3175 /* SCK */
3176 RCAR_GP_PIN(1, 2),
3177};
3178static const unsigned int msiof3_clk_b_mux[] = {
3179 MSIOF3_SCK_B_MARK,
3180};
3181static const unsigned int msiof3_sync_b_pins[] = {
3182 /* SYNC */
3183 RCAR_GP_PIN(1, 0),
3184};
3185static const unsigned int msiof3_sync_b_mux[] = {
3186 MSIOF3_SYNC_B_MARK,
3187};
3188static const unsigned int msiof3_ss1_b_pins[] = {
3189 /* SS1 */
3190 RCAR_GP_PIN(1, 4),
3191};
3192static const unsigned int msiof3_ss1_b_mux[] = {
3193 MSIOF3_SS1_B_MARK,
3194};
3195static const unsigned int msiof3_ss2_b_pins[] = {
3196 /* SS2 */
3197 RCAR_GP_PIN(1, 5),
3198};
3199static const unsigned int msiof3_ss2_b_mux[] = {
3200 MSIOF3_SS2_B_MARK,
3201};
3202static const unsigned int msiof3_txd_b_pins[] = {
3203 /* TXD */
3204 RCAR_GP_PIN(1, 1),
3205};
3206static const unsigned int msiof3_txd_b_mux[] = {
3207 MSIOF3_TXD_B_MARK,
3208};
3209static const unsigned int msiof3_rxd_b_pins[] = {
3210 /* RXD */
3211 RCAR_GP_PIN(1, 3),
3212};
3213static const unsigned int msiof3_rxd_b_mux[] = {
3214 MSIOF3_RXD_B_MARK,
3215};
3216static const unsigned int msiof3_clk_c_pins[] = {
3217 /* SCK */
3218 RCAR_GP_PIN(1, 12),
3219};
3220static const unsigned int msiof3_clk_c_mux[] = {
3221 MSIOF3_SCK_C_MARK,
3222};
3223static const unsigned int msiof3_sync_c_pins[] = {
3224 /* SYNC */
3225 RCAR_GP_PIN(1, 13),
3226};
3227static const unsigned int msiof3_sync_c_mux[] = {
3228 MSIOF3_SYNC_C_MARK,
3229};
3230static const unsigned int msiof3_txd_c_pins[] = {
3231 /* TXD */
3232 RCAR_GP_PIN(1, 15),
3233};
3234static const unsigned int msiof3_txd_c_mux[] = {
3235 MSIOF3_TXD_C_MARK,
3236};
3237static const unsigned int msiof3_rxd_c_pins[] = {
3238 /* RXD */
3239 RCAR_GP_PIN(1, 14),
3240};
3241static const unsigned int msiof3_rxd_c_mux[] = {
3242 MSIOF3_RXD_C_MARK,
3243};
3244static const unsigned int msiof3_clk_d_pins[] = {
3245 /* SCK */
3246 RCAR_GP_PIN(1, 22),
3247};
3248static const unsigned int msiof3_clk_d_mux[] = {
3249 MSIOF3_SCK_D_MARK,
3250};
3251static const unsigned int msiof3_sync_d_pins[] = {
3252 /* SYNC */
3253 RCAR_GP_PIN(1, 23),
3254};
3255static const unsigned int msiof3_sync_d_mux[] = {
3256 MSIOF3_SYNC_D_MARK,
3257};
3258static const unsigned int msiof3_ss1_d_pins[] = {
3259 /* SS1 */
3260 RCAR_GP_PIN(1, 26),
3261};
3262static const unsigned int msiof3_ss1_d_mux[] = {
3263 MSIOF3_SS1_D_MARK,
3264};
3265static const unsigned int msiof3_txd_d_pins[] = {
3266 /* TXD */
3267 RCAR_GP_PIN(1, 25),
3268};
3269static const unsigned int msiof3_txd_d_mux[] = {
3270 MSIOF3_TXD_D_MARK,
3271};
3272static const unsigned int msiof3_rxd_d_pins[] = {
3273 /* RXD */
3274 RCAR_GP_PIN(1, 24),
3275};
3276static const unsigned int msiof3_rxd_d_mux[] = {
3277 MSIOF3_RXD_D_MARK,
3278};
3279static const unsigned int msiof3_clk_e_pins[] = {
3280 /* SCK */
3281 RCAR_GP_PIN(2, 3),
3282};
3283static const unsigned int msiof3_clk_e_mux[] = {
3284 MSIOF3_SCK_E_MARK,
3285};
3286static const unsigned int msiof3_sync_e_pins[] = {
3287 /* SYNC */
3288 RCAR_GP_PIN(2, 2),
3289};
3290static const unsigned int msiof3_sync_e_mux[] = {
3291 MSIOF3_SYNC_E_MARK,
3292};
3293static const unsigned int msiof3_ss1_e_pins[] = {
3294 /* SS1 */
3295 RCAR_GP_PIN(2, 1),
3296};
3297static const unsigned int msiof3_ss1_e_mux[] = {
3298 MSIOF3_SS1_E_MARK,
3299};
3300static const unsigned int msiof3_ss2_e_pins[] = {
3301 /* SS2 */
3302 RCAR_GP_PIN(2, 0),
3303};
3304static const unsigned int msiof3_ss2_e_mux[] = {
3305 MSIOF3_SS2_E_MARK,
3306};
3307static const unsigned int msiof3_txd_e_pins[] = {
3308 /* TXD */
3309 RCAR_GP_PIN(2, 5),
3310};
3311static const unsigned int msiof3_txd_e_mux[] = {
3312 MSIOF3_TXD_E_MARK,
3313};
3314static const unsigned int msiof3_rxd_e_pins[] = {
3315 /* RXD */
3316 RCAR_GP_PIN(2, 4),
3317};
3318static const unsigned int msiof3_rxd_e_mux[] = {
3319 MSIOF3_RXD_E_MARK,
3320};
3321
3322/* - PWM0 --------------------------------------------------------------------*/
3323static const unsigned int pwm0_pins[] = {
3324 /* PWM */
3325 RCAR_GP_PIN(2, 6),
3326};
3327static const unsigned int pwm0_mux[] = {
3328 PWM0_MARK,
3329};
3330/* - PWM1 --------------------------------------------------------------------*/
3331static const unsigned int pwm1_a_pins[] = {
3332 /* PWM */
3333 RCAR_GP_PIN(2, 7),
3334};
3335static const unsigned int pwm1_a_mux[] = {
3336 PWM1_A_MARK,
3337};
3338static const unsigned int pwm1_b_pins[] = {
3339 /* PWM */
3340 RCAR_GP_PIN(1, 8),
3341};
3342static const unsigned int pwm1_b_mux[] = {
3343 PWM1_B_MARK,
3344};
3345/* - PWM2 --------------------------------------------------------------------*/
3346static const unsigned int pwm2_a_pins[] = {
3347 /* PWM */
3348 RCAR_GP_PIN(2, 8),
3349};
3350static const unsigned int pwm2_a_mux[] = {
3351 PWM2_A_MARK,
3352};
3353static const unsigned int pwm2_b_pins[] = {
3354 /* PWM */
3355 RCAR_GP_PIN(1, 11),
3356};
3357static const unsigned int pwm2_b_mux[] = {
3358 PWM2_B_MARK,
3359};
3360/* - PWM3 --------------------------------------------------------------------*/
3361static const unsigned int pwm3_a_pins[] = {
3362 /* PWM */
3363 RCAR_GP_PIN(1, 0),
3364};
3365static const unsigned int pwm3_a_mux[] = {
3366 PWM3_A_MARK,
3367};
3368static const unsigned int pwm3_b_pins[] = {
3369 /* PWM */
3370 RCAR_GP_PIN(2, 2),
3371};
3372static const unsigned int pwm3_b_mux[] = {
3373 PWM3_B_MARK,
3374};
3375/* - PWM4 --------------------------------------------------------------------*/
3376static const unsigned int pwm4_a_pins[] = {
3377 /* PWM */
3378 RCAR_GP_PIN(1, 1),
3379};
3380static const unsigned int pwm4_a_mux[] = {
3381 PWM4_A_MARK,
3382};
3383static const unsigned int pwm4_b_pins[] = {
3384 /* PWM */
3385 RCAR_GP_PIN(2, 3),
3386};
3387static const unsigned int pwm4_b_mux[] = {
3388 PWM4_B_MARK,
3389};
3390/* - PWM5 --------------------------------------------------------------------*/
3391static const unsigned int pwm5_a_pins[] = {
3392 /* PWM */
3393 RCAR_GP_PIN(1, 2),
3394};
3395static const unsigned int pwm5_a_mux[] = {
3396 PWM5_A_MARK,
3397};
3398static const unsigned int pwm5_b_pins[] = {
3399 /* PWM */
3400 RCAR_GP_PIN(2, 4),
3401};
3402static const unsigned int pwm5_b_mux[] = {
3403 PWM5_B_MARK,
3404};
3405/* - PWM6 --------------------------------------------------------------------*/
3406static const unsigned int pwm6_a_pins[] = {
3407 /* PWM */
3408 RCAR_GP_PIN(1, 3),
3409};
3410static const unsigned int pwm6_a_mux[] = {
3411 PWM6_A_MARK,
3412};
3413static const unsigned int pwm6_b_pins[] = {
3414 /* PWM */
3415 RCAR_GP_PIN(2, 5),
3416};
3417static const unsigned int pwm6_b_mux[] = {
3418 PWM6_B_MARK,
3419};
3420
3421/* - SATA --------------------------------------------------------------------*/
3422static const unsigned int sata0_devslp_a_pins[] = {
3423 /* DEVSLP */
3424 RCAR_GP_PIN(6, 16),
3425};
3426
3427static const unsigned int sata0_devslp_a_mux[] = {
3428 SATA_DEVSLP_A_MARK,
3429};
3430
3431static const unsigned int sata0_devslp_b_pins[] = {
3432 /* DEVSLP */
3433 RCAR_GP_PIN(4, 6),
3434};
3435
3436static const unsigned int sata0_devslp_b_mux[] = {
3437 SATA_DEVSLP_B_MARK,
3438};
3439
3440/* - SCIF0 ------------------------------------------------------------------ */
3441static const unsigned int scif0_data_pins[] = {
3442 /* RX, TX */
3443 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3444};
3445static const unsigned int scif0_data_mux[] = {
3446 RX0_MARK, TX0_MARK,
3447};
3448static const unsigned int scif0_clk_pins[] = {
3449 /* SCK */
3450 RCAR_GP_PIN(5, 0),
3451};
3452static const unsigned int scif0_clk_mux[] = {
3453 SCK0_MARK,
3454};
3455static const unsigned int scif0_ctrl_pins[] = {
3456 /* RTS, CTS */
3457 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3458};
3459static const unsigned int scif0_ctrl_mux[] = {
3460 RTS0_N_MARK, CTS0_N_MARK,
3461};
3462/* - SCIF1 ------------------------------------------------------------------ */
3463static const unsigned int scif1_data_a_pins[] = {
3464 /* RX, TX */
3465 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3466};
3467static const unsigned int scif1_data_a_mux[] = {
3468 RX1_A_MARK, TX1_A_MARK,
3469};
3470static const unsigned int scif1_clk_pins[] = {
3471 /* SCK */
3472 RCAR_GP_PIN(6, 21),
3473};
3474static const unsigned int scif1_clk_mux[] = {
3475 SCK1_MARK,
3476};
3477static const unsigned int scif1_ctrl_pins[] = {
3478 /* RTS, CTS */
3479 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3480};
3481static const unsigned int scif1_ctrl_mux[] = {
3482 RTS1_N_MARK, CTS1_N_MARK,
3483};
3484static const unsigned int scif1_data_b_pins[] = {
3485 /* RX, TX */
3486 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3487};
3488static const unsigned int scif1_data_b_mux[] = {
3489 RX1_B_MARK, TX1_B_MARK,
3490};
3491/* - SCIF2 ------------------------------------------------------------------ */
3492static const unsigned int scif2_data_a_pins[] = {
3493 /* RX, TX */
3494 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3495};
3496static const unsigned int scif2_data_a_mux[] = {
3497 RX2_A_MARK, TX2_A_MARK,
3498};
3499static const unsigned int scif2_clk_pins[] = {
3500 /* SCK */
3501 RCAR_GP_PIN(5, 9),
3502};
3503static const unsigned int scif2_clk_mux[] = {
3504 SCK2_MARK,
3505};
3506static const unsigned int scif2_data_b_pins[] = {
3507 /* RX, TX */
3508 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3509};
3510static const unsigned int scif2_data_b_mux[] = {
3511 RX2_B_MARK, TX2_B_MARK,
3512};
3513/* - SCIF3 ------------------------------------------------------------------ */
3514static const unsigned int scif3_data_a_pins[] = {
3515 /* RX, TX */
3516 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3517};
3518static const unsigned int scif3_data_a_mux[] = {
3519 RX3_A_MARK, TX3_A_MARK,
3520};
3521static const unsigned int scif3_clk_pins[] = {
3522 /* SCK */
3523 RCAR_GP_PIN(1, 22),
3524};
3525static const unsigned int scif3_clk_mux[] = {
3526 SCK3_MARK,
3527};
3528static const unsigned int scif3_ctrl_pins[] = {
3529 /* RTS, CTS */
3530 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3531};
3532static const unsigned int scif3_ctrl_mux[] = {
3533 RTS3_N_MARK, CTS3_N_MARK,
3534};
3535static const unsigned int scif3_data_b_pins[] = {
3536 /* RX, TX */
3537 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3538};
3539static const unsigned int scif3_data_b_mux[] = {
3540 RX3_B_MARK, TX3_B_MARK,
3541};
3542/* - SCIF4 ------------------------------------------------------------------ */
3543static const unsigned int scif4_data_a_pins[] = {
3544 /* RX, TX */
3545 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3546};
3547static const unsigned int scif4_data_a_mux[] = {
3548 RX4_A_MARK, TX4_A_MARK,
3549};
3550static const unsigned int scif4_clk_a_pins[] = {
3551 /* SCK */
3552 RCAR_GP_PIN(2, 10),
3553};
3554static const unsigned int scif4_clk_a_mux[] = {
3555 SCK4_A_MARK,
3556};
3557static const unsigned int scif4_ctrl_a_pins[] = {
3558 /* RTS, CTS */
3559 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3560};
3561static const unsigned int scif4_ctrl_a_mux[] = {
3562 RTS4_N_A_MARK, CTS4_N_A_MARK,
3563};
3564static const unsigned int scif4_data_b_pins[] = {
3565 /* RX, TX */
3566 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3567};
3568static const unsigned int scif4_data_b_mux[] = {
3569 RX4_B_MARK, TX4_B_MARK,
3570};
3571static const unsigned int scif4_clk_b_pins[] = {
3572 /* SCK */
3573 RCAR_GP_PIN(1, 5),
3574};
3575static const unsigned int scif4_clk_b_mux[] = {
3576 SCK4_B_MARK,
3577};
3578static const unsigned int scif4_ctrl_b_pins[] = {
3579 /* RTS, CTS */
3580 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3581};
3582static const unsigned int scif4_ctrl_b_mux[] = {
3583 RTS4_N_B_MARK, CTS4_N_B_MARK,
3584};
3585static const unsigned int scif4_data_c_pins[] = {
3586 /* RX, TX */
3587 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3588};
3589static const unsigned int scif4_data_c_mux[] = {
3590 RX4_C_MARK, TX4_C_MARK,
3591};
3592static const unsigned int scif4_clk_c_pins[] = {
3593 /* SCK */
3594 RCAR_GP_PIN(0, 8),
3595};
3596static const unsigned int scif4_clk_c_mux[] = {
3597 SCK4_C_MARK,
3598};
3599static const unsigned int scif4_ctrl_c_pins[] = {
3600 /* RTS, CTS */
3601 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3602};
3603static const unsigned int scif4_ctrl_c_mux[] = {
3604 RTS4_N_C_MARK, CTS4_N_C_MARK,
3605};
3606/* - SCIF5 ------------------------------------------------------------------ */
3607static const unsigned int scif5_data_a_pins[] = {
3608 /* RX, TX */
3609 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3610};
3611static const unsigned int scif5_data_a_mux[] = {
3612 RX5_A_MARK, TX5_A_MARK,
3613};
3614static const unsigned int scif5_clk_a_pins[] = {
3615 /* SCK */
3616 RCAR_GP_PIN(6, 21),
3617};
3618static const unsigned int scif5_clk_a_mux[] = {
3619 SCK5_A_MARK,
3620};
3621static const unsigned int scif5_data_b_pins[] = {
3622 /* RX, TX */
3623 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3624};
3625static const unsigned int scif5_data_b_mux[] = {
3626 RX5_B_MARK, TX5_B_MARK,
3627};
3628static const unsigned int scif5_clk_b_pins[] = {
3629 /* SCK */
3630 RCAR_GP_PIN(5, 0),
3631};
3632static const unsigned int scif5_clk_b_mux[] = {
3633 SCK5_B_MARK,
3634};
3635/* - SCIF Clock ------------------------------------------------------------- */
3636static const unsigned int scif_clk_a_pins[] = {
3637 /* SCIF_CLK */
3638 RCAR_GP_PIN(6, 23),
3639};
3640static const unsigned int scif_clk_a_mux[] = {
3641 SCIF_CLK_A_MARK,
3642};
3643static const unsigned int scif_clk_b_pins[] = {
3644 /* SCIF_CLK */
3645 RCAR_GP_PIN(5, 9),
3646};
3647static const unsigned int scif_clk_b_mux[] = {
3648 SCIF_CLK_B_MARK,
3649};
3650
3651/* - SDHI0 ------------------------------------------------------------------ */
3652static const unsigned int sdhi0_data1_pins[] = {
3653 /* D0 */
3654 RCAR_GP_PIN(3, 2),
3655};
3656
3657static const unsigned int sdhi0_data1_mux[] = {
3658 SD0_DAT0_MARK,
3659};
3660
3661static const unsigned int sdhi0_data4_pins[] = {
3662 /* D[0:3] */
3663 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3664 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3665};
3666
3667static const unsigned int sdhi0_data4_mux[] = {
3668 SD0_DAT0_MARK, SD0_DAT1_MARK,
3669 SD0_DAT2_MARK, SD0_DAT3_MARK,
3670};
3671
3672static const unsigned int sdhi0_ctrl_pins[] = {
3673 /* CLK, CMD */
3674 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3675};
3676
3677static const unsigned int sdhi0_ctrl_mux[] = {
3678 SD0_CLK_MARK, SD0_CMD_MARK,
3679};
3680
3681static const unsigned int sdhi0_cd_pins[] = {
3682 /* CD */
3683 RCAR_GP_PIN(3, 12),
3684};
3685
3686static const unsigned int sdhi0_cd_mux[] = {
3687 SD0_CD_MARK,
3688};
3689
3690static const unsigned int sdhi0_wp_pins[] = {
3691 /* WP */
3692 RCAR_GP_PIN(3, 13),
3693};
3694
3695static const unsigned int sdhi0_wp_mux[] = {
3696 SD0_WP_MARK,
3697};
3698
3699/* - SDHI1 ------------------------------------------------------------------ */
3700static const unsigned int sdhi1_data1_pins[] = {
3701 /* D0 */
3702 RCAR_GP_PIN(3, 8),
3703};
3704
3705static const unsigned int sdhi1_data1_mux[] = {
3706 SD1_DAT0_MARK,
3707};
3708
3709static const unsigned int sdhi1_data4_pins[] = {
3710 /* D[0:3] */
3711 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3712 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3713};
3714
3715static const unsigned int sdhi1_data4_mux[] = {
3716 SD1_DAT0_MARK, SD1_DAT1_MARK,
3717 SD1_DAT2_MARK, SD1_DAT3_MARK,
3718};
3719
3720static const unsigned int sdhi1_ctrl_pins[] = {
3721 /* CLK, CMD */
3722 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3723};
3724
3725static const unsigned int sdhi1_ctrl_mux[] = {
3726 SD1_CLK_MARK, SD1_CMD_MARK,
3727};
3728
3729static const unsigned int sdhi1_cd_pins[] = {
3730 /* CD */
3731 RCAR_GP_PIN(3, 14),
3732};
3733
3734static const unsigned int sdhi1_cd_mux[] = {
3735 SD1_CD_MARK,
3736};
3737
3738static const unsigned int sdhi1_wp_pins[] = {
3739 /* WP */
3740 RCAR_GP_PIN(3, 15),
3741};
3742
3743static const unsigned int sdhi1_wp_mux[] = {
3744 SD1_WP_MARK,
3745};
3746
3747/* - SDHI2 ------------------------------------------------------------------ */
3748static const unsigned int sdhi2_data1_pins[] = {
3749 /* D0 */
3750 RCAR_GP_PIN(4, 2),
3751};
3752
3753static const unsigned int sdhi2_data1_mux[] = {
3754 SD2_DAT0_MARK,
3755};
3756
3757static const unsigned int sdhi2_data4_pins[] = {
3758 /* D[0:3] */
3759 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3760 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3761};
3762
3763static const unsigned int sdhi2_data4_mux[] = {
3764 SD2_DAT0_MARK, SD2_DAT1_MARK,
3765 SD2_DAT2_MARK, SD2_DAT3_MARK,
3766};
3767
3768static const unsigned int sdhi2_data8_pins[] = {
3769 /* D[0:7] */
3770 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3771 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3772 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3773 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3774};
3775
3776static const unsigned int sdhi2_data8_mux[] = {
3777 SD2_DAT0_MARK, SD2_DAT1_MARK,
3778 SD2_DAT2_MARK, SD2_DAT3_MARK,
3779 SD2_DAT4_MARK, SD2_DAT5_MARK,
3780 SD2_DAT6_MARK, SD2_DAT7_MARK,
3781};
3782
3783static const unsigned int sdhi2_ctrl_pins[] = {
3784 /* CLK, CMD */
3785 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3786};
3787
3788static const unsigned int sdhi2_ctrl_mux[] = {
3789 SD2_CLK_MARK, SD2_CMD_MARK,
3790};
3791
3792static const unsigned int sdhi2_cd_a_pins[] = {
3793 /* CD */
3794 RCAR_GP_PIN(4, 13),
3795};
3796
3797static const unsigned int sdhi2_cd_a_mux[] = {
3798 SD2_CD_A_MARK,
3799};
3800
3801static const unsigned int sdhi2_cd_b_pins[] = {
3802 /* CD */
3803 RCAR_GP_PIN(5, 10),
3804};
3805
3806static const unsigned int sdhi2_cd_b_mux[] = {
3807 SD2_CD_B_MARK,
3808};
3809
3810static const unsigned int sdhi2_wp_a_pins[] = {
3811 /* WP */
3812 RCAR_GP_PIN(4, 14),
3813};
3814
3815static const unsigned int sdhi2_wp_a_mux[] = {
3816 SD2_WP_A_MARK,
3817};
3818
3819static const unsigned int sdhi2_wp_b_pins[] = {
3820 /* WP */
3821 RCAR_GP_PIN(5, 11),
3822};
3823
3824static const unsigned int sdhi2_wp_b_mux[] = {
3825 SD2_WP_B_MARK,
3826};
3827
3828static const unsigned int sdhi2_ds_pins[] = {
3829 /* DS */
3830 RCAR_GP_PIN(4, 6),
3831};
3832
3833static const unsigned int sdhi2_ds_mux[] = {
3834 SD2_DS_MARK,
3835};
3836
3837/* - SDHI3 ------------------------------------------------------------------ */
3838static const unsigned int sdhi3_data1_pins[] = {
3839 /* D0 */
3840 RCAR_GP_PIN(4, 9),
3841};
3842
3843static const unsigned int sdhi3_data1_mux[] = {
3844 SD3_DAT0_MARK,
3845};
3846
3847static const unsigned int sdhi3_data4_pins[] = {
3848 /* D[0:3] */
3849 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3850 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3851};
3852
3853static const unsigned int sdhi3_data4_mux[] = {
3854 SD3_DAT0_MARK, SD3_DAT1_MARK,
3855 SD3_DAT2_MARK, SD3_DAT3_MARK,
3856};
3857
3858static const unsigned int sdhi3_data8_pins[] = {
3859 /* D[0:7] */
3860 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3861 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3862 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3863 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3864};
3865
3866static const unsigned int sdhi3_data8_mux[] = {
3867 SD3_DAT0_MARK, SD3_DAT1_MARK,
3868 SD3_DAT2_MARK, SD3_DAT3_MARK,
3869 SD3_DAT4_MARK, SD3_DAT5_MARK,
3870 SD3_DAT6_MARK, SD3_DAT7_MARK,
3871};
3872
3873static const unsigned int sdhi3_ctrl_pins[] = {
3874 /* CLK, CMD */
3875 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3876};
3877
3878static const unsigned int sdhi3_ctrl_mux[] = {
3879 SD3_CLK_MARK, SD3_CMD_MARK,
3880};
3881
3882static const unsigned int sdhi3_cd_pins[] = {
3883 /* CD */
3884 RCAR_GP_PIN(4, 15),
3885};
3886
3887static const unsigned int sdhi3_cd_mux[] = {
3888 SD3_CD_MARK,
3889};
3890
3891static const unsigned int sdhi3_wp_pins[] = {
3892 /* WP */
3893 RCAR_GP_PIN(4, 16),
3894};
3895
3896static const unsigned int sdhi3_wp_mux[] = {
3897 SD3_WP_MARK,
3898};
3899
3900static const unsigned int sdhi3_ds_pins[] = {
3901 /* DS */
3902 RCAR_GP_PIN(4, 17),
3903};
3904
3905static const unsigned int sdhi3_ds_mux[] = {
3906 SD3_DS_MARK,
3907};
3908
3909/* - SSI -------------------------------------------------------------------- */
3910static const unsigned int ssi0_data_pins[] = {
3911 /* SDATA */
3912 RCAR_GP_PIN(6, 2),
3913};
3914static const unsigned int ssi0_data_mux[] = {
3915 SSI_SDATA0_MARK,
3916};
3917static const unsigned int ssi01239_ctrl_pins[] = {
3918 /* SCK, WS */
3919 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3920};
3921static const unsigned int ssi01239_ctrl_mux[] = {
3922 SSI_SCK01239_MARK, SSI_WS01239_MARK,
3923};
3924static const unsigned int ssi1_data_a_pins[] = {
3925 /* SDATA */
3926 RCAR_GP_PIN(6, 3),
3927};
3928static const unsigned int ssi1_data_a_mux[] = {
3929 SSI_SDATA1_A_MARK,
3930};
3931static const unsigned int ssi1_data_b_pins[] = {
3932 /* SDATA */
3933 RCAR_GP_PIN(5, 12),
3934};
3935static const unsigned int ssi1_data_b_mux[] = {
3936 SSI_SDATA1_B_MARK,
3937};
3938static const unsigned int ssi1_ctrl_a_pins[] = {
3939 /* SCK, WS */
3940 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3941};
3942static const unsigned int ssi1_ctrl_a_mux[] = {
3943 SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3944};
3945static const unsigned int ssi1_ctrl_b_pins[] = {
3946 /* SCK, WS */
3947 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3948};
3949static const unsigned int ssi1_ctrl_b_mux[] = {
3950 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3951};
3952static const unsigned int ssi2_data_a_pins[] = {
3953 /* SDATA */
3954 RCAR_GP_PIN(6, 4),
3955};
3956static const unsigned int ssi2_data_a_mux[] = {
3957 SSI_SDATA2_A_MARK,
3958};
3959static const unsigned int ssi2_data_b_pins[] = {
3960 /* SDATA */
3961 RCAR_GP_PIN(5, 13),
3962};
3963static const unsigned int ssi2_data_b_mux[] = {
3964 SSI_SDATA2_B_MARK,
3965};
3966static const unsigned int ssi2_ctrl_a_pins[] = {
3967 /* SCK, WS */
3968 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3969};
3970static const unsigned int ssi2_ctrl_a_mux[] = {
3971 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3972};
3973static const unsigned int ssi2_ctrl_b_pins[] = {
3974 /* SCK, WS */
3975 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3976};
3977static const unsigned int ssi2_ctrl_b_mux[] = {
3978 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3979};
3980static const unsigned int ssi3_data_pins[] = {
3981 /* SDATA */
3982 RCAR_GP_PIN(6, 7),
3983};
3984static const unsigned int ssi3_data_mux[] = {
3985 SSI_SDATA3_MARK,
3986};
3987static const unsigned int ssi349_ctrl_pins[] = {
3988 /* SCK, WS */
3989 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3990};
3991static const unsigned int ssi349_ctrl_mux[] = {
3992 SSI_SCK349_MARK, SSI_WS349_MARK,
3993};
3994static const unsigned int ssi4_data_pins[] = {
3995 /* SDATA */
3996 RCAR_GP_PIN(6, 10),
3997};
3998static const unsigned int ssi4_data_mux[] = {
3999 SSI_SDATA4_MARK,
4000};
4001static const unsigned int ssi4_ctrl_pins[] = {
4002 /* SCK, WS */
4003 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
4004};
4005static const unsigned int ssi4_ctrl_mux[] = {
4006 SSI_SCK4_MARK, SSI_WS4_MARK,
4007};
4008static const unsigned int ssi5_data_pins[] = {
4009 /* SDATA */
4010 RCAR_GP_PIN(6, 13),
4011};
4012static const unsigned int ssi5_data_mux[] = {
4013 SSI_SDATA5_MARK,
4014};
4015static const unsigned int ssi5_ctrl_pins[] = {
4016 /* SCK, WS */
4017 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
4018};
4019static const unsigned int ssi5_ctrl_mux[] = {
4020 SSI_SCK5_MARK, SSI_WS5_MARK,
4021};
4022static const unsigned int ssi6_data_pins[] = {
4023 /* SDATA */
4024 RCAR_GP_PIN(6, 16),
4025};
4026static const unsigned int ssi6_data_mux[] = {
4027 SSI_SDATA6_MARK,
4028};
4029static const unsigned int ssi6_ctrl_pins[] = {
4030 /* SCK, WS */
4031 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
4032};
4033static const unsigned int ssi6_ctrl_mux[] = {
4034 SSI_SCK6_MARK, SSI_WS6_MARK,
4035};
4036static const unsigned int ssi7_data_pins[] = {
4037 /* SDATA */
4038 RCAR_GP_PIN(6, 19),
4039};
4040static const unsigned int ssi7_data_mux[] = {
4041 SSI_SDATA7_MARK,
4042};
4043static const unsigned int ssi78_ctrl_pins[] = {
4044 /* SCK, WS */
4045 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
4046};
4047static const unsigned int ssi78_ctrl_mux[] = {
4048 SSI_SCK78_MARK, SSI_WS78_MARK,
4049};
4050static const unsigned int ssi8_data_pins[] = {
4051 /* SDATA */
4052 RCAR_GP_PIN(6, 20),
4053};
4054static const unsigned int ssi8_data_mux[] = {
4055 SSI_SDATA8_MARK,
4056};
4057static const unsigned int ssi9_data_a_pins[] = {
4058 /* SDATA */
4059 RCAR_GP_PIN(6, 21),
4060};
4061static const unsigned int ssi9_data_a_mux[] = {
4062 SSI_SDATA9_A_MARK,
4063};
4064static const unsigned int ssi9_data_b_pins[] = {
4065 /* SDATA */
4066 RCAR_GP_PIN(5, 14),
4067};
4068static const unsigned int ssi9_data_b_mux[] = {
4069 SSI_SDATA9_B_MARK,
4070};
4071static const unsigned int ssi9_ctrl_a_pins[] = {
4072 /* SCK, WS */
4073 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
4074};
4075static const unsigned int ssi9_ctrl_a_mux[] = {
4076 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
4077};
4078static const unsigned int ssi9_ctrl_b_pins[] = {
4079 /* SCK, WS */
4080 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
4081};
4082static const unsigned int ssi9_ctrl_b_mux[] = {
4083 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
4084};
4085
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4086/* - TMU -------------------------------------------------------------------- */
4087static const unsigned int tmu_tclk1_a_pins[] = {
4088 /* TCLK */
4089 RCAR_GP_PIN(6, 23),
4090};
4091
4092static const unsigned int tmu_tclk1_a_mux[] = {
4093 TCLK1_A_MARK,
4094};
4095
4096static const unsigned int tmu_tclk1_b_pins[] = {
4097 /* TCLK */
4098 RCAR_GP_PIN(5, 19),
4099};
4100
4101static const unsigned int tmu_tclk1_b_mux[] = {
4102 TCLK1_B_MARK,
4103};
4104
4105static const unsigned int tmu_tclk2_a_pins[] = {
4106 /* TCLK */
4107 RCAR_GP_PIN(6, 19),
4108};
4109
4110static const unsigned int tmu_tclk2_a_mux[] = {
4111 TCLK2_A_MARK,
4112};
4113
4114static const unsigned int tmu_tclk2_b_pins[] = {
4115 /* TCLK */
4116 RCAR_GP_PIN(6, 28),
4117};
4118
4119static const unsigned int tmu_tclk2_b_mux[] = {
4120 TCLK2_B_MARK,
4121};
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4122
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]4123/* - TPU ------------------------------------------------------------------- */
4124static const unsigned int tpu_to0_pins[] = {
4125 /* TPU0TO0 */
4126 RCAR_GP_PIN(6, 28),
4127};
4128static const unsigned int tpu_to0_mux[] = {
4129 TPU0TO0_MARK,
4130};
4131static const unsigned int tpu_to1_pins[] = {
4132 /* TPU0TO1 */
4133 RCAR_GP_PIN(6, 29),
4134};
4135static const unsigned int tpu_to1_mux[] = {
4136 TPU0TO1_MARK,
4137};
4138static const unsigned int tpu_to2_pins[] = {
4139 /* TPU0TO2 */
4140 RCAR_GP_PIN(6, 30),
4141};
4142static const unsigned int tpu_to2_mux[] = {
4143 TPU0TO2_MARK,
4144};
4145static const unsigned int tpu_to3_pins[] = {
4146 /* TPU0TO3 */
4147 RCAR_GP_PIN(6, 31),
4148};
4149static const unsigned int tpu_to3_mux[] = {
4150 TPU0TO3_MARK,
4151};
4152
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4153/* - USB0 ------------------------------------------------------------------- */
4154static const unsigned int usb0_pins[] = {
4155 /* PWEN, OVC */
4156 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
4157};
4158
4159static const unsigned int usb0_mux[] = {
4160 USB0_PWEN_MARK, USB0_OVC_MARK,
4161};
4162
4163/* - USB1 ------------------------------------------------------------------- */
4164static const unsigned int usb1_pins[] = {
4165 /* PWEN, OVC */
4166 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
4167};
4168
4169static const unsigned int usb1_mux[] = {
4170 USB1_PWEN_MARK, USB1_OVC_MARK,
4171};
4172
4173/* - USB30 ------------------------------------------------------------------ */
4174static const unsigned int usb30_pins[] = {
4175 /* PWEN, OVC */
4176 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
4177};
4178
4179static const unsigned int usb30_mux[] = {
4180 USB30_PWEN_MARK, USB30_OVC_MARK,
4181};
4182
4183/* - VIN4 ------------------------------------------------------------------- */
4184static const unsigned int vin4_data18_a_pins[] = {
4185 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
4186 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
4187 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
4188 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4189 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4190 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4191 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4192 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4193 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4194};
4195
4196static const unsigned int vin4_data18_a_mux[] = {
4197 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4198 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4199 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4200 VI4_DATA10_MARK, VI4_DATA11_MARK,
4201 VI4_DATA12_MARK, VI4_DATA13_MARK,
4202 VI4_DATA14_MARK, VI4_DATA15_MARK,
4203 VI4_DATA18_MARK, VI4_DATA19_MARK,
4204 VI4_DATA20_MARK, VI4_DATA21_MARK,
4205 VI4_DATA22_MARK, VI4_DATA23_MARK,
4206};
4207
4208static const union vin_data vin4_data_a_pins = {
4209 .data24 = {
4210 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
4211 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
4212 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
4213 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
4214 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4215 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4216 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4217 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4218 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4219 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4220 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4221 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4222 },
4223};
4224
4225static const union vin_data vin4_data_a_mux = {
4226 .data24 = {
4227 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
4228 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4229 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4230 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4231 VI4_DATA8_MARK, VI4_DATA9_MARK,
4232 VI4_DATA10_MARK, VI4_DATA11_MARK,
4233 VI4_DATA12_MARK, VI4_DATA13_MARK,
4234 VI4_DATA14_MARK, VI4_DATA15_MARK,
4235 VI4_DATA16_MARK, VI4_DATA17_MARK,
4236 VI4_DATA18_MARK, VI4_DATA19_MARK,
4237 VI4_DATA20_MARK, VI4_DATA21_MARK,
4238 VI4_DATA22_MARK, VI4_DATA23_MARK,
4239 },
4240};
4241
4242static const unsigned int vin4_data18_b_pins[] = {
4243 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4244 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4245 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4246 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4247 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4248 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4249 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4250 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4251 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4252};
4253
4254static const unsigned int vin4_data18_b_mux[] = {
4255 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4256 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4257 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4258 VI4_DATA10_MARK, VI4_DATA11_MARK,
4259 VI4_DATA12_MARK, VI4_DATA13_MARK,
4260 VI4_DATA14_MARK, VI4_DATA15_MARK,
4261 VI4_DATA18_MARK, VI4_DATA19_MARK,
4262 VI4_DATA20_MARK, VI4_DATA21_MARK,
4263 VI4_DATA22_MARK, VI4_DATA23_MARK,
4264};
4265
4266static const union vin_data vin4_data_b_pins = {
4267 .data24 = {
4268 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
4269 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4270 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4271 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4272 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4273 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4274 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4275 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4276 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4277 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4278 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4279 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4280 },
4281};
4282
4283static const union vin_data vin4_data_b_mux = {
4284 .data24 = {
4285 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
4286 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4287 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4288 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4289 VI4_DATA8_MARK, VI4_DATA9_MARK,
4290 VI4_DATA10_MARK, VI4_DATA11_MARK,
4291 VI4_DATA12_MARK, VI4_DATA13_MARK,
4292 VI4_DATA14_MARK, VI4_DATA15_MARK,
4293 VI4_DATA16_MARK, VI4_DATA17_MARK,
4294 VI4_DATA18_MARK, VI4_DATA19_MARK,
4295 VI4_DATA20_MARK, VI4_DATA21_MARK,
4296 VI4_DATA22_MARK, VI4_DATA23_MARK,
4297 },
4298};
4299
4300static const unsigned int vin4_sync_pins[] = {
4301 /* VSYNC_N, HSYNC_N */
4302 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
4303};
4304
4305static const unsigned int vin4_sync_mux[] = {
4306 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
4307};
4308
4309static const unsigned int vin4_field_pins[] = {
4310 RCAR_GP_PIN(1, 16),
4311};
4312
4313static const unsigned int vin4_field_mux[] = {
4314 VI4_FIELD_MARK,
4315};
4316
4317static const unsigned int vin4_clkenb_pins[] = {
4318 RCAR_GP_PIN(1, 19),
4319};
4320
4321static const unsigned int vin4_clkenb_mux[] = {
4322 VI4_CLKENB_MARK,
4323};
4324
4325static const unsigned int vin4_clk_pins[] = {
4326 RCAR_GP_PIN(1, 27),
4327};
4328
4329static const unsigned int vin4_clk_mux[] = {
4330 VI4_CLK_MARK,
4331};
4332
4333/* - VIN5 ------------------------------------------------------------------- */
4334static const union vin_data16 vin5_data_pins = {
4335 .data16 = {
4336 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4337 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4338 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4339 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4340 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4341 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4342 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4343 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4344 },
4345};
4346
4347static const union vin_data16 vin5_data_mux = {
4348 .data16 = {
4349 VI5_DATA0_MARK, VI5_DATA1_MARK,
4350 VI5_DATA2_MARK, VI5_DATA3_MARK,
4351 VI5_DATA4_MARK, VI5_DATA5_MARK,
4352 VI5_DATA6_MARK, VI5_DATA7_MARK,
4353 VI5_DATA8_MARK, VI5_DATA9_MARK,
4354 VI5_DATA10_MARK, VI5_DATA11_MARK,
4355 VI5_DATA12_MARK, VI5_DATA13_MARK,
4356 VI5_DATA14_MARK, VI5_DATA15_MARK,
4357 },
4358};
4359
4360static const unsigned int vin5_sync_pins[] = {
4361 /* VSYNC_N, HSYNC_N */
4362 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
4363};
4364
4365static const unsigned int vin5_sync_mux[] = {
4366 VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
4367};
4368
4369static const unsigned int vin5_field_pins[] = {
4370 RCAR_GP_PIN(1, 11),
4371};
4372
4373static const unsigned int vin5_field_mux[] = {
4374 VI5_FIELD_MARK,
4375};
4376
4377static const unsigned int vin5_clkenb_pins[] = {
4378 RCAR_GP_PIN(1, 20),
4379};
4380
4381static const unsigned int vin5_clkenb_mux[] = {
4382 VI5_CLKENB_MARK,
4383};
4384
4385static const unsigned int vin5_clk_pins[] = {
4386 RCAR_GP_PIN(1, 21),
4387};
4388
4389static const unsigned int vin5_clk_mux[] = {
4390 VI5_CLK_MARK,
4391};
4392
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]4393static const struct {
4394 struct sh_pfc_pin_group common[318];
Biju Das0a362702020-10-28 10:34:24 +0000[diff] [blame^]4395#ifdef CONFIG_PINCTRL_PFC_R8A77965
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]4396 struct sh_pfc_pin_group automotive[30];
Biju Das0a362702020-10-28 10:34:24 +0000[diff] [blame^]4397#endif
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]4398} pinmux_groups = {
4399 .common = {
4400 SH_PFC_PIN_GROUP(audio_clk_a_a),
4401 SH_PFC_PIN_GROUP(audio_clk_a_b),
4402 SH_PFC_PIN_GROUP(audio_clk_a_c),
4403 SH_PFC_PIN_GROUP(audio_clk_b_a),
4404 SH_PFC_PIN_GROUP(audio_clk_b_b),
4405 SH_PFC_PIN_GROUP(audio_clk_c_a),
4406 SH_PFC_PIN_GROUP(audio_clk_c_b),
4407 SH_PFC_PIN_GROUP(audio_clkout_a),
4408 SH_PFC_PIN_GROUP(audio_clkout_b),
4409 SH_PFC_PIN_GROUP(audio_clkout_c),
4410 SH_PFC_PIN_GROUP(audio_clkout_d),
4411 SH_PFC_PIN_GROUP(audio_clkout1_a),
4412 SH_PFC_PIN_GROUP(audio_clkout1_b),
4413 SH_PFC_PIN_GROUP(audio_clkout2_a),
4414 SH_PFC_PIN_GROUP(audio_clkout2_b),
4415 SH_PFC_PIN_GROUP(audio_clkout3_a),
4416 SH_PFC_PIN_GROUP(audio_clkout3_b),
4417 SH_PFC_PIN_GROUP(avb_link),
4418 SH_PFC_PIN_GROUP(avb_magic),
4419 SH_PFC_PIN_GROUP(avb_phy_int),
4420 SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
4421 SH_PFC_PIN_GROUP(avb_mdio),
4422 SH_PFC_PIN_GROUP(avb_mii),
4423 SH_PFC_PIN_GROUP(avb_avtp_pps),
4424 SH_PFC_PIN_GROUP(avb_avtp_match_a),
4425 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
4426 SH_PFC_PIN_GROUP(avb_avtp_match_b),
4427 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
4428 SH_PFC_PIN_GROUP(can0_data_a),
4429 SH_PFC_PIN_GROUP(can0_data_b),
4430 SH_PFC_PIN_GROUP(can1_data),
4431 SH_PFC_PIN_GROUP(can_clk),
4432 SH_PFC_PIN_GROUP(canfd0_data_a),
4433 SH_PFC_PIN_GROUP(canfd0_data_b),
4434 SH_PFC_PIN_GROUP(canfd1_data),
4435 SH_PFC_PIN_GROUP(du_rgb666),
4436 SH_PFC_PIN_GROUP(du_rgb888),
4437 SH_PFC_PIN_GROUP(du_clk_out_0),
4438 SH_PFC_PIN_GROUP(du_clk_out_1),
4439 SH_PFC_PIN_GROUP(du_sync),
4440 SH_PFC_PIN_GROUP(du_oddf),
4441 SH_PFC_PIN_GROUP(du_cde),
4442 SH_PFC_PIN_GROUP(du_disp),
4443 SH_PFC_PIN_GROUP(hscif0_data),
4444 SH_PFC_PIN_GROUP(hscif0_clk),
4445 SH_PFC_PIN_GROUP(hscif0_ctrl),
4446 SH_PFC_PIN_GROUP(hscif1_data_a),
4447 SH_PFC_PIN_GROUP(hscif1_clk_a),
4448 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
4449 SH_PFC_PIN_GROUP(hscif1_data_b),
4450 SH_PFC_PIN_GROUP(hscif1_clk_b),
4451 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
4452 SH_PFC_PIN_GROUP(hscif2_data_a),
4453 SH_PFC_PIN_GROUP(hscif2_clk_a),
4454 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
4455 SH_PFC_PIN_GROUP(hscif2_data_b),
4456 SH_PFC_PIN_GROUP(hscif2_clk_b),
4457 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4458 SH_PFC_PIN_GROUP(hscif2_data_c),
4459 SH_PFC_PIN_GROUP(hscif2_clk_c),
4460 SH_PFC_PIN_GROUP(hscif2_ctrl_c),
4461 SH_PFC_PIN_GROUP(hscif3_data_a),
4462 SH_PFC_PIN_GROUP(hscif3_clk),
4463 SH_PFC_PIN_GROUP(hscif3_ctrl),
4464 SH_PFC_PIN_GROUP(hscif3_data_b),
4465 SH_PFC_PIN_GROUP(hscif3_data_c),
4466 SH_PFC_PIN_GROUP(hscif3_data_d),
4467 SH_PFC_PIN_GROUP(hscif4_data_a),
4468 SH_PFC_PIN_GROUP(hscif4_clk),
4469 SH_PFC_PIN_GROUP(hscif4_ctrl),
4470 SH_PFC_PIN_GROUP(hscif4_data_b),
4471 SH_PFC_PIN_GROUP(i2c0),
4472 SH_PFC_PIN_GROUP(i2c1_a),
4473 SH_PFC_PIN_GROUP(i2c1_b),
4474 SH_PFC_PIN_GROUP(i2c2_a),
4475 SH_PFC_PIN_GROUP(i2c2_b),
4476 SH_PFC_PIN_GROUP(i2c3),
4477 SH_PFC_PIN_GROUP(i2c5),
4478 SH_PFC_PIN_GROUP(i2c6_a),
4479 SH_PFC_PIN_GROUP(i2c6_b),
4480 SH_PFC_PIN_GROUP(i2c6_c),
4481 SH_PFC_PIN_GROUP(intc_ex_irq0),
4482 SH_PFC_PIN_GROUP(intc_ex_irq1),
4483 SH_PFC_PIN_GROUP(intc_ex_irq2),
4484 SH_PFC_PIN_GROUP(intc_ex_irq3),
4485 SH_PFC_PIN_GROUP(intc_ex_irq4),
4486 SH_PFC_PIN_GROUP(intc_ex_irq5),
4487 SH_PFC_PIN_GROUP(msiof0_clk),
4488 SH_PFC_PIN_GROUP(msiof0_sync),
4489 SH_PFC_PIN_GROUP(msiof0_ss1),
4490 SH_PFC_PIN_GROUP(msiof0_ss2),
4491 SH_PFC_PIN_GROUP(msiof0_txd),
4492 SH_PFC_PIN_GROUP(msiof0_rxd),
4493 SH_PFC_PIN_GROUP(msiof1_clk_a),
4494 SH_PFC_PIN_GROUP(msiof1_sync_a),
4495 SH_PFC_PIN_GROUP(msiof1_ss1_a),
4496 SH_PFC_PIN_GROUP(msiof1_ss2_a),
4497 SH_PFC_PIN_GROUP(msiof1_txd_a),
4498 SH_PFC_PIN_GROUP(msiof1_rxd_a),
4499 SH_PFC_PIN_GROUP(msiof1_clk_b),
4500 SH_PFC_PIN_GROUP(msiof1_sync_b),
4501 SH_PFC_PIN_GROUP(msiof1_ss1_b),
4502 SH_PFC_PIN_GROUP(msiof1_ss2_b),
4503 SH_PFC_PIN_GROUP(msiof1_txd_b),
4504 SH_PFC_PIN_GROUP(msiof1_rxd_b),
4505 SH_PFC_PIN_GROUP(msiof1_clk_c),
4506 SH_PFC_PIN_GROUP(msiof1_sync_c),
4507 SH_PFC_PIN_GROUP(msiof1_ss1_c),
4508 SH_PFC_PIN_GROUP(msiof1_ss2_c),
4509 SH_PFC_PIN_GROUP(msiof1_txd_c),
4510 SH_PFC_PIN_GROUP(msiof1_rxd_c),
4511 SH_PFC_PIN_GROUP(msiof1_clk_d),
4512 SH_PFC_PIN_GROUP(msiof1_sync_d),
4513 SH_PFC_PIN_GROUP(msiof1_ss1_d),
4514 SH_PFC_PIN_GROUP(msiof1_ss2_d),
4515 SH_PFC_PIN_GROUP(msiof1_txd_d),
4516 SH_PFC_PIN_GROUP(msiof1_rxd_d),
4517 SH_PFC_PIN_GROUP(msiof1_clk_e),
4518 SH_PFC_PIN_GROUP(msiof1_sync_e),
4519 SH_PFC_PIN_GROUP(msiof1_ss1_e),
4520 SH_PFC_PIN_GROUP(msiof1_ss2_e),
4521 SH_PFC_PIN_GROUP(msiof1_txd_e),
4522 SH_PFC_PIN_GROUP(msiof1_rxd_e),
4523 SH_PFC_PIN_GROUP(msiof1_clk_f),
4524 SH_PFC_PIN_GROUP(msiof1_sync_f),
4525 SH_PFC_PIN_GROUP(msiof1_ss1_f),
4526 SH_PFC_PIN_GROUP(msiof1_ss2_f),
4527 SH_PFC_PIN_GROUP(msiof1_txd_f),
4528 SH_PFC_PIN_GROUP(msiof1_rxd_f),
4529 SH_PFC_PIN_GROUP(msiof1_clk_g),
4530 SH_PFC_PIN_GROUP(msiof1_sync_g),
4531 SH_PFC_PIN_GROUP(msiof1_ss1_g),
4532 SH_PFC_PIN_GROUP(msiof1_ss2_g),
4533 SH_PFC_PIN_GROUP(msiof1_txd_g),
4534 SH_PFC_PIN_GROUP(msiof1_rxd_g),
4535 SH_PFC_PIN_GROUP(msiof2_clk_a),
4536 SH_PFC_PIN_GROUP(msiof2_sync_a),
4537 SH_PFC_PIN_GROUP(msiof2_ss1_a),
4538 SH_PFC_PIN_GROUP(msiof2_ss2_a),
4539 SH_PFC_PIN_GROUP(msiof2_txd_a),
4540 SH_PFC_PIN_GROUP(msiof2_rxd_a),
4541 SH_PFC_PIN_GROUP(msiof2_clk_b),
4542 SH_PFC_PIN_GROUP(msiof2_sync_b),
4543 SH_PFC_PIN_GROUP(msiof2_ss1_b),
4544 SH_PFC_PIN_GROUP(msiof2_ss2_b),
4545 SH_PFC_PIN_GROUP(msiof2_txd_b),
4546 SH_PFC_PIN_GROUP(msiof2_rxd_b),
4547 SH_PFC_PIN_GROUP(msiof2_clk_c),
4548 SH_PFC_PIN_GROUP(msiof2_sync_c),
4549 SH_PFC_PIN_GROUP(msiof2_ss1_c),
4550 SH_PFC_PIN_GROUP(msiof2_ss2_c),
4551 SH_PFC_PIN_GROUP(msiof2_txd_c),
4552 SH_PFC_PIN_GROUP(msiof2_rxd_c),
4553 SH_PFC_PIN_GROUP(msiof2_clk_d),
4554 SH_PFC_PIN_GROUP(msiof2_sync_d),
4555 SH_PFC_PIN_GROUP(msiof2_ss1_d),
4556 SH_PFC_PIN_GROUP(msiof2_ss2_d),
4557 SH_PFC_PIN_GROUP(msiof2_txd_d),
4558 SH_PFC_PIN_GROUP(msiof2_rxd_d),
4559 SH_PFC_PIN_GROUP(msiof3_clk_a),
4560 SH_PFC_PIN_GROUP(msiof3_sync_a),
4561 SH_PFC_PIN_GROUP(msiof3_ss1_a),
4562 SH_PFC_PIN_GROUP(msiof3_ss2_a),
4563 SH_PFC_PIN_GROUP(msiof3_txd_a),
4564 SH_PFC_PIN_GROUP(msiof3_rxd_a),
4565 SH_PFC_PIN_GROUP(msiof3_clk_b),
4566 SH_PFC_PIN_GROUP(msiof3_sync_b),
4567 SH_PFC_PIN_GROUP(msiof3_ss1_b),
4568 SH_PFC_PIN_GROUP(msiof3_ss2_b),
4569 SH_PFC_PIN_GROUP(msiof3_txd_b),
4570 SH_PFC_PIN_GROUP(msiof3_rxd_b),
4571 SH_PFC_PIN_GROUP(msiof3_clk_c),
4572 SH_PFC_PIN_GROUP(msiof3_sync_c),
4573 SH_PFC_PIN_GROUP(msiof3_txd_c),
4574 SH_PFC_PIN_GROUP(msiof3_rxd_c),
4575 SH_PFC_PIN_GROUP(msiof3_clk_d),
4576 SH_PFC_PIN_GROUP(msiof3_sync_d),
4577 SH_PFC_PIN_GROUP(msiof3_ss1_d),
4578 SH_PFC_PIN_GROUP(msiof3_txd_d),
4579 SH_PFC_PIN_GROUP(msiof3_rxd_d),
4580 SH_PFC_PIN_GROUP(msiof3_clk_e),
4581 SH_PFC_PIN_GROUP(msiof3_sync_e),
4582 SH_PFC_PIN_GROUP(msiof3_ss1_e),
4583 SH_PFC_PIN_GROUP(msiof3_ss2_e),
4584 SH_PFC_PIN_GROUP(msiof3_txd_e),
4585 SH_PFC_PIN_GROUP(msiof3_rxd_e),
4586 SH_PFC_PIN_GROUP(pwm0),
4587 SH_PFC_PIN_GROUP(pwm1_a),
4588 SH_PFC_PIN_GROUP(pwm1_b),
4589 SH_PFC_PIN_GROUP(pwm2_a),
4590 SH_PFC_PIN_GROUP(pwm2_b),
4591 SH_PFC_PIN_GROUP(pwm3_a),
4592 SH_PFC_PIN_GROUP(pwm3_b),
4593 SH_PFC_PIN_GROUP(pwm4_a),
4594 SH_PFC_PIN_GROUP(pwm4_b),
4595 SH_PFC_PIN_GROUP(pwm5_a),
4596 SH_PFC_PIN_GROUP(pwm5_b),
4597 SH_PFC_PIN_GROUP(pwm6_a),
4598 SH_PFC_PIN_GROUP(pwm6_b),
4599 SH_PFC_PIN_GROUP(sata0_devslp_a),
4600 SH_PFC_PIN_GROUP(sata0_devslp_b),
4601 SH_PFC_PIN_GROUP(scif0_data),
4602 SH_PFC_PIN_GROUP(scif0_clk),
4603 SH_PFC_PIN_GROUP(scif0_ctrl),
4604 SH_PFC_PIN_GROUP(scif1_data_a),
4605 SH_PFC_PIN_GROUP(scif1_clk),
4606 SH_PFC_PIN_GROUP(scif1_ctrl),
4607 SH_PFC_PIN_GROUP(scif1_data_b),
4608 SH_PFC_PIN_GROUP(scif2_data_a),
4609 SH_PFC_PIN_GROUP(scif2_clk),
4610 SH_PFC_PIN_GROUP(scif2_data_b),
4611 SH_PFC_PIN_GROUP(scif3_data_a),
4612 SH_PFC_PIN_GROUP(scif3_clk),
4613 SH_PFC_PIN_GROUP(scif3_ctrl),
4614 SH_PFC_PIN_GROUP(scif3_data_b),
4615 SH_PFC_PIN_GROUP(scif4_data_a),
4616 SH_PFC_PIN_GROUP(scif4_clk_a),
4617 SH_PFC_PIN_GROUP(scif4_ctrl_a),
4618 SH_PFC_PIN_GROUP(scif4_data_b),
4619 SH_PFC_PIN_GROUP(scif4_clk_b),
4620 SH_PFC_PIN_GROUP(scif4_ctrl_b),
4621 SH_PFC_PIN_GROUP(scif4_data_c),
4622 SH_PFC_PIN_GROUP(scif4_clk_c),
4623 SH_PFC_PIN_GROUP(scif4_ctrl_c),
4624 SH_PFC_PIN_GROUP(scif5_data_a),
4625 SH_PFC_PIN_GROUP(scif5_clk_a),
4626 SH_PFC_PIN_GROUP(scif5_data_b),
4627 SH_PFC_PIN_GROUP(scif5_clk_b),
4628 SH_PFC_PIN_GROUP(scif_clk_a),
4629 SH_PFC_PIN_GROUP(scif_clk_b),
4630 SH_PFC_PIN_GROUP(sdhi0_data1),
4631 SH_PFC_PIN_GROUP(sdhi0_data4),
4632 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4633 SH_PFC_PIN_GROUP(sdhi0_cd),
4634 SH_PFC_PIN_GROUP(sdhi0_wp),
4635 SH_PFC_PIN_GROUP(sdhi1_data1),
4636 SH_PFC_PIN_GROUP(sdhi1_data4),
4637 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4638 SH_PFC_PIN_GROUP(sdhi1_cd),
4639 SH_PFC_PIN_GROUP(sdhi1_wp),
4640 SH_PFC_PIN_GROUP(sdhi2_data1),
4641 SH_PFC_PIN_GROUP(sdhi2_data4),
4642 SH_PFC_PIN_GROUP(sdhi2_data8),
4643 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4644 SH_PFC_PIN_GROUP(sdhi2_cd_a),
4645 SH_PFC_PIN_GROUP(sdhi2_wp_a),
4646 SH_PFC_PIN_GROUP(sdhi2_cd_b),
4647 SH_PFC_PIN_GROUP(sdhi2_wp_b),
4648 SH_PFC_PIN_GROUP(sdhi2_ds),
4649 SH_PFC_PIN_GROUP(sdhi3_data1),
4650 SH_PFC_PIN_GROUP(sdhi3_data4),
4651 SH_PFC_PIN_GROUP(sdhi3_data8),
4652 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4653 SH_PFC_PIN_GROUP(sdhi3_cd),
4654 SH_PFC_PIN_GROUP(sdhi3_wp),
4655 SH_PFC_PIN_GROUP(sdhi3_ds),
4656 SH_PFC_PIN_GROUP(ssi0_data),
4657 SH_PFC_PIN_GROUP(ssi01239_ctrl),
4658 SH_PFC_PIN_GROUP(ssi1_data_a),
4659 SH_PFC_PIN_GROUP(ssi1_data_b),
4660 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4661 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4662 SH_PFC_PIN_GROUP(ssi2_data_a),
4663 SH_PFC_PIN_GROUP(ssi2_data_b),
4664 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4665 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4666 SH_PFC_PIN_GROUP(ssi3_data),
4667 SH_PFC_PIN_GROUP(ssi349_ctrl),
4668 SH_PFC_PIN_GROUP(ssi4_data),
4669 SH_PFC_PIN_GROUP(ssi4_ctrl),
4670 SH_PFC_PIN_GROUP(ssi5_data),
4671 SH_PFC_PIN_GROUP(ssi5_ctrl),
4672 SH_PFC_PIN_GROUP(ssi6_data),
4673 SH_PFC_PIN_GROUP(ssi6_ctrl),
4674 SH_PFC_PIN_GROUP(ssi7_data),
4675 SH_PFC_PIN_GROUP(ssi78_ctrl),
4676 SH_PFC_PIN_GROUP(ssi8_data),
4677 SH_PFC_PIN_GROUP(ssi9_data_a),
4678 SH_PFC_PIN_GROUP(ssi9_data_b),
4679 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4680 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4681 SH_PFC_PIN_GROUP(tmu_tclk1_a),
4682 SH_PFC_PIN_GROUP(tmu_tclk1_b),
4683 SH_PFC_PIN_GROUP(tmu_tclk2_a),
4684 SH_PFC_PIN_GROUP(tmu_tclk2_b),
4685 SH_PFC_PIN_GROUP(tpu_to0),
4686 SH_PFC_PIN_GROUP(tpu_to1),
4687 SH_PFC_PIN_GROUP(tpu_to2),
4688 SH_PFC_PIN_GROUP(tpu_to3),
4689 SH_PFC_PIN_GROUP(usb0),
4690 SH_PFC_PIN_GROUP(usb1),
4691 SH_PFC_PIN_GROUP(usb30),
4692 VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
4693 VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
4694 VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
4695 VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
4696 SH_PFC_PIN_GROUP(vin4_data18_a),
4697 VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
4698 VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
4699 VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
4700 VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
4701 VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
4702 VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
4703 SH_PFC_PIN_GROUP(vin4_data18_b),
4704 VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
4705 VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
4706 SH_PFC_PIN_GROUP(vin4_sync),
4707 SH_PFC_PIN_GROUP(vin4_field),
4708 SH_PFC_PIN_GROUP(vin4_clkenb),
4709 SH_PFC_PIN_GROUP(vin4_clk),
4710 VIN_DATA_PIN_GROUP(vin5_data, 8),
4711 VIN_DATA_PIN_GROUP(vin5_data, 10),
4712 VIN_DATA_PIN_GROUP(vin5_data, 12),
4713 VIN_DATA_PIN_GROUP(vin5_data, 16),
4714 SH_PFC_PIN_GROUP(vin5_sync),
4715 SH_PFC_PIN_GROUP(vin5_field),
4716 SH_PFC_PIN_GROUP(vin5_clkenb),
4717 SH_PFC_PIN_GROUP(vin5_clk),
4718 },
Biju Das0a362702020-10-28 10:34:24 +0000[diff] [blame^]4719#ifdef CONFIG_PINCTRL_PFC_R8A77965
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]4720 .automotive = {
4721 SH_PFC_PIN_GROUP(drif0_ctrl_a),
4722 SH_PFC_PIN_GROUP(drif0_data0_a),
4723 SH_PFC_PIN_GROUP(drif0_data1_a),
4724 SH_PFC_PIN_GROUP(drif0_ctrl_b),
4725 SH_PFC_PIN_GROUP(drif0_data0_b),
4726 SH_PFC_PIN_GROUP(drif0_data1_b),
4727 SH_PFC_PIN_GROUP(drif0_ctrl_c),
4728 SH_PFC_PIN_GROUP(drif0_data0_c),
4729 SH_PFC_PIN_GROUP(drif0_data1_c),
4730 SH_PFC_PIN_GROUP(drif1_ctrl_a),
4731 SH_PFC_PIN_GROUP(drif1_data0_a),
4732 SH_PFC_PIN_GROUP(drif1_data1_a),
4733 SH_PFC_PIN_GROUP(drif1_ctrl_b),
4734 SH_PFC_PIN_GROUP(drif1_data0_b),
4735 SH_PFC_PIN_GROUP(drif1_data1_b),
4736 SH_PFC_PIN_GROUP(drif1_ctrl_c),
4737 SH_PFC_PIN_GROUP(drif1_data0_c),
4738 SH_PFC_PIN_GROUP(drif1_data1_c),
4739 SH_PFC_PIN_GROUP(drif2_ctrl_a),
4740 SH_PFC_PIN_GROUP(drif2_data0_a),
4741 SH_PFC_PIN_GROUP(drif2_data1_a),
4742 SH_PFC_PIN_GROUP(drif2_ctrl_b),
4743 SH_PFC_PIN_GROUP(drif2_data0_b),
4744 SH_PFC_PIN_GROUP(drif2_data1_b),
4745 SH_PFC_PIN_GROUP(drif3_ctrl_a),
4746 SH_PFC_PIN_GROUP(drif3_data0_a),
4747 SH_PFC_PIN_GROUP(drif3_data1_a),
4748 SH_PFC_PIN_GROUP(drif3_ctrl_b),
4749 SH_PFC_PIN_GROUP(drif3_data0_b),
4750 SH_PFC_PIN_GROUP(drif3_data1_b),
4751 }
Biju Das0a362702020-10-28 10:34:24 +0000[diff] [blame^]4752#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4753};
4754
4755static const char * const audio_clk_groups[] = {
4756 "audio_clk_a_a",
4757 "audio_clk_a_b",
4758 "audio_clk_a_c",
4759 "audio_clk_b_a",
4760 "audio_clk_b_b",
4761 "audio_clk_c_a",
4762 "audio_clk_c_b",
4763 "audio_clkout_a",
4764 "audio_clkout_b",
4765 "audio_clkout_c",
4766 "audio_clkout_d",
4767 "audio_clkout1_a",
4768 "audio_clkout1_b",
4769 "audio_clkout2_a",
4770 "audio_clkout2_b",
4771 "audio_clkout3_a",
4772 "audio_clkout3_b",
4773};
4774
4775static const char * const avb_groups[] = {
4776 "avb_link",
4777 "avb_magic",
4778 "avb_phy_int",
4779 "avb_mdc", /* Deprecated, please use "avb_mdio" instead */
4780 "avb_mdio",
4781 "avb_mii",
4782 "avb_avtp_pps",
4783 "avb_avtp_match_a",
4784 "avb_avtp_capture_a",
4785 "avb_avtp_match_b",
4786 "avb_avtp_capture_b",
4787};
4788
4789static const char * const can0_groups[] = {
4790 "can0_data_a",
4791 "can0_data_b",
4792};
4793
4794static const char * const can1_groups[] = {
4795 "can1_data",
4796};
4797
4798static const char * const can_clk_groups[] = {
4799 "can_clk",
4800};
4801
4802static const char * const canfd0_groups[] = {
4803 "canfd0_data_a",
4804 "canfd0_data_b",
4805};
4806
4807static const char * const canfd1_groups[] = {
4808 "canfd1_data",
4809};
4810
Biju Das0a362702020-10-28 10:34:24 +0000[diff] [blame^]4811#ifdef CONFIG_PINCTRL_PFC_R8A77965
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4812static const char * const drif0_groups[] = {
4813 "drif0_ctrl_a",
4814 "drif0_data0_a",
4815 "drif0_data1_a",
4816 "drif0_ctrl_b",
4817 "drif0_data0_b",
4818 "drif0_data1_b",
4819 "drif0_ctrl_c",
4820 "drif0_data0_c",
4821 "drif0_data1_c",
4822};
4823
4824static const char * const drif1_groups[] = {
4825 "drif1_ctrl_a",
4826 "drif1_data0_a",
4827 "drif1_data1_a",
4828 "drif1_ctrl_b",
4829 "drif1_data0_b",
4830 "drif1_data1_b",
4831 "drif1_ctrl_c",
4832 "drif1_data0_c",
4833 "drif1_data1_c",
4834};
4835
4836static const char * const drif2_groups[] = {
4837 "drif2_ctrl_a",
4838 "drif2_data0_a",
4839 "drif2_data1_a",
4840 "drif2_ctrl_b",
4841 "drif2_data0_b",
4842 "drif2_data1_b",
4843};
4844
4845static const char * const drif3_groups[] = {
4846 "drif3_ctrl_a",
4847 "drif3_data0_a",
4848 "drif3_data1_a",
4849 "drif3_ctrl_b",
4850 "drif3_data0_b",
4851 "drif3_data1_b",
4852};
Biju Das0a362702020-10-28 10:34:24 +0000[diff] [blame^]4853#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]4854
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4855static const char * const du_groups[] = {
4856 "du_rgb666",
4857 "du_rgb888",
4858 "du_clk_out_0",
4859 "du_clk_out_1",
4860 "du_sync",
4861 "du_oddf",
4862 "du_cde",
4863 "du_disp",
4864};
4865
4866static const char * const hscif0_groups[] = {
4867 "hscif0_data",
4868 "hscif0_clk",
4869 "hscif0_ctrl",
4870};
4871
4872static const char * const hscif1_groups[] = {
4873 "hscif1_data_a",
4874 "hscif1_clk_a",
4875 "hscif1_ctrl_a",
4876 "hscif1_data_b",
4877 "hscif1_clk_b",
4878 "hscif1_ctrl_b",
4879};
4880
4881static const char * const hscif2_groups[] = {
4882 "hscif2_data_a",
4883 "hscif2_clk_a",
4884 "hscif2_ctrl_a",
4885 "hscif2_data_b",
4886 "hscif2_clk_b",
4887 "hscif2_ctrl_b",
4888 "hscif2_data_c",
4889 "hscif2_clk_c",
4890 "hscif2_ctrl_c",
4891};
4892
4893static const char * const hscif3_groups[] = {
4894 "hscif3_data_a",
4895 "hscif3_clk",
4896 "hscif3_ctrl",
4897 "hscif3_data_b",
4898 "hscif3_data_c",
4899 "hscif3_data_d",
4900};
4901
4902static const char * const hscif4_groups[] = {
4903 "hscif4_data_a",
4904 "hscif4_clk",
4905 "hscif4_ctrl",
4906 "hscif4_data_b",
4907};
4908
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]4909static const char * const i2c0_groups[] = {
4910 "i2c0",
4911};
4912
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4913static const char * const i2c1_groups[] = {
4914 "i2c1_a",
4915 "i2c1_b",
4916};
4917
4918static const char * const i2c2_groups[] = {
4919 "i2c2_a",
4920 "i2c2_b",
4921};
4922
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]4923static const char * const i2c3_groups[] = {
4924 "i2c3",
4925};
4926
4927static const char * const i2c5_groups[] = {
4928 "i2c5",
4929};
4930
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]4931static const char * const i2c6_groups[] = {
4932 "i2c6_a",
4933 "i2c6_b",
4934 "i2c6_c",
4935};
4936
4937static const char * const intc_ex_groups[] = {
4938 "intc_ex_irq0",
4939 "intc_ex_irq1",
4940 "intc_ex_irq2",
4941 "intc_ex_irq3",
4942 "intc_ex_irq4",
4943 "intc_ex_irq5",
4944};
4945
4946static const char * const msiof0_groups[] = {
4947 "msiof0_clk",
4948 "msiof0_sync",
4949 "msiof0_ss1",
4950 "msiof0_ss2",
4951 "msiof0_txd",
4952 "msiof0_rxd",
4953};
4954
4955static const char * const msiof1_groups[] = {
4956 "msiof1_clk_a",
4957 "msiof1_sync_a",
4958 "msiof1_ss1_a",
4959 "msiof1_ss2_a",
4960 "msiof1_txd_a",
4961 "msiof1_rxd_a",
4962 "msiof1_clk_b",
4963 "msiof1_sync_b",
4964 "msiof1_ss1_b",
4965 "msiof1_ss2_b",
4966 "msiof1_txd_b",
4967 "msiof1_rxd_b",
4968 "msiof1_clk_c",
4969 "msiof1_sync_c",
4970 "msiof1_ss1_c",
4971 "msiof1_ss2_c",
4972 "msiof1_txd_c",
4973 "msiof1_rxd_c",
4974 "msiof1_clk_d",
4975 "msiof1_sync_d",
4976 "msiof1_ss1_d",
4977 "msiof1_ss2_d",
4978 "msiof1_txd_d",
4979 "msiof1_rxd_d",
4980 "msiof1_clk_e",
4981 "msiof1_sync_e",
4982 "msiof1_ss1_e",
4983 "msiof1_ss2_e",
4984 "msiof1_txd_e",
4985 "msiof1_rxd_e",
4986 "msiof1_clk_f",
4987 "msiof1_sync_f",
4988 "msiof1_ss1_f",
4989 "msiof1_ss2_f",
4990 "msiof1_txd_f",
4991 "msiof1_rxd_f",
4992 "msiof1_clk_g",
4993 "msiof1_sync_g",
4994 "msiof1_ss1_g",
4995 "msiof1_ss2_g",
4996 "msiof1_txd_g",
4997 "msiof1_rxd_g",
4998};
4999
5000static const char * const msiof2_groups[] = {
5001 "msiof2_clk_a",
5002 "msiof2_sync_a",
5003 "msiof2_ss1_a",
5004 "msiof2_ss2_a",
5005 "msiof2_txd_a",
5006 "msiof2_rxd_a",
5007 "msiof2_clk_b",
5008 "msiof2_sync_b",
5009 "msiof2_ss1_b",
5010 "msiof2_ss2_b",
5011 "msiof2_txd_b",
5012 "msiof2_rxd_b",
5013 "msiof2_clk_c",
5014 "msiof2_sync_c",
5015 "msiof2_ss1_c",
5016 "msiof2_ss2_c",
5017 "msiof2_txd_c",
5018 "msiof2_rxd_c",
5019 "msiof2_clk_d",
5020 "msiof2_sync_d",
5021 "msiof2_ss1_d",
5022 "msiof2_ss2_d",
5023 "msiof2_txd_d",
5024 "msiof2_rxd_d",
5025};
5026
5027static const char * const msiof3_groups[] = {
5028 "msiof3_clk_a",
5029 "msiof3_sync_a",
5030 "msiof3_ss1_a",
5031 "msiof3_ss2_a",
5032 "msiof3_txd_a",
5033 "msiof3_rxd_a",
5034 "msiof3_clk_b",
5035 "msiof3_sync_b",
5036 "msiof3_ss1_b",
5037 "msiof3_ss2_b",
5038 "msiof3_txd_b",
5039 "msiof3_rxd_b",
5040 "msiof3_clk_c",
5041 "msiof3_sync_c",
5042 "msiof3_txd_c",
5043 "msiof3_rxd_c",
5044 "msiof3_clk_d",
5045 "msiof3_sync_d",
5046 "msiof3_ss1_d",
5047 "msiof3_txd_d",
5048 "msiof3_rxd_d",
5049 "msiof3_clk_e",
5050 "msiof3_sync_e",
5051 "msiof3_ss1_e",
5052 "msiof3_ss2_e",
5053 "msiof3_txd_e",
5054 "msiof3_rxd_e",
5055};
5056
5057static const char * const pwm0_groups[] = {
5058 "pwm0",
5059};
5060
5061static const char * const pwm1_groups[] = {
5062 "pwm1_a",
5063 "pwm1_b",
5064};
5065
5066static const char * const pwm2_groups[] = {
5067 "pwm2_a",
5068 "pwm2_b",
5069};
5070
5071static const char * const pwm3_groups[] = {
5072 "pwm3_a",
5073 "pwm3_b",
5074};
5075
5076static const char * const pwm4_groups[] = {
5077 "pwm4_a",
5078 "pwm4_b",
5079};
5080
5081static const char * const pwm5_groups[] = {
5082 "pwm5_a",
5083 "pwm5_b",
5084};
5085
5086static const char * const pwm6_groups[] = {
5087 "pwm6_a",
5088 "pwm6_b",
5089};
5090
5091static const char * const sata0_groups[] = {
5092 "sata0_devslp_a",
5093 "sata0_devslp_b",
5094};
5095
5096static const char * const scif0_groups[] = {
5097 "scif0_data",
5098 "scif0_clk",
5099 "scif0_ctrl",
5100};
5101
5102static const char * const scif1_groups[] = {
5103 "scif1_data_a",
5104 "scif1_clk",
5105 "scif1_ctrl",
5106 "scif1_data_b",
5107};
5108static const char * const scif2_groups[] = {
5109 "scif2_data_a",
5110 "scif2_clk",
5111 "scif2_data_b",
5112};
5113
5114static const char * const scif3_groups[] = {
5115 "scif3_data_a",
5116 "scif3_clk",
5117 "scif3_ctrl",
5118 "scif3_data_b",
5119};
5120
5121static const char * const scif4_groups[] = {
5122 "scif4_data_a",
5123 "scif4_clk_a",
5124 "scif4_ctrl_a",
5125 "scif4_data_b",
5126 "scif4_clk_b",
5127 "scif4_ctrl_b",
5128 "scif4_data_c",
5129 "scif4_clk_c",
5130 "scif4_ctrl_c",
5131};
5132
5133static const char * const scif5_groups[] = {
5134 "scif5_data_a",
5135 "scif5_clk_a",
5136 "scif5_data_b",
5137 "scif5_clk_b",
5138};
5139
5140static const char * const scif_clk_groups[] = {
5141 "scif_clk_a",
5142 "scif_clk_b",
5143};
5144
5145static const char * const sdhi0_groups[] = {
5146 "sdhi0_data1",
5147 "sdhi0_data4",
5148 "sdhi0_ctrl",
5149 "sdhi0_cd",
5150 "sdhi0_wp",
5151};
5152
5153static const char * const sdhi1_groups[] = {
5154 "sdhi1_data1",
5155 "sdhi1_data4",
5156 "sdhi1_ctrl",
5157 "sdhi1_cd",
5158 "sdhi1_wp",
5159};
5160
5161static const char * const sdhi2_groups[] = {
5162 "sdhi2_data1",
5163 "sdhi2_data4",
5164 "sdhi2_data8",
5165 "sdhi2_ctrl",
5166 "sdhi2_cd_a",
5167 "sdhi2_wp_a",
5168 "sdhi2_cd_b",
5169 "sdhi2_wp_b",
5170 "sdhi2_ds",
5171};
5172
5173static const char * const sdhi3_groups[] = {
5174 "sdhi3_data1",
5175 "sdhi3_data4",
5176 "sdhi3_data8",
5177 "sdhi3_ctrl",
5178 "sdhi3_cd",
5179 "sdhi3_wp",
5180 "sdhi3_ds",
5181};
5182
5183static const char * const ssi_groups[] = {
5184 "ssi0_data",
5185 "ssi01239_ctrl",
5186 "ssi1_data_a",
5187 "ssi1_data_b",
5188 "ssi1_ctrl_a",
5189 "ssi1_ctrl_b",
5190 "ssi2_data_a",
5191 "ssi2_data_b",
5192 "ssi2_ctrl_a",
5193 "ssi2_ctrl_b",
5194 "ssi3_data",
5195 "ssi349_ctrl",
5196 "ssi4_data",
5197 "ssi4_ctrl",
5198 "ssi5_data",
5199 "ssi5_ctrl",
5200 "ssi6_data",
5201 "ssi6_ctrl",
5202 "ssi7_data",
5203 "ssi78_ctrl",
5204 "ssi8_data",
5205 "ssi9_data_a",
5206 "ssi9_data_b",
5207 "ssi9_ctrl_a",
5208 "ssi9_ctrl_b",
5209};
5210
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]5211static const char * const tmu_groups[] = {
5212 "tmu_tclk1_a",
5213 "tmu_tclk1_b",
5214 "tmu_tclk2_a",
5215 "tmu_tclk2_b",
5216};
5217
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]5218static const char * const tpu_groups[] = {
5219 "tpu_to0",
5220 "tpu_to1",
5221 "tpu_to2",
5222 "tpu_to3",
5223};
5224
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5225static const char * const usb0_groups[] = {
5226 "usb0",
5227};
5228
5229static const char * const usb1_groups[] = {
5230 "usb1",
5231};
5232
5233static const char * const usb30_groups[] = {
5234 "usb30",
5235};
5236
5237static const char * const vin4_groups[] = {
5238 "vin4_data8_a",
5239 "vin4_data10_a",
5240 "vin4_data12_a",
5241 "vin4_data16_a",
5242 "vin4_data18_a",
5243 "vin4_data20_a",
5244 "vin4_data24_a",
5245 "vin4_data8_b",
5246 "vin4_data10_b",
5247 "vin4_data12_b",
5248 "vin4_data16_b",
5249 "vin4_data18_b",
5250 "vin4_data20_b",
5251 "vin4_data24_b",
5252 "vin4_sync",
5253 "vin4_field",
5254 "vin4_clkenb",
5255 "vin4_clk",
5256};
5257
5258static const char * const vin5_groups[] = {
5259 "vin5_data8",
5260 "vin5_data10",
5261 "vin5_data12",
5262 "vin5_data16",
5263 "vin5_sync",
5264 "vin5_field",
5265 "vin5_clkenb",
5266 "vin5_clk",
5267};
5268
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]5269static const struct {
5270 struct sh_pfc_function common[51];
Biju Das0a362702020-10-28 10:34:24 +0000[diff] [blame^]5271#ifdef CONFIG_PINCTRL_PFC_R8A77965
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]5272 struct sh_pfc_function automotive[4];
Biju Das0a362702020-10-28 10:34:24 +0000[diff] [blame^]5273#endif
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]5274} pinmux_functions = {
5275 .common = {
5276 SH_PFC_FUNCTION(audio_clk),
5277 SH_PFC_FUNCTION(avb),
5278 SH_PFC_FUNCTION(can0),
5279 SH_PFC_FUNCTION(can1),
5280 SH_PFC_FUNCTION(can_clk),
5281 SH_PFC_FUNCTION(canfd0),
5282 SH_PFC_FUNCTION(canfd1),
5283 SH_PFC_FUNCTION(du),
5284 SH_PFC_FUNCTION(hscif0),
5285 SH_PFC_FUNCTION(hscif1),
5286 SH_PFC_FUNCTION(hscif2),
5287 SH_PFC_FUNCTION(hscif3),
5288 SH_PFC_FUNCTION(hscif4),
5289 SH_PFC_FUNCTION(i2c0),
5290 SH_PFC_FUNCTION(i2c1),
5291 SH_PFC_FUNCTION(i2c2),
5292 SH_PFC_FUNCTION(i2c3),
5293 SH_PFC_FUNCTION(i2c5),
5294 SH_PFC_FUNCTION(i2c6),
5295 SH_PFC_FUNCTION(intc_ex),
5296 SH_PFC_FUNCTION(msiof0),
5297 SH_PFC_FUNCTION(msiof1),
5298 SH_PFC_FUNCTION(msiof2),
5299 SH_PFC_FUNCTION(msiof3),
5300 SH_PFC_FUNCTION(pwm0),
5301 SH_PFC_FUNCTION(pwm1),
5302 SH_PFC_FUNCTION(pwm2),
5303 SH_PFC_FUNCTION(pwm3),
5304 SH_PFC_FUNCTION(pwm4),
5305 SH_PFC_FUNCTION(pwm5),
5306 SH_PFC_FUNCTION(pwm6),
5307 SH_PFC_FUNCTION(sata0),
5308 SH_PFC_FUNCTION(scif0),
5309 SH_PFC_FUNCTION(scif1),
5310 SH_PFC_FUNCTION(scif2),
5311 SH_PFC_FUNCTION(scif3),
5312 SH_PFC_FUNCTION(scif4),
5313 SH_PFC_FUNCTION(scif5),
5314 SH_PFC_FUNCTION(scif_clk),
5315 SH_PFC_FUNCTION(sdhi0),
5316 SH_PFC_FUNCTION(sdhi1),
5317 SH_PFC_FUNCTION(sdhi2),
5318 SH_PFC_FUNCTION(sdhi3),
5319 SH_PFC_FUNCTION(ssi),
5320 SH_PFC_FUNCTION(tmu),
5321 SH_PFC_FUNCTION(tpu),
5322 SH_PFC_FUNCTION(usb0),
5323 SH_PFC_FUNCTION(usb1),
5324 SH_PFC_FUNCTION(usb30),
5325 SH_PFC_FUNCTION(vin4),
5326 SH_PFC_FUNCTION(vin5),
5327 },
Biju Das0a362702020-10-28 10:34:24 +0000[diff] [blame^]5328#ifdef CONFIG_PINCTRL_PFC_R8A77965
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]5329 .automotive = {
5330 SH_PFC_FUNCTION(drif0),
5331 SH_PFC_FUNCTION(drif1),
5332 SH_PFC_FUNCTION(drif2),
5333 SH_PFC_FUNCTION(drif3),
5334 }
Biju Das0a362702020-10-28 10:34:24 +0000[diff] [blame^]5335#endif /* CONFIG_PINCTRL_PFC_R8A77965 */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5336};
5337
5338static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5339#define F_(x, y) FN_##y
5340#define FM(x) FN_##x
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5341 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5342 0, 0,
5343 0, 0,
5344 0, 0,
5345 0, 0,
5346 0, 0,
5347 0, 0,
5348 0, 0,
5349 0, 0,
5350 0, 0,
5351 0, 0,
5352 0, 0,
5353 0, 0,
5354 0, 0,
5355 0, 0,
5356 0, 0,
5357 0, 0,
5358 GP_0_15_FN, GPSR0_15,
5359 GP_0_14_FN, GPSR0_14,
5360 GP_0_13_FN, GPSR0_13,
5361 GP_0_12_FN, GPSR0_12,
5362 GP_0_11_FN, GPSR0_11,
5363 GP_0_10_FN, GPSR0_10,
5364 GP_0_9_FN, GPSR0_9,
5365 GP_0_8_FN, GPSR0_8,
5366 GP_0_7_FN, GPSR0_7,
5367 GP_0_6_FN, GPSR0_6,
5368 GP_0_5_FN, GPSR0_5,
5369 GP_0_4_FN, GPSR0_4,
5370 GP_0_3_FN, GPSR0_3,
5371 GP_0_2_FN, GPSR0_2,
5372 GP_0_1_FN, GPSR0_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5373 GP_0_0_FN, GPSR0_0, ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5374 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5375 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5376 0, 0,
5377 0, 0,
5378 0, 0,
5379 GP_1_28_FN, GPSR1_28,
5380 GP_1_27_FN, GPSR1_27,
5381 GP_1_26_FN, GPSR1_26,
5382 GP_1_25_FN, GPSR1_25,
5383 GP_1_24_FN, GPSR1_24,
5384 GP_1_23_FN, GPSR1_23,
5385 GP_1_22_FN, GPSR1_22,
5386 GP_1_21_FN, GPSR1_21,
5387 GP_1_20_FN, GPSR1_20,
5388 GP_1_19_FN, GPSR1_19,
5389 GP_1_18_FN, GPSR1_18,
5390 GP_1_17_FN, GPSR1_17,
5391 GP_1_16_FN, GPSR1_16,
5392 GP_1_15_FN, GPSR1_15,
5393 GP_1_14_FN, GPSR1_14,
5394 GP_1_13_FN, GPSR1_13,
5395 GP_1_12_FN, GPSR1_12,
5396 GP_1_11_FN, GPSR1_11,
5397 GP_1_10_FN, GPSR1_10,
5398 GP_1_9_FN, GPSR1_9,
5399 GP_1_8_FN, GPSR1_8,
5400 GP_1_7_FN, GPSR1_7,
5401 GP_1_6_FN, GPSR1_6,
5402 GP_1_5_FN, GPSR1_5,
5403 GP_1_4_FN, GPSR1_4,
5404 GP_1_3_FN, GPSR1_3,
5405 GP_1_2_FN, GPSR1_2,
5406 GP_1_1_FN, GPSR1_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5407 GP_1_0_FN, GPSR1_0, ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5408 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5409 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5410 0, 0,
5411 0, 0,
5412 0, 0,
5413 0, 0,
5414 0, 0,
5415 0, 0,
5416 0, 0,
5417 0, 0,
5418 0, 0,
5419 0, 0,
5420 0, 0,
5421 0, 0,
5422 0, 0,
5423 0, 0,
5424 0, 0,
5425 0, 0,
5426 0, 0,
5427 GP_2_14_FN, GPSR2_14,
5428 GP_2_13_FN, GPSR2_13,
5429 GP_2_12_FN, GPSR2_12,
5430 GP_2_11_FN, GPSR2_11,
5431 GP_2_10_FN, GPSR2_10,
5432 GP_2_9_FN, GPSR2_9,
5433 GP_2_8_FN, GPSR2_8,
5434 GP_2_7_FN, GPSR2_7,
5435 GP_2_6_FN, GPSR2_6,
5436 GP_2_5_FN, GPSR2_5,
5437 GP_2_4_FN, GPSR2_4,
5438 GP_2_3_FN, GPSR2_3,
5439 GP_2_2_FN, GPSR2_2,
5440 GP_2_1_FN, GPSR2_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5441 GP_2_0_FN, GPSR2_0, ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5442 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5443 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5444 0, 0,
5445 0, 0,
5446 0, 0,
5447 0, 0,
5448 0, 0,
5449 0, 0,
5450 0, 0,
5451 0, 0,
5452 0, 0,
5453 0, 0,
5454 0, 0,
5455 0, 0,
5456 0, 0,
5457 0, 0,
5458 0, 0,
5459 0, 0,
5460 GP_3_15_FN, GPSR3_15,
5461 GP_3_14_FN, GPSR3_14,
5462 GP_3_13_FN, GPSR3_13,
5463 GP_3_12_FN, GPSR3_12,
5464 GP_3_11_FN, GPSR3_11,
5465 GP_3_10_FN, GPSR3_10,
5466 GP_3_9_FN, GPSR3_9,
5467 GP_3_8_FN, GPSR3_8,
5468 GP_3_7_FN, GPSR3_7,
5469 GP_3_6_FN, GPSR3_6,
5470 GP_3_5_FN, GPSR3_5,
5471 GP_3_4_FN, GPSR3_4,
5472 GP_3_3_FN, GPSR3_3,
5473 GP_3_2_FN, GPSR3_2,
5474 GP_3_1_FN, GPSR3_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5475 GP_3_0_FN, GPSR3_0, ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5476 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5477 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5478 0, 0,
5479 0, 0,
5480 0, 0,
5481 0, 0,
5482 0, 0,
5483 0, 0,
5484 0, 0,
5485 0, 0,
5486 0, 0,
5487 0, 0,
5488 0, 0,
5489 0, 0,
5490 0, 0,
5491 0, 0,
5492 GP_4_17_FN, GPSR4_17,
5493 GP_4_16_FN, GPSR4_16,
5494 GP_4_15_FN, GPSR4_15,
5495 GP_4_14_FN, GPSR4_14,
5496 GP_4_13_FN, GPSR4_13,
5497 GP_4_12_FN, GPSR4_12,
5498 GP_4_11_FN, GPSR4_11,
5499 GP_4_10_FN, GPSR4_10,
5500 GP_4_9_FN, GPSR4_9,
5501 GP_4_8_FN, GPSR4_8,
5502 GP_4_7_FN, GPSR4_7,
5503 GP_4_6_FN, GPSR4_6,
5504 GP_4_5_FN, GPSR4_5,
5505 GP_4_4_FN, GPSR4_4,
5506 GP_4_3_FN, GPSR4_3,
5507 GP_4_2_FN, GPSR4_2,
5508 GP_4_1_FN, GPSR4_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5509 GP_4_0_FN, GPSR4_0, ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5510 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5511 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5512 0, 0,
5513 0, 0,
5514 0, 0,
5515 0, 0,
5516 0, 0,
5517 0, 0,
5518 GP_5_25_FN, GPSR5_25,
5519 GP_5_24_FN, GPSR5_24,
5520 GP_5_23_FN, GPSR5_23,
5521 GP_5_22_FN, GPSR5_22,
5522 GP_5_21_FN, GPSR5_21,
5523 GP_5_20_FN, GPSR5_20,
5524 GP_5_19_FN, GPSR5_19,
5525 GP_5_18_FN, GPSR5_18,
5526 GP_5_17_FN, GPSR5_17,
5527 GP_5_16_FN, GPSR5_16,
5528 GP_5_15_FN, GPSR5_15,
5529 GP_5_14_FN, GPSR5_14,
5530 GP_5_13_FN, GPSR5_13,
5531 GP_5_12_FN, GPSR5_12,
5532 GP_5_11_FN, GPSR5_11,
5533 GP_5_10_FN, GPSR5_10,
5534 GP_5_9_FN, GPSR5_9,
5535 GP_5_8_FN, GPSR5_8,
5536 GP_5_7_FN, GPSR5_7,
5537 GP_5_6_FN, GPSR5_6,
5538 GP_5_5_FN, GPSR5_5,
5539 GP_5_4_FN, GPSR5_4,
5540 GP_5_3_FN, GPSR5_3,
5541 GP_5_2_FN, GPSR5_2,
5542 GP_5_1_FN, GPSR5_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5543 GP_5_0_FN, GPSR5_0, ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5544 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5545 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5546 GP_6_31_FN, GPSR6_31,
5547 GP_6_30_FN, GPSR6_30,
5548 GP_6_29_FN, GPSR6_29,
5549 GP_6_28_FN, GPSR6_28,
5550 GP_6_27_FN, GPSR6_27,
5551 GP_6_26_FN, GPSR6_26,
5552 GP_6_25_FN, GPSR6_25,
5553 GP_6_24_FN, GPSR6_24,
5554 GP_6_23_FN, GPSR6_23,
5555 GP_6_22_FN, GPSR6_22,
5556 GP_6_21_FN, GPSR6_21,
5557 GP_6_20_FN, GPSR6_20,
5558 GP_6_19_FN, GPSR6_19,
5559 GP_6_18_FN, GPSR6_18,
5560 GP_6_17_FN, GPSR6_17,
5561 GP_6_16_FN, GPSR6_16,
5562 GP_6_15_FN, GPSR6_15,
5563 GP_6_14_FN, GPSR6_14,
5564 GP_6_13_FN, GPSR6_13,
5565 GP_6_12_FN, GPSR6_12,
5566 GP_6_11_FN, GPSR6_11,
5567 GP_6_10_FN, GPSR6_10,
5568 GP_6_9_FN, GPSR6_9,
5569 GP_6_8_FN, GPSR6_8,
5570 GP_6_7_FN, GPSR6_7,
5571 GP_6_6_FN, GPSR6_6,
5572 GP_6_5_FN, GPSR6_5,
5573 GP_6_4_FN, GPSR6_4,
5574 GP_6_3_FN, GPSR6_3,
5575 GP_6_2_FN, GPSR6_2,
5576 GP_6_1_FN, GPSR6_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5577 GP_6_0_FN, GPSR6_0, ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5578 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5579 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5580 0, 0,
5581 0, 0,
5582 0, 0,
5583 0, 0,
5584 0, 0,
5585 0, 0,
5586 0, 0,
5587 0, 0,
5588 0, 0,
5589 0, 0,
5590 0, 0,
5591 0, 0,
5592 0, 0,
5593 0, 0,
5594 0, 0,
5595 0, 0,
5596 0, 0,
5597 0, 0,
5598 0, 0,
5599 0, 0,
5600 0, 0,
5601 0, 0,
5602 0, 0,
5603 0, 0,
5604 0, 0,
5605 0, 0,
5606 0, 0,
5607 0, 0,
5608 GP_7_3_FN, GPSR7_3,
5609 GP_7_2_FN, GPSR7_2,
5610 GP_7_1_FN, GPSR7_1,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5611 GP_7_0_FN, GPSR7_0, ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5612 },
5613#undef F_
5614#undef FM
5615
5616#define F_(x, y) x,
5617#define FM(x) FN_##x,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5618 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5619 IP0_31_28
5620 IP0_27_24
5621 IP0_23_20
5622 IP0_19_16
5623 IP0_15_12
5624 IP0_11_8
5625 IP0_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5626 IP0_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5627 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5628 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5629 IP1_31_28
5630 IP1_27_24
5631 IP1_23_20
5632 IP1_19_16
5633 IP1_15_12
5634 IP1_11_8
5635 IP1_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5636 IP1_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5637 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5638 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5639 IP2_31_28
5640 IP2_27_24
5641 IP2_23_20
5642 IP2_19_16
5643 IP2_15_12
5644 IP2_11_8
5645 IP2_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5646 IP2_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5647 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5648 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5649 IP3_31_28
5650 IP3_27_24
5651 IP3_23_20
5652 IP3_19_16
5653 IP3_15_12
5654 IP3_11_8
5655 IP3_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5656 IP3_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5657 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5658 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5659 IP4_31_28
5660 IP4_27_24
5661 IP4_23_20
5662 IP4_19_16
5663 IP4_15_12
5664 IP4_11_8
5665 IP4_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5666 IP4_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5667 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5668 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5669 IP5_31_28
5670 IP5_27_24
5671 IP5_23_20
5672 IP5_19_16
5673 IP5_15_12
5674 IP5_11_8
5675 IP5_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5676 IP5_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5677 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5678 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5679 IP6_31_28
5680 IP6_27_24
5681 IP6_23_20
5682 IP6_19_16
5683 IP6_15_12
5684 IP6_11_8
5685 IP6_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5686 IP6_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5687 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5688 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5689 IP7_31_28
5690 IP7_27_24
5691 IP7_23_20
5692 IP7_19_16
5693 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5694 IP7_11_8
5695 IP7_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5696 IP7_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5697 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5698 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5699 IP8_31_28
5700 IP8_27_24
5701 IP8_23_20
5702 IP8_19_16
5703 IP8_15_12
5704 IP8_11_8
5705 IP8_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5706 IP8_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5707 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5708 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5709 IP9_31_28
5710 IP9_27_24
5711 IP9_23_20
5712 IP9_19_16
5713 IP9_15_12
5714 IP9_11_8
5715 IP9_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5716 IP9_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5717 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5718 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5719 IP10_31_28
5720 IP10_27_24
5721 IP10_23_20
5722 IP10_19_16
5723 IP10_15_12
5724 IP10_11_8
5725 IP10_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5726 IP10_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5727 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5728 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5729 IP11_31_28
5730 IP11_27_24
5731 IP11_23_20
5732 IP11_19_16
5733 IP11_15_12
5734 IP11_11_8
5735 IP11_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5736 IP11_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5737 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5738 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5739 IP12_31_28
5740 IP12_27_24
5741 IP12_23_20
5742 IP12_19_16
5743 IP12_15_12
5744 IP12_11_8
5745 IP12_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5746 IP12_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5747 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5748 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5749 IP13_31_28
5750 IP13_27_24
5751 IP13_23_20
5752 IP13_19_16
5753 IP13_15_12
5754 IP13_11_8
5755 IP13_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5756 IP13_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5757 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5758 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5759 IP14_31_28
5760 IP14_27_24
5761 IP14_23_20
5762 IP14_19_16
5763 IP14_15_12
5764 IP14_11_8
5765 IP14_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5766 IP14_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5767 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5768 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5769 IP15_31_28
5770 IP15_27_24
5771 IP15_23_20
5772 IP15_19_16
5773 IP15_15_12
5774 IP15_11_8
5775 IP15_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5776 IP15_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5777 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5778 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5779 IP16_31_28
5780 IP16_27_24
5781 IP16_23_20
5782 IP16_19_16
5783 IP16_15_12
5784 IP16_11_8
5785 IP16_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5786 IP16_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5787 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5788 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5789 IP17_31_28
5790 IP17_27_24
5791 IP17_23_20
5792 IP17_19_16
5793 IP17_15_12
5794 IP17_11_8
5795 IP17_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5796 IP17_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5797 },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5798 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4, GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5799 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5800 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5801 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5802 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5803 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5804 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5805 IP18_7_4
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5806 IP18_3_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5807 },
5808#undef F_
5809#undef FM
5810
5811#define F_(x, y) x,
5812#define FM(x) FN_##x,
5813 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5814 GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, 1, 2,
5815 1, 1, 1, 2, 2, 1, 2, 3),
5816 GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5817 MOD_SEL0_31_30_29
5818 MOD_SEL0_28_27
5819 MOD_SEL0_26_25_24
5820 MOD_SEL0_23
5821 MOD_SEL0_22
5822 MOD_SEL0_21
5823 MOD_SEL0_20
5824 MOD_SEL0_19
5825 MOD_SEL0_18_17
5826 MOD_SEL0_16
5827 0, 0, /* RESERVED 15 */
5828 MOD_SEL0_14_13
5829 MOD_SEL0_12
5830 MOD_SEL0_11
5831 MOD_SEL0_10
5832 MOD_SEL0_9_8
5833 MOD_SEL0_7_6
5834 MOD_SEL0_5
5835 MOD_SEL0_4_3
5836 /* RESERVED 2, 1, 0 */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5837 0, 0, 0, 0, 0, 0, 0, 0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5838 },
5839 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5840 GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
5841 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
5842 GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5843 MOD_SEL1_31_30
5844 MOD_SEL1_29_28_27
5845 MOD_SEL1_26
5846 MOD_SEL1_25_24
5847 MOD_SEL1_23_22_21
5848 MOD_SEL1_20
5849 MOD_SEL1_19
5850 MOD_SEL1_18_17
5851 MOD_SEL1_16
5852 MOD_SEL1_15_14
5853 MOD_SEL1_13
5854 MOD_SEL1_12
5855 MOD_SEL1_11
5856 MOD_SEL1_10
5857 MOD_SEL1_9
5858 0, 0, 0, 0, /* RESERVED 8, 7 */
5859 MOD_SEL1_6
5860 MOD_SEL1_5
5861 MOD_SEL1_4
5862 MOD_SEL1_3
5863 MOD_SEL1_2
5864 MOD_SEL1_1
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5865 MOD_SEL1_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5866 },
5867 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5868 GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
5869 1, 4, 4, 4, 3, 1),
5870 GROUP(
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5871 MOD_SEL2_31
5872 MOD_SEL2_30
5873 MOD_SEL2_29
5874 MOD_SEL2_28_27
5875 MOD_SEL2_26
5876 MOD_SEL2_25_24_23
5877 MOD_SEL2_22
5878 MOD_SEL2_21
5879 MOD_SEL2_20
5880 MOD_SEL2_19
5881 MOD_SEL2_18
5882 MOD_SEL2_17
5883 /* RESERVED 16 */
5884 0, 0,
5885 /* RESERVED 15, 14, 13, 12 */
5886 0, 0, 0, 0, 0, 0, 0, 0,
5887 0, 0, 0, 0, 0, 0, 0, 0,
5888 /* RESERVED 11, 10, 9, 8 */
5889 0, 0, 0, 0, 0, 0, 0, 0,
5890 0, 0, 0, 0, 0, 0, 0, 0,
5891 /* RESERVED 7, 6, 5, 4 */
5892 0, 0, 0, 0, 0, 0, 0, 0,
5893 0, 0, 0, 0, 0, 0, 0, 0,
5894 /* RESERVED 3, 2, 1 */
5895 0, 0, 0, 0, 0, 0, 0, 0,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]5896 MOD_SEL2_0 ))
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]5897 },
5898 { },
5899};
5900
5901static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5902 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5903 { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
5904 { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
5905 { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
5906 { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
5907 { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
5908 { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
5909 { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
5910 { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
5911 } },
5912 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5913 { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
5914 { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
5915 { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
5916 { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
5917 { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
5918 { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
5919 { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
5920 { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
5921 } },
5922 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5923 { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
5924 { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
5925 { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
5926 { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
5927 { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
5928 { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
5929 { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
5930 { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
5931 } },
5932 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5933 { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
5934 { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
5935 { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
5936 { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
5937 { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
5938 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
5939 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
5940 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
5941 } },
5942 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5943 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
5944 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
5945 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
5946 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
5947 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
5948 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
5949 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
5950 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
5951 } },
5952 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5953 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
5954 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
5955 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
5956 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
5957 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
5958 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
5959 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
5960 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
5961 } },
5962 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5963 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
5964 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
5965 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
5966 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
5967 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
5968 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
5969 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
5970 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
5971 } },
5972 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5973 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
5974 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
5975 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
5976 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
5977 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
5978 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
5979 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
5980 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
5981 } },
5982 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5983 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
5984 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
5985 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
5986 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
5987 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
5988 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
5989 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
5990 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
5991 } },
5992 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5993 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
5994 { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
5995 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
5996 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
5997 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
5998 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
5999 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
6000 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
6001 } },
6002 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
6003 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
6004 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
6005 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
6006 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
6007 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
6008 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
6009 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
6010 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
6011 } },
6012 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
6013 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
6014 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
6015 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
6016 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]6017 { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6018 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
6019 { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
6020 { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
6021 } },
6022 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
6023 { PIN_A_NUMBER('R', 8), 28, 2 }, /* DU_DOTCLKIN3 */
6024 { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST */
6025 { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
6026 } },
6027 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
6028 { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
6029 { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
6030 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
6031 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
6032 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
6033 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
6034 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
6035 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
6036 } },
6037 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
6038 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
6039 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
6040 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
6041 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
6042 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
6043 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
6044 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
6045 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
6046 } },
6047 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
6048 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
6049 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
6050 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
6051 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
6052 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
6053 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
6054 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
6055 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
6056 } },
6057 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
6058 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
6059 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
6060 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
6061 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
6062 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
6063 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
6064 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
6065 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
6066 } },
6067 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
6068 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
6069 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
6070 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
6071 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
6072 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
6073 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
6074 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
6075 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
6076 } },
6077 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
6078 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
6079 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
6080 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
6081 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
6082 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
6083 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
6084 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
6085 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
6086 } },
6087 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
6088 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
6089 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
6090 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
6091 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
6092 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
6093 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
6094 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
6095 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
6096 } },
6097 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
6098 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
6099 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
6100 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
6101 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
6102 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
6103 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
6104 { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
6105 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
6106 } },
6107 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
6108 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
6109 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
6110 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
6111 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
6112 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
6113 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
6114 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
6115 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
6116 } },
6117 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
6118 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
6119 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
6120 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
6121 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
6122 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
6123 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
6124 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
6125 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
6126 } },
6127 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
6128 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
6129 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
6130 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
6131 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
6132 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
6133 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
6134 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
6135 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
6136 } },
6137 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
6138 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
6139 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
6140 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
6141 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
6142 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
6143 { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30 */
6144 { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31 */
6145 } },
6146 { },
6147};
6148
6149enum ioctrl_regs {
6150 POCCTRL,
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]6151 TDSELCTRL,
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6152};
6153
6154static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
6155 [POCCTRL] = { 0xe6060380, },
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]6156 [TDSELCTRL] = { 0xe60603c0, },
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6157 { /* sentinel */ },
6158};
6159
6160static int r8a77965_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
6161{
6162 int bit = -EINVAL;
6163
6164 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
6165
6166 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
6167 bit = pin & 0x1f;
6168
6169 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
6170 bit = (pin & 0x1f) + 12;
6171
6172 return bit;
6173}
6174
6175static const struct pinmux_bias_reg pinmux_bias_regs[] = {
6176 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
6177 [ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */
6178 [ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */
6179 [ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */
6180 [ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */
6181 [ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */
6182 [ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */
6183 [ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */
6184 [ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */
6185 [ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */
6186 [ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */
6187 [10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */
6188 [11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */
6189 [12] = PIN_NUMBER('Y', 7), /* RPC_INT# */
6190 [13] = PIN_NUMBER('V', 6), /* RPC_WP# */
6191 [14] = PIN_NUMBER('V', 7), /* RPC_RESET# */
6192 [15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */
6193 [16] = PIN_NUMBER('B', 19), /* AVB_RXC */
6194 [17] = PIN_NUMBER('A', 13), /* AVB_RD0 */
6195 [18] = PIN_NUMBER('B', 13), /* AVB_RD1 */
6196 [19] = PIN_NUMBER('A', 14), /* AVB_RD2 */
6197 [20] = PIN_NUMBER('B', 14), /* AVB_RD3 */
6198 [21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */
6199 [22] = PIN_NUMBER('A', 19), /* AVB_TXC */
6200 [23] = PIN_NUMBER('A', 18), /* AVB_TD0 */
6201 [24] = PIN_NUMBER('B', 18), /* AVB_TD1 */
6202 [25] = PIN_NUMBER('A', 17), /* AVB_TD2 */
6203 [26] = PIN_NUMBER('B', 17), /* AVB_TD3 */
6204 [27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */
6205 [28] = PIN_NUMBER('A', 9), /* AVB_MDIO */
6206 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
6207 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
6208 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
6209 } },
6210 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
6211 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
6212 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
6213 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
6214 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
6215 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
6216 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
6217 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
6218 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
6219 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
6220 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
6221 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
6222 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
6223 [12] = RCAR_GP_PIN(1, 0), /* A0 */
6224 [13] = RCAR_GP_PIN(1, 1), /* A1 */
6225 [14] = RCAR_GP_PIN(1, 2), /* A2 */
6226 [15] = RCAR_GP_PIN(1, 3), /* A3 */
6227 [16] = RCAR_GP_PIN(1, 4), /* A4 */
6228 [17] = RCAR_GP_PIN(1, 5), /* A5 */
6229 [18] = RCAR_GP_PIN(1, 6), /* A6 */
6230 [19] = RCAR_GP_PIN(1, 7), /* A7 */
6231 [20] = RCAR_GP_PIN(1, 8), /* A8 */
6232 [21] = RCAR_GP_PIN(1, 9), /* A9 */
6233 [22] = RCAR_GP_PIN(1, 10), /* A10 */
6234 [23] = RCAR_GP_PIN(1, 11), /* A11 */
6235 [24] = RCAR_GP_PIN(1, 12), /* A12 */
6236 [25] = RCAR_GP_PIN(1, 13), /* A13 */
6237 [26] = RCAR_GP_PIN(1, 14), /* A14 */
6238 [27] = RCAR_GP_PIN(1, 15), /* A15 */
6239 [28] = RCAR_GP_PIN(1, 16), /* A16 */
6240 [29] = RCAR_GP_PIN(1, 17), /* A17 */
6241 [30] = RCAR_GP_PIN(1, 18), /* A18 */
6242 [31] = RCAR_GP_PIN(1, 19), /* A19 */
6243 } },
6244 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
6245 [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */
6246 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
6247 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */
6248 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
6249 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
6250 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
6251 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
6252 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
6253 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
6254 [ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */
6255 [10] = RCAR_GP_PIN(0, 0), /* D0 */
6256 [11] = RCAR_GP_PIN(0, 1), /* D1 */
6257 [12] = RCAR_GP_PIN(0, 2), /* D2 */
6258 [13] = RCAR_GP_PIN(0, 3), /* D3 */
6259 [14] = RCAR_GP_PIN(0, 4), /* D4 */
6260 [15] = RCAR_GP_PIN(0, 5), /* D5 */
6261 [16] = RCAR_GP_PIN(0, 6), /* D6 */
6262 [17] = RCAR_GP_PIN(0, 7), /* D7 */
6263 [18] = RCAR_GP_PIN(0, 8), /* D8 */
6264 [19] = RCAR_GP_PIN(0, 9), /* D9 */
6265 [20] = RCAR_GP_PIN(0, 10), /* D10 */
6266 [21] = RCAR_GP_PIN(0, 11), /* D11 */
6267 [22] = RCAR_GP_PIN(0, 12), /* D12 */
6268 [23] = RCAR_GP_PIN(0, 13), /* D13 */
6269 [24] = RCAR_GP_PIN(0, 14), /* D14 */
6270 [25] = RCAR_GP_PIN(0, 15), /* D15 */
6271 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
6272 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
Eugeniu Roscaf0066b02019-07-09 18:27:11 +0200[diff] [blame]6273 [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6274 [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
6275 [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
6276 [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
6277 } },
6278 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
Marek Vasut88e81ec2019-03-04 22:39:51 +0100[diff] [blame]6279 [ 0] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN3 */
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6280 [ 1] = PIN_NONE,
6281 [ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST */
6282 [ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/
6283 [ 4] = PIN_A_NUMBER('R', 26), /* TRST# */
6284 [ 5] = PIN_A_NUMBER('T', 27), /* TCK */
6285 [ 6] = PIN_A_NUMBER('R', 30), /* TMS */
6286 [ 7] = PIN_A_NUMBER('R', 29), /* TDI */
6287 [ 8] = PIN_NONE,
6288 [ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */
6289 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
6290 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
6291 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
6292 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
6293 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
6294 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
6295 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
6296 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
6297 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
6298 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
6299 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
6300 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
6301 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
6302 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
6303 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
6304 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
6305 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
6306 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
6307 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
6308 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
6309 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
6310 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
6311 } },
6312 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
6313 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
6314 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
6315 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
6316 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
6317 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
6318 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
6319 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
6320 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
6321 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
6322 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
6323 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
6324 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
6325 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
6326 [13] = RCAR_GP_PIN(5, 1), /* RX0 */
6327 [14] = RCAR_GP_PIN(5, 2), /* TX0 */
6328 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
6329 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
6330 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
6331 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
6332 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
6333 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
6334 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
6335 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
6336 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
6337 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
6338 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */
6339 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */
6340 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
6341 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
6342 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
6343 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
6344 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
6345 } },
6346 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
6347 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
6348 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
6349 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
6350 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
6351 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
6352 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
6353 [ 6] = PIN_NUMBER('H', 37), /* MLB_REF */
6354 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
6355 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
6356 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
6357 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
6358 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
6359 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
6360 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
6361 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
6362 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
6363 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
6364 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
6365 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
6366 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
6367 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
6368 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
6369 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
6370 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
6371 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
6372 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
6373 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
6374 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
6375 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
6376 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
6377 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
6378 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
6379 } },
6380 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
6381 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
6382 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
6383 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
6384 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
6385 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
6386 [ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */
6387 [ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */
6388 [ 7] = PIN_NONE,
6389 [ 8] = PIN_NONE,
6390 [ 9] = PIN_NONE,
6391 [10] = PIN_NONE,
6392 [11] = PIN_NONE,
6393 [12] = PIN_NONE,
6394 [13] = PIN_NONE,
6395 [14] = PIN_NONE,
6396 [15] = PIN_NONE,
6397 [16] = PIN_NONE,
6398 [17] = PIN_NONE,
6399 [18] = PIN_NONE,
6400 [19] = PIN_NONE,
6401 [20] = PIN_NONE,
6402 [21] = PIN_NONE,
6403 [22] = PIN_NONE,
6404 [23] = PIN_NONE,
6405 [24] = PIN_NONE,
6406 [25] = PIN_NONE,
6407 [26] = PIN_NONE,
6408 [27] = PIN_NONE,
6409 [28] = PIN_NONE,
6410 [29] = PIN_NONE,
6411 [30] = PIN_NONE,
6412 [31] = PIN_NONE,
6413 } },
6414 { /* sentinel */ },
6415};
6416
6417static unsigned int r8a77965_pinmux_get_bias(struct sh_pfc *pfc,
6418 unsigned int pin)
6419{
6420 const struct pinmux_bias_reg *reg;
6421 unsigned int bit;
6422
6423 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
6424 if (!reg)
6425 return PIN_CONFIG_BIAS_DISABLE;
6426
6427 if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
6428 return PIN_CONFIG_BIAS_DISABLE;
6429 else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
6430 return PIN_CONFIG_BIAS_PULL_UP;
6431 else
6432 return PIN_CONFIG_BIAS_PULL_DOWN;
6433}
6434
6435static void r8a77965_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
6436 unsigned int bias)
6437{
6438 const struct pinmux_bias_reg *reg;
6439 u32 enable, updown;
6440 unsigned int bit;
6441
6442 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
6443 if (!reg)
6444 return;
6445
6446 enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
6447 if (bias != PIN_CONFIG_BIAS_DISABLE)
6448 enable |= BIT(bit);
6449
6450 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
6451 if (bias == PIN_CONFIG_BIAS_PULL_UP)
6452 updown |= BIT(bit);
6453
6454 sh_pfc_write(pfc, reg->pud, updown);
6455 sh_pfc_write(pfc, reg->puen, enable);
6456}
6457
6458static const struct sh_pfc_soc_operations r8a77965_pinmux_ops = {
6459 .pin_to_pocctrl = r8a77965_pin_to_pocctrl,
6460 .get_bias = r8a77965_pinmux_get_bias,
6461 .set_bias = r8a77965_pinmux_set_bias,
6462};
6463
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]6464#ifdef CONFIG_PINCTRL_PFC_R8A774B1
6465const struct sh_pfc_soc_info r8a774b1_pinmux_info = {
6466 .name = "r8a774b1_pfc",
6467 .ops = &r8a77965_pinmux_ops,
6468 .unlock_reg = 0xe6060000, /* PMMR */
6469
6470 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6471
6472 .pins = pinmux_pins,
6473 .nr_pins = ARRAY_SIZE(pinmux_pins),
6474 .groups = pinmux_groups.common,
6475 .nr_groups = ARRAY_SIZE(pinmux_groups.common),
6476 .functions = pinmux_functions.common,
6477 .nr_functions = ARRAY_SIZE(pinmux_functions.common),
6478
6479 .cfg_regs = pinmux_config_regs,
6480 .drive_regs = pinmux_drive_regs,
6481 .bias_regs = pinmux_bias_regs,
6482 .ioctrl_regs = pinmux_ioctrl_regs,
6483
6484 .pinmux_data = pinmux_data,
6485 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6486};
6487#endif
6488
6489#ifdef CONFIG_PINCTRL_PFC_R8A77965
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6490const struct sh_pfc_soc_info r8a77965_pinmux_info = {
6491 .name = "r8a77965_pfc",
6492 .ops = &r8a77965_pinmux_ops,
6493 .unlock_reg = 0xe6060000, /* PMMR */
6494
6495 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6496
6497 .pins = pinmux_pins,
6498 .nr_pins = ARRAY_SIZE(pinmux_pins),
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]6499 .groups = pinmux_groups.common,
6500 .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6501 ARRAY_SIZE(pinmux_groups.automotive),
6502 .functions = pinmux_functions.common,
6503 .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6504 ARRAY_SIZE(pinmux_functions.automotive),
Marek Vasut72269e02019-03-04 01:32:44 +0100[diff] [blame]6505
6506 .cfg_regs = pinmux_config_regs,
6507 .drive_regs = pinmux_drive_regs,
6508 .bias_regs = pinmux_bias_regs,
6509 .ioctrl_regs = pinmux_ioctrl_regs,
6510
6511 .pinmux_data = pinmux_data,
6512 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6513};
Biju Dasd1d78882020-10-28 10:34:21 +0000[diff] [blame]6514#endif