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wdenk0157ced2002-10-21 17:04:47 +00001/*
Wolfgang Denkf710efd2010-07-24 20:22:02 +02002 * (C) Copyright 2002-2010
wdenk0157ced2002-10-21 17:04:47 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __ASM_GBL_DATA_H
25#define __ASM_GBL_DATA_H
Eran Liberty9095d4a2005-07-28 10:08:46 -050026
Peter Tyserbe34d1d2009-09-21 11:20:37 -050027#include "config.h"
Eran Liberty9095d4a2005-07-28 10:08:46 -050028#include "asm/types.h"
29
Simon Glass3ac47d72012-12-13 20:48:30 +000030/* Architecture-specific global data */
31struct arch_global_data {
Simon Glass34a194f2012-12-13 20:48:44 +000032#if defined(CONFIG_8xx)
33 unsigned long brg_clk;
34#endif
35#if defined(CONFIG_CPM2)
Simon Glass44ea8512012-12-13 20:48:46 +000036 /* There are many clocks on the MPC8260 - see page 9-5 */
37 unsigned long vco_out;
38 unsigned long cpm_clk;
39 unsigned long scc_clk;
Simon Glass34a194f2012-12-13 20:48:44 +000040 unsigned long brg_clk;
41#endif
Simon Glasscc76e9e2012-12-13 20:48:47 +000042 /* TODO: sjg@chromium.org: Should these be unslgned long? */
Peter Tyser62e73982009-05-22 17:23:24 -050043#if defined(CONFIG_MPC83xx)
Eran Liberty9095d4a2005-07-28 10:08:46 -050044 /* There are other clocks in the MPC83XX */
45 u32 csb_clk;
Simon Glasscc76e9e2012-12-13 20:48:47 +000046# if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
Ilya Yanoka3e5fd52010-06-28 16:44:33 +040047 defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
Eran Liberty9095d4a2005-07-28 10:08:46 -050048 u32 tsec1_clk;
49 u32 tsec2_clk;
Eran Liberty9095d4a2005-07-28 10:08:46 -050050 u32 usbdr_clk;
Simon Glasscc76e9e2012-12-13 20:48:47 +000051# elif defined(CONFIG_MPC8309)
Gerlando Falautofe201cb2012-10-10 22:13:08 +000052 u32 usbdr_clk;
Simon Glasscc76e9e2012-12-13 20:48:47 +000053# endif
54# if defined(CONFIG_MPC834x)
Scott Woodbeb638a2007-04-16 14:34:18 -050055 u32 usbmph_clk;
Simon Glasscc76e9e2012-12-13 20:48:47 +000056# endif /* CONFIG_MPC834x */
57# if defined(CONFIG_MPC8315)
Dave Liue0cfec82007-09-18 12:36:58 +080058 u32 tdm_clk;
Simon Glasscc76e9e2012-12-13 20:48:47 +000059# endif
Dave Liua46daea2006-11-03 19:33:44 -060060 u32 core_clk;
Eran Liberty9095d4a2005-07-28 10:08:46 -050061 u32 enc_clk;
62 u32 lbiu_clk;
63 u32 lclk_clk;
Simon Glasscc76e9e2012-12-13 20:48:47 +000064# if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
Ilya Yanoka3e5fd52010-06-28 16:44:33 +040065 defined(CONFIG_MPC837x)
Dave Liu5245ff52007-09-18 12:36:11 +080066 u32 pciexp1_clk;
67 u32 pciexp2_clk;
Simon Glasscc76e9e2012-12-13 20:48:47 +000068# endif
69# if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
Dave Liu5245ff52007-09-18 12:36:11 +080070 u32 sata_clk;
Simon Glasscc76e9e2012-12-13 20:48:47 +000071# endif
72# if defined(CONFIG_MPC8360)
73 u32 mem_sec_clk;
74# endif /* CONFIG_MPC8360 */
Dave Liu5245ff52007-09-18 12:36:11 +080075#endif
Simon Glassa8b57392012-12-13 20:48:48 +000076#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
77 u32 lbc_clk;
78 void *cpu;
79#endif /* CONFIG_MPC85xx || CONFIG_MPC86xx */
Simon Glassc2baaec2012-12-13 20:48:49 +000080#if defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \
81 defined(CONFIG_MPC86xx)
82 u32 i2c1_clk;
83 u32 i2c2_clk;
84#endif
Simon Glass8518b172012-12-13 20:48:50 +000085#if defined(CONFIG_QE)
86 u32 qe_clk;
87 u32 brg_clk;
88 uint mp_alloc_base;
89 uint mp_alloc_top;
90#endif /* CONFIG_QE */
Simon Glassc6622d62012-12-13 20:48:51 +000091#if defined(CONFIG_FSL_LAW)
92 u32 used_laws;
93#endif
Simon Glass0b466582012-12-13 20:48:52 +000094#if defined(CONFIG_E500)
95 u32 used_tlb_cams[(CONFIG_SYS_NUM_TLBCAMS+31)/32];
96#endif
Simon Glass4f8c5f02012-12-13 20:48:53 +000097#if defined(CONFIG_MPC5xxx)
98 unsigned long ipb_clk;
99#endif
Simon Glass6c6cbd12012-12-13 20:48:54 +0000100#if defined(CONFIG_MPC512X)
101 u32 ips_clk;
102 u32 csb_clk;
103#endif /* CONFIG_MPC512X */
Simon Glasse02a6e3f2012-12-13 20:48:55 +0000104#if defined(CONFIG_MPC8220)
105 unsigned long inp_clk;
106 unsigned long vco_clk;
107 unsigned long pev_clk;
108 unsigned long flb_clk;
109#endif
Simon Glasscc76e9e2012-12-13 20:48:47 +0000110};
111
112/*
113 * The following data structure is placed in some memory wich is
114 * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
115 * some locked parts of the data cache) to allow for a minimum set of
116 * global variables during system initialization (until we have set
117 * up the memory controller so that we can use RAM).
118 */
119
120typedef struct global_data {
121 bd_t *bd;
122 unsigned long flags;
123 unsigned int baudrate;
124 unsigned long cpu_clk; /* CPU clock in Hz! */
125 unsigned long bus_clk;
126 /* We cannot bracket this with CONFIG_PCI due to mpc5xxx */
127 unsigned long pci_clk;
128 unsigned long mem_clk;
Poonam Aggrwal987862c2009-08-05 13:29:24 +0530129#if defined(CONFIG_FSL_ESDHC)
Kumar Galacd777282008-08-12 11:14:19 -0500130 u32 sdhc_clk;
131#endif
Becky Brucea36601e2008-06-09 20:37:16 -0500132 phys_size_t ram_size; /* RAM size */
wdenk0157ced2002-10-21 17:04:47 +0000133 unsigned long reset_status; /* reset status register at boot */
Peter Tyser62e73982009-05-22 17:23:24 -0500134#if defined(CONFIG_MPC83xx)
Nick Spence56fd3c22008-08-28 14:09:19 -0700135 unsigned long arbiter_event_attributes;
136 unsigned long arbiter_event_address;
137#endif
wdenk0157ced2002-10-21 17:04:47 +0000138 unsigned long env_addr; /* Address of Environment struct */
139 unsigned long env_valid; /* Checksum of Environment valid? */
140 unsigned long have_console; /* serial_init() was called */
Graeme Russ3c28f482011-09-01 00:48:27 +0000141#ifdef CONFIG_PRE_CONSOLE_BUFFER
142 unsigned long precon_buf_idx; /* Pre-Console buffer index */
143#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200144#if defined(CONFIG_SYS_ALLOC_DPRAM) || defined(CONFIG_CPM2)
wdenk0157ced2002-10-21 17:04:47 +0000145 unsigned int dp_alloc_base;
146 unsigned int dp_alloc_top;
147#endif
Stefan Roese19b77f42007-10-23 11:31:05 +0200148#if defined(CONFIG_4xx)
149 u32 uart_clk;
150#endif /* CONFIG_4xx */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200151#if defined(CONFIG_SYS_GT_6426x)
wdenk0157ced2002-10-21 17:04:47 +0000152 unsigned int mirror_hack[16];
153#endif
wdenke0c812a2005-04-03 15:51:42 +0000154#if defined(CONFIG_A3000) || \
155 defined(CONFIG_HIDDEN_DRAGON) || \
156 defined(CONFIG_MUSENKI) || \
157 defined(CONFIG_SANDPOINT)
wdenk0157ced2002-10-21 17:04:47 +0000158 void * console_addr;
159#endif
wdenk452cfd62002-11-19 11:04:11 +0000160 unsigned long relocaddr; /* Start address of U-Boot in RAM */
wdenk0157ced2002-10-21 17:04:47 +0000161#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO)
162 unsigned long fb_base; /* Base address of framebuffer memory */
163#endif
wdenk3aaa67a2003-07-15 21:50:34 +0000164#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
wdenk9dfa8d12002-12-08 09:53:23 +0000165 unsigned long post_log_word; /* Record POST activities */
Valentin Longchampb9181732011-08-03 02:37:01 +0000166 unsigned long post_log_res; /* success of POST test */
wdenkc08f1582003-04-27 22:52:51 +0000167 unsigned long post_init_f_time; /* When post_init_f started */
wdenk9dfa8d12002-12-08 09:53:23 +0000168#endif
wdenk0157ced2002-10-21 17:04:47 +0000169#ifdef CONFIG_BOARD_TYPES
170 unsigned long board_type;
171#endif
wdenkc08f1582003-04-27 22:52:51 +0000172#ifdef CONFIG_MODEM_SUPPORT
173 unsigned long do_mdm_init;
174 unsigned long be_quiet;
175#endif
Stefan Roesef55a22c2007-08-21 16:27:57 +0200176#if defined(CONFIG_LWMON) || defined(CONFIG_LWMON5)
wdenkc08f1582003-04-27 22:52:51 +0000177 unsigned long kbd_status;
wdenk57b2d802003-06-27 21:31:46 +0000178#endif
Dirk Eibach81b37932011-01-21 09:31:21 +0100179#ifdef CONFIG_SYS_FPGA_COUNT
180 unsigned fpga_state[CONFIG_SYS_FPGA_COUNT];
181#endif
Yuri Tikhonov89a4b702008-04-06 19:19:14 +0200182#if defined(CONFIG_WD_MAX_RATE)
183 unsigned long long wdt_last; /* trace watch-dog triggering rate */
184#endif
wdenk874ac262003-07-24 23:38:38 +0000185 void **jt; /* jump table */
Wolfgang Denkf710efd2010-07-24 20:22:02 +0200186 char env_buf[32]; /* buffer for getenv() before reloc. */
Simon Glass3ac47d72012-12-13 20:48:30 +0000187 struct arch_global_data arch; /* architecture-specific data */
wdenk0157ced2002-10-21 17:04:47 +0000188} gd_t;
189
Mike Frysinger211c2102012-03-18 14:31:24 +0000190#include <asm-generic/global_data_flags.h>
wdenk0157ced2002-10-21 17:04:47 +0000191
192#if 1
Wolfgang Denk69c09642008-02-14 22:43:22 +0100193#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r2")
wdenk0157ced2002-10-21 17:04:47 +0000194#else /* We could use plain global data, but the resulting code is bigger */
195#define XTRN_DECLARE_GLOBAL_DATA_PTR extern
196#define DECLARE_GLOBAL_DATA_PTR XTRN_DECLARE_GLOBAL_DATA_PTR \
197 gd_t *gd
198#endif
199
200#endif /* __ASM_GBL_DATA_H */