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wdenk0157ced2002-10-21 17:04:47 +00001/*
Wolfgang Denkf710efd2010-07-24 20:22:02 +02002 * (C) Copyright 2002-2010
wdenk0157ced2002-10-21 17:04:47 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __ASM_GBL_DATA_H
25#define __ASM_GBL_DATA_H
Eran Liberty9095d4a2005-07-28 10:08:46 -050026
Peter Tyserbe34d1d2009-09-21 11:20:37 -050027#include "config.h"
Eran Liberty9095d4a2005-07-28 10:08:46 -050028#include "asm/types.h"
29
wdenk0157ced2002-10-21 17:04:47 +000030/*
31 * The following data structure is placed in some memory wich is
32 * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
33 * some locked parts of the data cache) to allow for a minimum set of
34 * global variables during system initialization (until we have set
35 * up the memory controller so that we can use RAM).
36 *
Wolfgang Denk0191e472010-10-26 14:34:52 +020037 * Keep it *SMALL* and remember to set GENERATED_GBL_DATA_SIZE > sizeof(gd_t)
wdenk0157ced2002-10-21 17:04:47 +000038 */
39
40typedef struct global_data {
41 bd_t *bd;
42 unsigned long flags;
43 unsigned long baudrate;
Bryan O'Donoghue86c8d742008-02-17 22:57:47 +000044 unsigned long cpu_clk; /* CPU clock in Hz! */
wdenk0157ced2002-10-21 17:04:47 +000045 unsigned long bus_clk;
Bryan O'Donoghue86c8d742008-02-17 22:57:47 +000046#if defined(CONFIG_8xx)
47 unsigned long brg_clk;
48#endif
Jon Loeligerf5ad3782005-07-23 10:37:35 -050049#if defined(CONFIG_CPM2)
wdenk0157ced2002-10-21 17:04:47 +000050 /* There are many clocks on the MPC8260 - see page 9-5 */
51 unsigned long vco_out;
52 unsigned long cpm_clk;
53 unsigned long scc_clk;
54 unsigned long brg_clk;
Stefan Roese37628252008-08-06 14:05:38 +020055#ifdef CONFIG_PCI
56 unsigned long pci_clk;
57#endif
wdenk0157ced2002-10-21 17:04:47 +000058#endif
roy zangd136d662006-11-02 18:49:51 +080059 unsigned long mem_clk;
Peter Tyser62e73982009-05-22 17:23:24 -050060#if defined(CONFIG_MPC83xx)
Eran Liberty9095d4a2005-07-28 10:08:46 -050061 /* There are other clocks in the MPC83XX */
62 u32 csb_clk;
Ilya Yanoka3e5fd52010-06-28 16:44:33 +040063#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
64 defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
Eran Liberty9095d4a2005-07-28 10:08:46 -050065 u32 tsec1_clk;
66 u32 tsec2_clk;
Eran Liberty9095d4a2005-07-28 10:08:46 -050067 u32 usbdr_clk;
Scott Woodbeb638a2007-04-16 14:34:18 -050068#endif
Peter Tyser72f2d392009-05-22 17:23:25 -050069#if defined (CONFIG_MPC834x)
Scott Woodbeb638a2007-04-16 14:34:18 -050070 u32 usbmph_clk;
Peter Tyser72f2d392009-05-22 17:23:25 -050071#endif /* CONFIG_MPC834x */
Dave Liu0ce4fef2008-01-10 23:04:13 +080072#if defined(CONFIG_MPC8315)
Dave Liue0cfec82007-09-18 12:36:58 +080073 u32 tdm_clk;
74#endif
Dave Liua46daea2006-11-03 19:33:44 -060075 u32 core_clk;
Eran Liberty9095d4a2005-07-28 10:08:46 -050076 u32 enc_clk;
77 u32 lbiu_clk;
78 u32 lclk_clk;
Rafal Jaworowski384da5e2005-10-17 02:39:53 +020079 u32 pci_clk;
Ilya Yanoka3e5fd52010-06-28 16:44:33 +040080#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
81 defined(CONFIG_MPC837x)
Dave Liu5245ff52007-09-18 12:36:11 +080082 u32 pciexp1_clk;
83 u32 pciexp2_clk;
Dave Liue0cfec82007-09-18 12:36:58 +080084#endif
Peter Tyser72f2d392009-05-22 17:23:25 -050085#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
Dave Liu5245ff52007-09-18 12:36:11 +080086 u32 sata_clk;
87#endif
Andy Flemingee0e9172007-08-14 00:14:25 -050088#if defined(CONFIG_MPC8360)
Kim Phillipsc02cf1e2008-03-28 10:18:40 -050089 u32 mem_sec_clk;
Andy Flemingee0e9172007-08-14 00:14:25 -050090#endif /* CONFIG_MPC8360 */
91#endif
Poonam Aggrwal987862c2009-08-05 13:29:24 +053092#if defined(CONFIG_FSL_ESDHC)
Kumar Galacd777282008-08-12 11:14:19 -050093 u32 sdhc_clk;
94#endif
Trent Piepho0b691fc2008-12-03 15:16:37 -080095#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
96 u32 lbc_clk;
Poonam Aggrwal4baef822009-07-31 12:08:14 +053097 void *cpu;
Trent Piepho0b691fc2008-12-03 15:16:37 -080098#endif /* CONFIG_MPC85xx || CONFIG_MPC86xx */
Peter Tyser62e73982009-05-22 17:23:24 -050099#if defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
Timur Tabic1499f482008-01-09 14:35:26 -0600100 u32 i2c1_clk;
101 u32 i2c2_clk;
102#endif
Dave Liua46daea2006-11-03 19:33:44 -0600103#if defined(CONFIG_QE)
104 u32 qe_clk;
105 u32 brg_clk;
Dave Liue732e9c2006-11-03 12:11:15 -0600106 uint mp_alloc_base;
107 uint mp_alloc_top;
Dave Liua46daea2006-11-03 19:33:44 -0600108#endif /* CONFIG_QE */
Kumar Gala75639e02008-06-11 00:44:10 -0500109#if defined(CONFIG_FSL_LAW)
110 u32 used_laws;
111#endif
Kumar Gala42f99182009-11-12 10:26:16 -0600112#if defined(CONFIG_E500)
113 u32 used_tlb_cams[(CONFIG_SYS_NUM_TLBCAMS+31)/32];
114#endif
wdenkbe9c1cb2004-02-24 02:00:03 +0000115#if defined(CONFIG_MPC5xxx)
wdenk21136db2003-07-16 21:53:01 +0000116 unsigned long ipb_clk;
117 unsigned long pci_clk;
118#endif
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +0200119#if defined(CONFIG_MPC512X)
Grzegorz Bernacki21305af2008-01-11 12:03:43 +0100120 u32 ips_clk;
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +0200121 u32 csb_clk;
John Rigbyd1228c92008-02-26 09:38:14 -0700122 u32 pci_clk;
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +0200123#endif /* CONFIG_MPC512X */
wdenk337f5652004-10-28 00:09:35 +0000124#if defined(CONFIG_MPC8220)
125 unsigned long bExtUart;
126 unsigned long inp_clk;
127 unsigned long pci_clk;
128 unsigned long vco_clk;
129 unsigned long pev_clk;
130 unsigned long flb_clk;
131#endif
Becky Brucea36601e2008-06-09 20:37:16 -0500132 phys_size_t ram_size; /* RAM size */
wdenk0157ced2002-10-21 17:04:47 +0000133 unsigned long reset_status; /* reset status register at boot */
Peter Tyser62e73982009-05-22 17:23:24 -0500134#if defined(CONFIG_MPC83xx)
Nick Spence56fd3c22008-08-28 14:09:19 -0700135 unsigned long arbiter_event_attributes;
136 unsigned long arbiter_event_address;
137#endif
wdenk0157ced2002-10-21 17:04:47 +0000138 unsigned long env_addr; /* Address of Environment struct */
139 unsigned long env_valid; /* Checksum of Environment valid? */
140 unsigned long have_console; /* serial_init() was called */
Graeme Russ3c28f482011-09-01 00:48:27 +0000141#ifdef CONFIG_PRE_CONSOLE_BUFFER
142 unsigned long precon_buf_idx; /* Pre-Console buffer index */
143#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200144#if defined(CONFIG_SYS_ALLOC_DPRAM) || defined(CONFIG_CPM2)
wdenk0157ced2002-10-21 17:04:47 +0000145 unsigned int dp_alloc_base;
146 unsigned int dp_alloc_top;
147#endif
Stefan Roese19b77f42007-10-23 11:31:05 +0200148#if defined(CONFIG_4xx)
149 u32 uart_clk;
150#endif /* CONFIG_4xx */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200151#if defined(CONFIG_SYS_GT_6426x)
wdenk0157ced2002-10-21 17:04:47 +0000152 unsigned int mirror_hack[16];
153#endif
wdenke0c812a2005-04-03 15:51:42 +0000154#if defined(CONFIG_A3000) || \
155 defined(CONFIG_HIDDEN_DRAGON) || \
156 defined(CONFIG_MUSENKI) || \
157 defined(CONFIG_SANDPOINT)
wdenk0157ced2002-10-21 17:04:47 +0000158 void * console_addr;
159#endif
wdenk452cfd62002-11-19 11:04:11 +0000160 unsigned long relocaddr; /* Start address of U-Boot in RAM */
wdenk0157ced2002-10-21 17:04:47 +0000161#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO)
162 unsigned long fb_base; /* Base address of framebuffer memory */
163#endif
wdenk3aaa67a2003-07-15 21:50:34 +0000164#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
wdenk9dfa8d12002-12-08 09:53:23 +0000165 unsigned long post_log_word; /* Record POST activities */
wdenkc08f1582003-04-27 22:52:51 +0000166 unsigned long post_init_f_time; /* When post_init_f started */
wdenk9dfa8d12002-12-08 09:53:23 +0000167#endif
wdenk0157ced2002-10-21 17:04:47 +0000168#ifdef CONFIG_BOARD_TYPES
169 unsigned long board_type;
170#endif
wdenkc08f1582003-04-27 22:52:51 +0000171#ifdef CONFIG_MODEM_SUPPORT
172 unsigned long do_mdm_init;
173 unsigned long be_quiet;
174#endif
Stefan Roesef55a22c2007-08-21 16:27:57 +0200175#if defined(CONFIG_LWMON) || defined(CONFIG_LWMON5)
wdenkc08f1582003-04-27 22:52:51 +0000176 unsigned long kbd_status;
wdenk57b2d802003-06-27 21:31:46 +0000177#endif
Dirk Eibach81b37932011-01-21 09:31:21 +0100178#ifdef CONFIG_SYS_FPGA_COUNT
179 unsigned fpga_state[CONFIG_SYS_FPGA_COUNT];
180#endif
Yuri Tikhonov89a4b702008-04-06 19:19:14 +0200181#if defined(CONFIG_WD_MAX_RATE)
182 unsigned long long wdt_last; /* trace watch-dog triggering rate */
183#endif
wdenk874ac262003-07-24 23:38:38 +0000184 void **jt; /* jump table */
Wolfgang Denkf710efd2010-07-24 20:22:02 +0200185 char env_buf[32]; /* buffer for getenv() before reloc. */
wdenk0157ced2002-10-21 17:04:47 +0000186} gd_t;
187
188/*
189 * Global Data Flags
190 */
Wolfgang Denk460a9ff2010-06-20 23:33:59 +0200191#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */
192#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
193#define GD_FLG_SILENT 0x00004 /* Silent mode */
194#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
195#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */
196#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */
Wolfgang Denkf710efd2010-07-24 20:22:02 +0200197#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */
Wolfgang Denk460a9ff2010-06-20 23:33:59 +0200198#define GD_FLG_ENV_READY 0x00080 /* Environment imported into hash table */
wdenk0157ced2002-10-21 17:04:47 +0000199
200#if 1
Wolfgang Denk69c09642008-02-14 22:43:22 +0100201#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r2")
wdenk0157ced2002-10-21 17:04:47 +0000202#else /* We could use plain global data, but the resulting code is bigger */
203#define XTRN_DECLARE_GLOBAL_DATA_PTR extern
204#define DECLARE_GLOBAL_DATA_PTR XTRN_DECLARE_GLOBAL_DATA_PTR \
205 gd_t *gd
206#endif
207
208#endif /* __ASM_GBL_DATA_H */