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Haavard Skinnemoen51c8f242006-01-20 10:03:34 +01001/*
2 * Copyright (C) 2005-2006 Atmel Corporation
3 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +01005 */
6#include <common.h>
Wenyou Yang3d8d3482016-11-02 10:06:56 +08007#include <clk.h>
Simon Glass75c5d182016-05-05 07:28:11 -06008#include <dm.h>
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +01009
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +010010/*
11 * The u-boot networking stack is a little weird. It seems like the
12 * networking core allocates receive buffers up front without any
13 * regard to the hardware that's supposed to actually receive those
14 * packets.
15 *
16 * The MACB receives packets into 128-byte receive buffers, so the
17 * buffers allocated by the core isn't very practical to use. We'll
18 * allocate our own, but we need one such buffer in case a packet
19 * wraps around the DMA ring so that we have to copy it.
20 *
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020021 * Therefore, define CONFIG_SYS_RX_ETH_BUFFER to 1 in the board-specific
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +010022 * configuration header. This way, the core allocates one RX buffer
23 * and one TX buffer, each of which can hold a ethernet packet of
24 * maximum size.
25 *
26 * For some reason, the networking core unconditionally specifies a
27 * 32-byte packet "alignment" (which really should be called
28 * "padding"). MACB shouldn't need that, but we'll refrain from any
29 * core modifications here...
30 */
31
32#include <net.h>
Simon Glass75c5d182016-05-05 07:28:11 -060033#ifndef CONFIG_DM_ETH
Ben Warren2f2b6b62008-08-31 22:22:04 -070034#include <netdev.h>
Simon Glass75c5d182016-05-05 07:28:11 -060035#endif
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +010036#include <malloc.h>
Semih Hazar790088e2009-12-17 15:07:15 +020037#include <miiphy.h>
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +010038
39#include <linux/mii.h>
40#include <asm/io.h>
41#include <asm/dma-mapping.h>
42#include <asm/arch/clk.h>
Masahiro Yamada64e4f7f2016-09-21 11:28:57 +090043#include <linux/errno.h>
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +010044
45#include "macb.h"
46
Wenyou Yang7b811852016-05-17 13:11:35 +080047DECLARE_GLOBAL_DATA_PTR;
48
Andreas Bießmann1e868122014-05-26 22:55:18 +020049#define MACB_RX_BUFFER_SIZE 4096
50#define MACB_RX_RING_SIZE (MACB_RX_BUFFER_SIZE / 128)
51#define MACB_TX_RING_SIZE 16
52#define MACB_TX_TIMEOUT 1000
53#define MACB_AUTONEG_TIMEOUT 5000000
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +010054
Wilson Lee41d6d1e2017-08-22 20:25:07 -070055#ifdef CONFIG_MACB_ZYNQ
56/* INCR4 AHB bursts */
57#define MACB_ZYNQ_GEM_DMACR_BLENGTH 0x00000004
58/* Use full configured addressable space (8 Kb) */
59#define MACB_ZYNQ_GEM_DMACR_RXSIZE 0x00000300
60/* Use full configured addressable space (4 Kb) */
61#define MACB_ZYNQ_GEM_DMACR_TXSIZE 0x00000400
62/* Set RXBUF with use of 128 byte */
63#define MACB_ZYNQ_GEM_DMACR_RXBUF 0x00020000
64#define MACB_ZYNQ_GEM_DMACR_INIT \
65 (MACB_ZYNQ_GEM_DMACR_BLENGTH | \
66 MACB_ZYNQ_GEM_DMACR_RXSIZE | \
67 MACB_ZYNQ_GEM_DMACR_TXSIZE | \
68 MACB_ZYNQ_GEM_DMACR_RXBUF)
69#endif
70
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +010071struct macb_dma_desc {
72 u32 addr;
73 u32 ctrl;
74};
75
Wu, Josh18052402014-05-27 16:31:05 +080076#define DMA_DESC_BYTES(n) (n * sizeof(struct macb_dma_desc))
77#define MACB_TX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_TX_RING_SIZE))
78#define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE))
Wu, Josh012d68d2015-06-03 16:45:44 +080079#define MACB_TX_DUMMY_DMA_DESC_SIZE (DMA_DESC_BYTES(1))
Wu, Josh18052402014-05-27 16:31:05 +080080
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +010081#define RXADDR_USED 0x00000001
82#define RXADDR_WRAP 0x00000002
83
84#define RXBUF_FRMLEN_MASK 0x00000fff
85#define RXBUF_FRAME_START 0x00004000
86#define RXBUF_FRAME_END 0x00008000
87#define RXBUF_TYPEID_MATCH 0x00400000
88#define RXBUF_ADDR4_MATCH 0x00800000
89#define RXBUF_ADDR3_MATCH 0x01000000
90#define RXBUF_ADDR2_MATCH 0x02000000
91#define RXBUF_ADDR1_MATCH 0x04000000
92#define RXBUF_BROADCAST 0x80000000
93
94#define TXBUF_FRMLEN_MASK 0x000007ff
95#define TXBUF_FRAME_END 0x00008000
96#define TXBUF_NOCRC 0x00010000
97#define TXBUF_EXHAUSTED 0x08000000
98#define TXBUF_UNDERRUN 0x10000000
99#define TXBUF_MAXRETRY 0x20000000
100#define TXBUF_WRAP 0x40000000
101#define TXBUF_USED 0x80000000
102
103struct macb_device {
104 void *regs;
105
106 unsigned int rx_tail;
107 unsigned int tx_head;
108 unsigned int tx_tail;
Simon Glass5ad27512016-05-05 07:28:09 -0600109 unsigned int next_rx_tail;
110 bool wrapped;
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100111
112 void *rx_buffer;
113 void *tx_buffer;
114 struct macb_dma_desc *rx_ring;
115 struct macb_dma_desc *tx_ring;
116
117 unsigned long rx_buffer_dma;
118 unsigned long rx_ring_dma;
119 unsigned long tx_ring_dma;
120
Wu, Josh012d68d2015-06-03 16:45:44 +0800121 struct macb_dma_desc *dummy_desc;
122 unsigned long dummy_desc_dma;
123
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100124 const struct device *dev;
Simon Glass75c5d182016-05-05 07:28:11 -0600125#ifndef CONFIG_DM_ETH
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100126 struct eth_device netdev;
Simon Glass75c5d182016-05-05 07:28:11 -0600127#endif
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100128 unsigned short phy_addr;
Bo Shen7d91deb2013-04-24 15:59:27 +0800129 struct mii_dev *bus;
Wenyou Yang44835ea2017-04-14 14:36:04 +0800130#ifdef CONFIG_PHYLIB
131 struct phy_device *phydev;
132#endif
Wenyou Yang7b811852016-05-17 13:11:35 +0800133
134#ifdef CONFIG_DM_ETH
Wenyou Yang19449362017-02-14 16:24:40 +0800135#ifdef CONFIG_CLK
Wenyou Yang3d8d3482016-11-02 10:06:56 +0800136 unsigned long pclk_rate;
Wenyou Yang19449362017-02-14 16:24:40 +0800137#endif
Wenyou Yang7b811852016-05-17 13:11:35 +0800138 phy_interface_t phy_interface;
139#endif
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100140};
Simon Glass75c5d182016-05-05 07:28:11 -0600141#ifndef CONFIG_DM_ETH
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100142#define to_macb(_nd) container_of(_nd, struct macb_device, netdev)
Simon Glass75c5d182016-05-05 07:28:11 -0600143#endif
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100144
Bo Shen6f7d7d92013-04-24 15:59:28 +0800145static int macb_is_gem(struct macb_device *macb)
146{
147 return MACB_BFEXT(IDNUM, macb_readl(macb, MID)) == 0x2;
148}
149
Gregory CLEMENTf1a1e582015-12-16 14:50:34 +0100150#ifndef cpu_is_sama5d2
151#define cpu_is_sama5d2() 0
152#endif
153
154#ifndef cpu_is_sama5d4
155#define cpu_is_sama5d4() 0
156#endif
157
158static int gem_is_gigabit_capable(struct macb_device *macb)
159{
160 /*
Robert P. J. Day8c60f922016-05-04 04:47:31 -0400161 * The GEM controllers embedded in SAMA5D2 and SAMA5D4 are
Gregory CLEMENTf1a1e582015-12-16 14:50:34 +0100162 * configured to support only 10/100.
163 */
164 return macb_is_gem(macb) && !cpu_is_sama5d2() && !cpu_is_sama5d4();
165}
166
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100167static void macb_mdio_write(struct macb_device *macb, u8 reg, u16 value)
168{
169 unsigned long netctl;
170 unsigned long netstat;
171 unsigned long frame;
172
173 netctl = macb_readl(macb, NCR);
174 netctl |= MACB_BIT(MPE);
175 macb_writel(macb, NCR, netctl);
176
177 frame = (MACB_BF(SOF, 1)
178 | MACB_BF(RW, 1)
179 | MACB_BF(PHYA, macb->phy_addr)
180 | MACB_BF(REGA, reg)
181 | MACB_BF(CODE, 2)
182 | MACB_BF(DATA, value));
183 macb_writel(macb, MAN, frame);
184
185 do {
186 netstat = macb_readl(macb, NSR);
187 } while (!(netstat & MACB_BIT(IDLE)));
188
189 netctl = macb_readl(macb, NCR);
190 netctl &= ~MACB_BIT(MPE);
191 macb_writel(macb, NCR, netctl);
192}
193
194static u16 macb_mdio_read(struct macb_device *macb, u8 reg)
195{
196 unsigned long netctl;
197 unsigned long netstat;
198 unsigned long frame;
199
200 netctl = macb_readl(macb, NCR);
201 netctl |= MACB_BIT(MPE);
202 macb_writel(macb, NCR, netctl);
203
204 frame = (MACB_BF(SOF, 1)
205 | MACB_BF(RW, 2)
206 | MACB_BF(PHYA, macb->phy_addr)
207 | MACB_BF(REGA, reg)
208 | MACB_BF(CODE, 2));
209 macb_writel(macb, MAN, frame);
210
211 do {
212 netstat = macb_readl(macb, NSR);
213 } while (!(netstat & MACB_BIT(IDLE)));
214
215 frame = macb_readl(macb, MAN);
216
217 netctl = macb_readl(macb, NCR);
218 netctl &= ~MACB_BIT(MPE);
219 macb_writel(macb, NCR, netctl);
220
221 return MACB_BFEXT(DATA, frame);
222}
223
Joe Hershberger9e5742b2013-06-24 19:06:38 -0500224void __weak arch_get_mdio_control(const char *name)
Shiraz Hashim77cdf0f2012-12-13 17:22:52 +0530225{
226 return;
227}
228
Bo Shen7d91deb2013-04-24 15:59:27 +0800229#if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
Semih Hazar790088e2009-12-17 15:07:15 +0200230
Joe Hershberger1fbcbed2016-08-08 11:28:38 -0500231int macb_miiphy_read(struct mii_dev *bus, int phy_adr, int devad, int reg)
Semih Hazar790088e2009-12-17 15:07:15 +0200232{
Joe Hershberger1fbcbed2016-08-08 11:28:38 -0500233 u16 value = 0;
Simon Glass75c5d182016-05-05 07:28:11 -0600234#ifdef CONFIG_DM_ETH
Joe Hershberger1fbcbed2016-08-08 11:28:38 -0500235 struct udevice *dev = eth_get_dev_by_name(bus->name);
Simon Glass75c5d182016-05-05 07:28:11 -0600236 struct macb_device *macb = dev_get_priv(dev);
237#else
Joe Hershberger1fbcbed2016-08-08 11:28:38 -0500238 struct eth_device *dev = eth_get_dev_by_name(bus->name);
Semih Hazar790088e2009-12-17 15:07:15 +0200239 struct macb_device *macb = to_macb(dev);
Simon Glass75c5d182016-05-05 07:28:11 -0600240#endif
Semih Hazar790088e2009-12-17 15:07:15 +0200241
Andreas Bießmann1e868122014-05-26 22:55:18 +0200242 if (macb->phy_addr != phy_adr)
Semih Hazar790088e2009-12-17 15:07:15 +0200243 return -1;
244
Joe Hershberger1fbcbed2016-08-08 11:28:38 -0500245 arch_get_mdio_control(bus->name);
246 value = macb_mdio_read(macb, reg);
Semih Hazar790088e2009-12-17 15:07:15 +0200247
Joe Hershberger1fbcbed2016-08-08 11:28:38 -0500248 return value;
Semih Hazar790088e2009-12-17 15:07:15 +0200249}
250
Joe Hershberger1fbcbed2016-08-08 11:28:38 -0500251int macb_miiphy_write(struct mii_dev *bus, int phy_adr, int devad, int reg,
252 u16 value)
Semih Hazar790088e2009-12-17 15:07:15 +0200253{
Simon Glass75c5d182016-05-05 07:28:11 -0600254#ifdef CONFIG_DM_ETH
Joe Hershberger1fbcbed2016-08-08 11:28:38 -0500255 struct udevice *dev = eth_get_dev_by_name(bus->name);
Simon Glass75c5d182016-05-05 07:28:11 -0600256 struct macb_device *macb = dev_get_priv(dev);
257#else
Joe Hershberger1fbcbed2016-08-08 11:28:38 -0500258 struct eth_device *dev = eth_get_dev_by_name(bus->name);
Semih Hazar790088e2009-12-17 15:07:15 +0200259 struct macb_device *macb = to_macb(dev);
Simon Glass75c5d182016-05-05 07:28:11 -0600260#endif
Semih Hazar790088e2009-12-17 15:07:15 +0200261
Andreas Bießmann1e868122014-05-26 22:55:18 +0200262 if (macb->phy_addr != phy_adr)
Semih Hazar790088e2009-12-17 15:07:15 +0200263 return -1;
264
Joe Hershberger1fbcbed2016-08-08 11:28:38 -0500265 arch_get_mdio_control(bus->name);
Semih Hazar790088e2009-12-17 15:07:15 +0200266 macb_mdio_write(macb, reg, value);
267
268 return 0;
269}
270#endif
271
Wu, Josh18052402014-05-27 16:31:05 +0800272#define RX 1
273#define TX 0
274static inline void macb_invalidate_ring_desc(struct macb_device *macb, bool rx)
275{
276 if (rx)
Heiko Schocher8353f9d2016-08-29 07:46:11 +0200277 invalidate_dcache_range(macb->rx_ring_dma,
278 ALIGN(macb->rx_ring_dma + MACB_RX_DMA_DESC_SIZE,
279 PKTALIGN));
Wu, Josh18052402014-05-27 16:31:05 +0800280 else
Heiko Schocher8353f9d2016-08-29 07:46:11 +0200281 invalidate_dcache_range(macb->tx_ring_dma,
282 ALIGN(macb->tx_ring_dma + MACB_TX_DMA_DESC_SIZE,
283 PKTALIGN));
Wu, Josh18052402014-05-27 16:31:05 +0800284}
285
286static inline void macb_flush_ring_desc(struct macb_device *macb, bool rx)
287{
288 if (rx)
289 flush_dcache_range(macb->rx_ring_dma, macb->rx_ring_dma +
Heiko Schocher8353f9d2016-08-29 07:46:11 +0200290 ALIGN(MACB_RX_DMA_DESC_SIZE, PKTALIGN));
Wu, Josh18052402014-05-27 16:31:05 +0800291 else
292 flush_dcache_range(macb->tx_ring_dma, macb->tx_ring_dma +
Heiko Schocher8353f9d2016-08-29 07:46:11 +0200293 ALIGN(MACB_TX_DMA_DESC_SIZE, PKTALIGN));
Wu, Josh18052402014-05-27 16:31:05 +0800294}
295
296static inline void macb_flush_rx_buffer(struct macb_device *macb)
297{
298 flush_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
Heiko Schocher8353f9d2016-08-29 07:46:11 +0200299 ALIGN(MACB_RX_BUFFER_SIZE, PKTALIGN));
Wu, Josh18052402014-05-27 16:31:05 +0800300}
301
302static inline void macb_invalidate_rx_buffer(struct macb_device *macb)
303{
304 invalidate_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
Heiko Schocher8353f9d2016-08-29 07:46:11 +0200305 ALIGN(MACB_RX_BUFFER_SIZE, PKTALIGN));
Wu, Josh18052402014-05-27 16:31:05 +0800306}
Semih Hazar790088e2009-12-17 15:07:15 +0200307
Jon Loeligerb1d408a2007-07-09 17:30:01 -0500308#if defined(CONFIG_CMD_NET)
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100309
Simon Glass5ad27512016-05-05 07:28:09 -0600310static int _macb_send(struct macb_device *macb, const char *name, void *packet,
311 int length)
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100312{
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100313 unsigned long paddr, ctrl;
314 unsigned int tx_head = macb->tx_head;
315 int i;
316
317 paddr = dma_map_single(packet, length, DMA_TO_DEVICE);
318
319 ctrl = length & TXBUF_FRMLEN_MASK;
320 ctrl |= TXBUF_FRAME_END;
Andreas Bießmann1e868122014-05-26 22:55:18 +0200321 if (tx_head == (MACB_TX_RING_SIZE - 1)) {
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100322 ctrl |= TXBUF_WRAP;
323 macb->tx_head = 0;
Andreas Bießmann1e868122014-05-26 22:55:18 +0200324 } else {
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100325 macb->tx_head++;
Andreas Bießmann1e868122014-05-26 22:55:18 +0200326 }
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100327
328 macb->tx_ring[tx_head].ctrl = ctrl;
329 macb->tx_ring[tx_head].addr = paddr;
Haavard Skinnemoen996e1472007-05-02 13:22:38 +0200330 barrier();
Wu, Josh18052402014-05-27 16:31:05 +0800331 macb_flush_ring_desc(macb, TX);
332 /* Do we need check paddr and length is dcache line aligned? */
Simon Glass3d5dcef2016-05-05 07:28:10 -0600333 flush_dcache_range(paddr, paddr + ALIGN(length, ARCH_DMA_MINALIGN));
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100334 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
335
336 /*
337 * I guess this is necessary because the networking core may
338 * re-use the transmit buffer as soon as we return...
339 */
Andreas Bießmann1e868122014-05-26 22:55:18 +0200340 for (i = 0; i <= MACB_TX_TIMEOUT; i++) {
Haavard Skinnemoen996e1472007-05-02 13:22:38 +0200341 barrier();
Wu, Josh18052402014-05-27 16:31:05 +0800342 macb_invalidate_ring_desc(macb, TX);
Haavard Skinnemoen996e1472007-05-02 13:22:38 +0200343 ctrl = macb->tx_ring[tx_head].ctrl;
344 if (ctrl & TXBUF_USED)
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100345 break;
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100346 udelay(1);
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100347 }
348
349 dma_unmap_single(packet, length, paddr);
350
Andreas Bießmann1e868122014-05-26 22:55:18 +0200351 if (i <= MACB_TX_TIMEOUT) {
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100352 if (ctrl & TXBUF_UNDERRUN)
Simon Glass5ad27512016-05-05 07:28:09 -0600353 printf("%s: TX underrun\n", name);
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100354 if (ctrl & TXBUF_EXHAUSTED)
Simon Glass5ad27512016-05-05 07:28:09 -0600355 printf("%s: TX buffers exhausted in mid frame\n", name);
Haavard Skinnemoen996e1472007-05-02 13:22:38 +0200356 } else {
Simon Glass5ad27512016-05-05 07:28:09 -0600357 printf("%s: TX timeout\n", name);
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100358 }
359
360 /* No one cares anyway */
361 return 0;
362}
363
364static void reclaim_rx_buffers(struct macb_device *macb,
365 unsigned int new_tail)
366{
367 unsigned int i;
368
369 i = macb->rx_tail;
Wu, Josh18052402014-05-27 16:31:05 +0800370
371 macb_invalidate_ring_desc(macb, RX);
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100372 while (i > new_tail) {
373 macb->rx_ring[i].addr &= ~RXADDR_USED;
374 i++;
Andreas Bießmann1e868122014-05-26 22:55:18 +0200375 if (i > MACB_RX_RING_SIZE)
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100376 i = 0;
377 }
378
379 while (i < new_tail) {
380 macb->rx_ring[i].addr &= ~RXADDR_USED;
381 i++;
382 }
383
Haavard Skinnemoen996e1472007-05-02 13:22:38 +0200384 barrier();
Wu, Josh18052402014-05-27 16:31:05 +0800385 macb_flush_ring_desc(macb, RX);
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100386 macb->rx_tail = new_tail;
387}
388
Simon Glass5ad27512016-05-05 07:28:09 -0600389static int _macb_recv(struct macb_device *macb, uchar **packetp)
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100390{
Simon Glass5ad27512016-05-05 07:28:09 -0600391 unsigned int next_rx_tail = macb->next_rx_tail;
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100392 void *buffer;
393 int length;
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100394 u32 status;
395
Simon Glass5ad27512016-05-05 07:28:09 -0600396 macb->wrapped = false;
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100397 for (;;) {
Wu, Josh18052402014-05-27 16:31:05 +0800398 macb_invalidate_ring_desc(macb, RX);
399
Simon Glass5ad27512016-05-05 07:28:09 -0600400 if (!(macb->rx_ring[next_rx_tail].addr & RXADDR_USED))
401 return -EAGAIN;
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100402
Simon Glass5ad27512016-05-05 07:28:09 -0600403 status = macb->rx_ring[next_rx_tail].ctrl;
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100404 if (status & RXBUF_FRAME_START) {
Simon Glass5ad27512016-05-05 07:28:09 -0600405 if (next_rx_tail != macb->rx_tail)
406 reclaim_rx_buffers(macb, next_rx_tail);
407 macb->wrapped = false;
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100408 }
409
410 if (status & RXBUF_FRAME_END) {
411 buffer = macb->rx_buffer + 128 * macb->rx_tail;
412 length = status & RXBUF_FRMLEN_MASK;
Wu, Josh18052402014-05-27 16:31:05 +0800413
414 macb_invalidate_rx_buffer(macb);
Simon Glass5ad27512016-05-05 07:28:09 -0600415 if (macb->wrapped) {
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100416 unsigned int headlen, taillen;
417
Andreas Bießmann1e868122014-05-26 22:55:18 +0200418 headlen = 128 * (MACB_RX_RING_SIZE
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100419 - macb->rx_tail);
420 taillen = length - headlen;
Joe Hershberger9f09a362015-04-08 01:41:06 -0500421 memcpy((void *)net_rx_packets[0],
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100422 buffer, headlen);
Joe Hershberger9f09a362015-04-08 01:41:06 -0500423 memcpy((void *)net_rx_packets[0] + headlen,
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100424 macb->rx_buffer, taillen);
Simon Glass5ad27512016-05-05 07:28:09 -0600425 *packetp = (void *)net_rx_packets[0];
426 } else {
427 *packetp = buffer;
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100428 }
429
Simon Glass5ad27512016-05-05 07:28:09 -0600430 if (++next_rx_tail >= MACB_RX_RING_SIZE)
431 next_rx_tail = 0;
432 macb->next_rx_tail = next_rx_tail;
433 return length;
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100434 } else {
Simon Glass5ad27512016-05-05 07:28:09 -0600435 if (++next_rx_tail >= MACB_RX_RING_SIZE) {
436 macb->wrapped = true;
437 next_rx_tail = 0;
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100438 }
439 }
Haavard Skinnemoen996e1472007-05-02 13:22:38 +0200440 barrier();
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100441 }
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100442}
443
Simon Glass5ad27512016-05-05 07:28:09 -0600444static void macb_phy_reset(struct macb_device *macb, const char *name)
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100445{
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100446 int i;
Haavard Skinnemoenb3ad7722007-05-02 13:31:53 +0200447 u16 status, adv;
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100448
449 adv = ADVERTISE_CSMA | ADVERTISE_ALL;
450 macb_mdio_write(macb, MII_ADVERTISE, adv);
Simon Glass5ad27512016-05-05 07:28:09 -0600451 printf("%s: Starting autonegotiation...\n", name);
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100452 macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE
453 | BMCR_ANRESTART));
454
Andreas Bießmann1e868122014-05-26 22:55:18 +0200455 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100456 status = macb_mdio_read(macb, MII_BMSR);
457 if (status & BMSR_ANEGCOMPLETE)
458 break;
459 udelay(100);
460 }
461
462 if (status & BMSR_ANEGCOMPLETE)
Simon Glass5ad27512016-05-05 07:28:09 -0600463 printf("%s: Autonegotiation complete\n", name);
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100464 else
465 printf("%s: Autonegotiation timed out (status=0x%04x)\n",
Simon Glass5ad27512016-05-05 07:28:09 -0600466 name, status);
Haavard Skinnemoenb3ad7722007-05-02 13:31:53 +0200467}
468
Wenyou Yang7b811852016-05-17 13:11:35 +0800469static int macb_phy_find(struct macb_device *macb, const char *name)
Gunnar Rangoy6dd74f32009-01-23 12:56:31 +0100470{
471 int i;
472 u16 phy_id;
473
474 /* Search for PHY... */
475 for (i = 0; i < 32; i++) {
476 macb->phy_addr = i;
477 phy_id = macb_mdio_read(macb, MII_PHYSID1);
478 if (phy_id != 0xffff) {
Wenyou Yang7b811852016-05-17 13:11:35 +0800479 printf("%s: PHY present at %d\n", name, i);
Wilson Lee41d6d1e2017-08-22 20:25:07 -0700480 return 0;
Gunnar Rangoy6dd74f32009-01-23 12:56:31 +0100481 }
482 }
483
484 /* PHY isn't up to snuff */
Wenyou Yang7b811852016-05-17 13:11:35 +0800485 printf("%s: PHY not found\n", name);
Gunnar Rangoy6dd74f32009-01-23 12:56:31 +0100486
Wilson Lee41d6d1e2017-08-22 20:25:07 -0700487 return -ENODEV;
488}
489
490/**
491 * macb_linkspd_cb - Linkspeed change callback function
492 * @regs: Base Register of MACB devices
493 * @speed: Linkspeed
494 * Returns 0 when operation success and negative errno number
495 * when operation failed.
496 */
497int __weak macb_linkspd_cb(void *regs, unsigned int speed)
498{
Gunnar Rangoy6dd74f32009-01-23 12:56:31 +0100499 return 0;
500}
Gunnar Rangoy6dd74f32009-01-23 12:56:31 +0100501
Wenyou Yang7b811852016-05-17 13:11:35 +0800502#ifdef CONFIG_DM_ETH
503static int macb_phy_init(struct udevice *dev, const char *name)
504#else
Simon Glass5ad27512016-05-05 07:28:09 -0600505static int macb_phy_init(struct macb_device *macb, const char *name)
Wenyou Yang7b811852016-05-17 13:11:35 +0800506#endif
Haavard Skinnemoenb3ad7722007-05-02 13:31:53 +0200507{
Wenyou Yang7b811852016-05-17 13:11:35 +0800508#ifdef CONFIG_DM_ETH
509 struct macb_device *macb = dev_get_priv(dev);
510#endif
Haavard Skinnemoenb3ad7722007-05-02 13:31:53 +0200511 u32 ncfgr;
512 u16 phy_id, status, adv, lpa;
513 int media, speed, duplex;
Wilson Lee41d6d1e2017-08-22 20:25:07 -0700514 int ret;
Haavard Skinnemoenb3ad7722007-05-02 13:31:53 +0200515 int i;
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100516
Simon Glass5ad27512016-05-05 07:28:09 -0600517 arch_get_mdio_control(name);
Gunnar Rangoy6dd74f32009-01-23 12:56:31 +0100518 /* Auto-detect phy_addr */
Wilson Lee41d6d1e2017-08-22 20:25:07 -0700519 ret = macb_phy_find(macb, name);
520 if (ret)
521 return ret;
Gunnar Rangoy6dd74f32009-01-23 12:56:31 +0100522
Haavard Skinnemoenb3ad7722007-05-02 13:31:53 +0200523 /* Check if the PHY is up to snuff... */
524 phy_id = macb_mdio_read(macb, MII_PHYSID1);
525 if (phy_id == 0xffff) {
Simon Glass5ad27512016-05-05 07:28:09 -0600526 printf("%s: No PHY present\n", name);
Wilson Lee41d6d1e2017-08-22 20:25:07 -0700527 return -ENODEV;
Haavard Skinnemoenb3ad7722007-05-02 13:31:53 +0200528 }
529
Bo Shen7d91deb2013-04-24 15:59:27 +0800530#ifdef CONFIG_PHYLIB
Wenyou Yang7b811852016-05-17 13:11:35 +0800531#ifdef CONFIG_DM_ETH
Wenyou Yang44835ea2017-04-14 14:36:04 +0800532 macb->phydev = phy_connect(macb->bus, macb->phy_addr, dev,
Wenyou Yang7b811852016-05-17 13:11:35 +0800533 macb->phy_interface);
534#else
Bo Shene04fe552013-08-19 10:35:47 +0800535 /* need to consider other phy interface mode */
Wenyou Yang44835ea2017-04-14 14:36:04 +0800536 macb->phydev = phy_connect(macb->bus, macb->phy_addr, &macb->netdev,
Bo Shene04fe552013-08-19 10:35:47 +0800537 PHY_INTERFACE_MODE_RGMII);
Wenyou Yang7b811852016-05-17 13:11:35 +0800538#endif
Wenyou Yang44835ea2017-04-14 14:36:04 +0800539 if (!macb->phydev) {
Bo Shene04fe552013-08-19 10:35:47 +0800540 printf("phy_connect failed\n");
541 return -ENODEV;
542 }
543
Wenyou Yang44835ea2017-04-14 14:36:04 +0800544 phy_config(macb->phydev);
Bo Shen7d91deb2013-04-24 15:59:27 +0800545#endif
546
Haavard Skinnemoenb3ad7722007-05-02 13:31:53 +0200547 status = macb_mdio_read(macb, MII_BMSR);
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100548 if (!(status & BMSR_LSTATUS)) {
Haavard Skinnemoenb3ad7722007-05-02 13:31:53 +0200549 /* Try to re-negotiate if we don't have link already. */
Simon Glass5ad27512016-05-05 07:28:09 -0600550 macb_phy_reset(macb, name);
Haavard Skinnemoenb3ad7722007-05-02 13:31:53 +0200551
Andreas Bießmann1e868122014-05-26 22:55:18 +0200552 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100553 status = macb_mdio_read(macb, MII_BMSR);
554 if (status & BMSR_LSTATUS)
555 break;
Haavard Skinnemoenb3ad7722007-05-02 13:31:53 +0200556 udelay(100);
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100557 }
558 }
559
560 if (!(status & BMSR_LSTATUS)) {
561 printf("%s: link down (status: 0x%04x)\n",
Simon Glass5ad27512016-05-05 07:28:09 -0600562 name, status);
Wilson Lee41d6d1e2017-08-22 20:25:07 -0700563 return -ENETDOWN;
Bo Shen6f7d7d92013-04-24 15:59:28 +0800564 }
565
Gregory CLEMENTf1a1e582015-12-16 14:50:34 +0100566 /* First check for GMAC and that it is GiB capable */
567 if (gem_is_gigabit_capable(macb)) {
Bo Shen6f7d7d92013-04-24 15:59:28 +0800568 lpa = macb_mdio_read(macb, MII_STAT1000);
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100569
Andreas Bießmannd43a89a2014-09-18 23:46:48 +0200570 if (lpa & (LPA_1000FULL | LPA_1000HALF)) {
571 duplex = ((lpa & LPA_1000FULL) ? 1 : 0);
572
573 printf("%s: link up, 1000Mbps %s-duplex (lpa: 0x%04x)\n",
Simon Glass5ad27512016-05-05 07:28:09 -0600574 name,
Bo Shen6f7d7d92013-04-24 15:59:28 +0800575 duplex ? "full" : "half",
576 lpa);
577
578 ncfgr = macb_readl(macb, NCFGR);
Andreas Bießmannd43a89a2014-09-18 23:46:48 +0200579 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
580 ncfgr |= GEM_BIT(GBE);
581
Bo Shen6f7d7d92013-04-24 15:59:28 +0800582 if (duplex)
583 ncfgr |= MACB_BIT(FD);
Andreas Bießmannd43a89a2014-09-18 23:46:48 +0200584
Bo Shen6f7d7d92013-04-24 15:59:28 +0800585 macb_writel(macb, NCFGR, ncfgr);
586
Wilson Lee41d6d1e2017-08-22 20:25:07 -0700587 ret = macb_linkspd_cb(macb->regs, _1000BASET);
588 if (ret)
589 return ret;
590
591 return 0;
Bo Shen6f7d7d92013-04-24 15:59:28 +0800592 }
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100593 }
Bo Shen6f7d7d92013-04-24 15:59:28 +0800594
595 /* fall back for EMAC checking */
596 adv = macb_mdio_read(macb, MII_ADVERTISE);
597 lpa = macb_mdio_read(macb, MII_LPA);
598 media = mii_nway_result(lpa & adv);
599 speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
600 ? 1 : 0);
601 duplex = (media & ADVERTISE_FULL) ? 1 : 0;
602 printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n",
Simon Glass5ad27512016-05-05 07:28:09 -0600603 name,
Bo Shen6f7d7d92013-04-24 15:59:28 +0800604 speed ? "100" : "10",
605 duplex ? "full" : "half",
606 lpa);
607
608 ncfgr = macb_readl(macb, NCFGR);
Bo Shenfe19ef32015-03-04 13:35:16 +0800609 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD) | GEM_BIT(GBE));
Wilson Lee41d6d1e2017-08-22 20:25:07 -0700610 if (speed) {
Bo Shen6f7d7d92013-04-24 15:59:28 +0800611 ncfgr |= MACB_BIT(SPD);
Wilson Lee41d6d1e2017-08-22 20:25:07 -0700612 ret = macb_linkspd_cb(macb->regs, _100BASET);
613 } else {
614 ret = macb_linkspd_cb(macb->regs, _10BASET);
615 }
616
617 if (ret)
618 return ret;
619
Bo Shen6f7d7d92013-04-24 15:59:28 +0800620 if (duplex)
621 ncfgr |= MACB_BIT(FD);
622 macb_writel(macb, NCFGR, ncfgr);
623
Wilson Lee41d6d1e2017-08-22 20:25:07 -0700624 return 0;
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100625}
626
Wu, Josh012d68d2015-06-03 16:45:44 +0800627static int gmac_init_multi_queues(struct macb_device *macb)
628{
629 int i, num_queues = 1;
630 u32 queue_mask;
631
632 /* bit 0 is never set but queue 0 always exists */
633 queue_mask = gem_readl(macb, DCFG6) & 0xff;
634 queue_mask |= 0x1;
635
636 for (i = 1; i < MACB_MAX_QUEUES; i++)
637 if (queue_mask & (1 << i))
638 num_queues++;
639
640 macb->dummy_desc->ctrl = TXBUF_USED;
641 macb->dummy_desc->addr = 0;
642 flush_dcache_range(macb->dummy_desc_dma, macb->dummy_desc_dma +
Heiko Schocher8353f9d2016-08-29 07:46:11 +0200643 ALIGN(MACB_TX_DUMMY_DMA_DESC_SIZE, PKTALIGN));
Wu, Josh012d68d2015-06-03 16:45:44 +0800644
645 for (i = 1; i < num_queues; i++)
646 gem_writel_queue_TBQP(macb, macb->dummy_desc_dma, i - 1);
647
648 return 0;
649}
650
Wenyou Yang7b811852016-05-17 13:11:35 +0800651#ifdef CONFIG_DM_ETH
652static int _macb_init(struct udevice *dev, const char *name)
653#else
Simon Glass5ad27512016-05-05 07:28:09 -0600654static int _macb_init(struct macb_device *macb, const char *name)
Wenyou Yang7b811852016-05-17 13:11:35 +0800655#endif
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100656{
Wenyou Yang7b811852016-05-17 13:11:35 +0800657#ifdef CONFIG_DM_ETH
658 struct macb_device *macb = dev_get_priv(dev);
659#endif
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100660 unsigned long paddr;
Wilson Lee41d6d1e2017-08-22 20:25:07 -0700661 int ret;
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100662 int i;
663
664 /*
665 * macb_halt should have been called at some point before now,
666 * so we'll assume the controller is idle.
667 */
668
669 /* initialize DMA descriptors */
670 paddr = macb->rx_buffer_dma;
Andreas Bießmann1e868122014-05-26 22:55:18 +0200671 for (i = 0; i < MACB_RX_RING_SIZE; i++) {
672 if (i == (MACB_RX_RING_SIZE - 1))
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100673 paddr |= RXADDR_WRAP;
674 macb->rx_ring[i].addr = paddr;
675 macb->rx_ring[i].ctrl = 0;
676 paddr += 128;
677 }
Wu, Josh18052402014-05-27 16:31:05 +0800678 macb_flush_ring_desc(macb, RX);
679 macb_flush_rx_buffer(macb);
680
Andreas Bießmann1e868122014-05-26 22:55:18 +0200681 for (i = 0; i < MACB_TX_RING_SIZE; i++) {
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100682 macb->tx_ring[i].addr = 0;
Andreas Bießmann1e868122014-05-26 22:55:18 +0200683 if (i == (MACB_TX_RING_SIZE - 1))
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100684 macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP;
685 else
686 macb->tx_ring[i].ctrl = TXBUF_USED;
687 }
Wu, Josh18052402014-05-27 16:31:05 +0800688 macb_flush_ring_desc(macb, TX);
689
Andreas Bießmann1e868122014-05-26 22:55:18 +0200690 macb->rx_tail = 0;
691 macb->tx_head = 0;
692 macb->tx_tail = 0;
Simon Glass5ad27512016-05-05 07:28:09 -0600693 macb->next_rx_tail = 0;
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100694
Wilson Lee41d6d1e2017-08-22 20:25:07 -0700695#ifdef CONFIG_MACB_ZYNQ
696 macb_writel(macb, DMACFG, MACB_ZYNQ_GEM_DMACR_INIT);
697#endif
698
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100699 macb_writel(macb, RBQP, macb->rx_ring_dma);
700 macb_writel(macb, TBQP, macb->tx_ring_dma);
701
Bo Shen6f7d7d92013-04-24 15:59:28 +0800702 if (macb_is_gem(macb)) {
Wu, Josh012d68d2015-06-03 16:45:44 +0800703 /* Check the multi queue and initialize the queue for tx */
704 gmac_init_multi_queues(macb);
705
Bo Shen4660b332014-11-10 15:24:01 +0800706 /*
707 * When the GMAC IP with GE feature, this bit is used to
708 * select interface between RGMII and GMII.
709 * When the GMAC IP without GE feature, this bit is used
710 * to select interface between RMII and MII.
711 */
Wenyou Yang7b811852016-05-17 13:11:35 +0800712#ifdef CONFIG_DM_ETH
Wenyou Yang5653dbc2017-04-20 11:13:13 +0800713 if ((macb->phy_interface == PHY_INTERFACE_MODE_RMII) ||
714 (macb->phy_interface == PHY_INTERFACE_MODE_RGMII))
Wenyou Yang7b811852016-05-17 13:11:35 +0800715 gem_writel(macb, UR, GEM_BIT(RGMII));
716 else
717 gem_writel(macb, UR, 0);
718#else
Bo Shen4660b332014-11-10 15:24:01 +0800719#if defined(CONFIG_RGMII) || defined(CONFIG_RMII)
Bo Shen6f7d7d92013-04-24 15:59:28 +0800720 gem_writel(macb, UR, GEM_BIT(RGMII));
721#else
722 gem_writel(macb, UR, 0);
723#endif
Wenyou Yang7b811852016-05-17 13:11:35 +0800724#endif
Bo Shen6f7d7d92013-04-24 15:59:28 +0800725 } else {
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100726 /* choose RMII or MII mode. This depends on the board */
Wenyou Yang7b811852016-05-17 13:11:35 +0800727#ifdef CONFIG_DM_ETH
728#ifdef CONFIG_AT91FAMILY
729 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII) {
730 macb_writel(macb, USRIO,
731 MACB_BIT(RMII) | MACB_BIT(CLKEN));
732 } else {
733 macb_writel(macb, USRIO, MACB_BIT(CLKEN));
734 }
735#else
736 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII)
737 macb_writel(macb, USRIO, 0);
738 else
739 macb_writel(macb, USRIO, MACB_BIT(MII));
740#endif
741#else
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100742#ifdef CONFIG_RMII
Bo Shencc29ce52013-04-24 15:59:26 +0800743#ifdef CONFIG_AT91FAMILY
Stelian Pop87a82542008-01-03 21:15:56 +0000744 macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN));
745#else
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100746 macb_writel(macb, USRIO, 0);
Stelian Pop87a82542008-01-03 21:15:56 +0000747#endif
748#else
Bo Shencc29ce52013-04-24 15:59:26 +0800749#ifdef CONFIG_AT91FAMILY
Stelian Pop87a82542008-01-03 21:15:56 +0000750 macb_writel(macb, USRIO, MACB_BIT(CLKEN));
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100751#else
752 macb_writel(macb, USRIO, MACB_BIT(MII));
753#endif
Stelian Pop87a82542008-01-03 21:15:56 +0000754#endif /* CONFIG_RMII */
Wenyou Yang7b811852016-05-17 13:11:35 +0800755#endif
Bo Shen6f7d7d92013-04-24 15:59:28 +0800756 }
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100757
Wenyou Yang7b811852016-05-17 13:11:35 +0800758#ifdef CONFIG_DM_ETH
Wilson Lee41d6d1e2017-08-22 20:25:07 -0700759 ret = macb_phy_init(dev, name);
Wenyou Yang7b811852016-05-17 13:11:35 +0800760#else
Wilson Lee41d6d1e2017-08-22 20:25:07 -0700761 ret = macb_phy_init(macb, name);
Wenyou Yang7b811852016-05-17 13:11:35 +0800762#endif
Wilson Lee41d6d1e2017-08-22 20:25:07 -0700763 if (ret)
764 return ret;
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100765
766 /* Enable TX and RX */
767 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE));
768
Ben Warrende9fcb52008-01-09 18:15:53 -0500769 return 0;
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100770}
771
Simon Glass5ad27512016-05-05 07:28:09 -0600772static void _macb_halt(struct macb_device *macb)
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100773{
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100774 u32 ncr, tsr;
775
776 /* Halt the controller and wait for any ongoing transmission to end. */
777 ncr = macb_readl(macb, NCR);
778 ncr |= MACB_BIT(THALT);
779 macb_writel(macb, NCR, ncr);
780
781 do {
782 tsr = macb_readl(macb, TSR);
783 } while (tsr & MACB_BIT(TGO));
784
785 /* Disable TX and RX, and clear statistics */
786 macb_writel(macb, NCR, MACB_BIT(CLRSTAT));
787}
788
Simon Glass5ad27512016-05-05 07:28:09 -0600789static int _macb_write_hwaddr(struct macb_device *macb, unsigned char *enetaddr)
Ben Warren33f84312010-06-01 11:55:42 -0700790{
Ben Warren33f84312010-06-01 11:55:42 -0700791 u32 hwaddr_bottom;
792 u16 hwaddr_top;
793
794 /* set hardware address */
Simon Glass5ad27512016-05-05 07:28:09 -0600795 hwaddr_bottom = enetaddr[0] | enetaddr[1] << 8 |
796 enetaddr[2] << 16 | enetaddr[3] << 24;
Ben Warren33f84312010-06-01 11:55:42 -0700797 macb_writel(macb, SA1B, hwaddr_bottom);
Simon Glass5ad27512016-05-05 07:28:09 -0600798 hwaddr_top = enetaddr[4] | enetaddr[5] << 8;
Ben Warren33f84312010-06-01 11:55:42 -0700799 macb_writel(macb, SA1T, hwaddr_top);
800 return 0;
801}
802
Bo Shen6f7d7d92013-04-24 15:59:28 +0800803static u32 macb_mdc_clk_div(int id, struct macb_device *macb)
804{
805 u32 config;
Wenyou Yang19449362017-02-14 16:24:40 +0800806#if defined(CONFIG_DM_ETH) && defined(CONFIG_CLK)
Wenyou Yang3d8d3482016-11-02 10:06:56 +0800807 unsigned long macb_hz = macb->pclk_rate;
808#else
Bo Shen6f7d7d92013-04-24 15:59:28 +0800809 unsigned long macb_hz = get_macb_pclk_rate(id);
Wenyou Yang3d8d3482016-11-02 10:06:56 +0800810#endif
Bo Shen6f7d7d92013-04-24 15:59:28 +0800811
812 if (macb_hz < 20000000)
813 config = MACB_BF(CLK, MACB_CLK_DIV8);
814 else if (macb_hz < 40000000)
815 config = MACB_BF(CLK, MACB_CLK_DIV16);
816 else if (macb_hz < 80000000)
817 config = MACB_BF(CLK, MACB_CLK_DIV32);
818 else
819 config = MACB_BF(CLK, MACB_CLK_DIV64);
820
821 return config;
822}
823
824static u32 gem_mdc_clk_div(int id, struct macb_device *macb)
825{
826 u32 config;
Wenyou Yang3d8d3482016-11-02 10:06:56 +0800827
Wenyou Yang19449362017-02-14 16:24:40 +0800828#if defined(CONFIG_DM_ETH) && defined(CONFIG_CLK)
Wenyou Yang3d8d3482016-11-02 10:06:56 +0800829 unsigned long macb_hz = macb->pclk_rate;
830#else
Bo Shen6f7d7d92013-04-24 15:59:28 +0800831 unsigned long macb_hz = get_macb_pclk_rate(id);
Wenyou Yang3d8d3482016-11-02 10:06:56 +0800832#endif
Bo Shen6f7d7d92013-04-24 15:59:28 +0800833
834 if (macb_hz < 20000000)
835 config = GEM_BF(CLK, GEM_CLK_DIV8);
836 else if (macb_hz < 40000000)
837 config = GEM_BF(CLK, GEM_CLK_DIV16);
838 else if (macb_hz < 80000000)
839 config = GEM_BF(CLK, GEM_CLK_DIV32);
840 else if (macb_hz < 120000000)
841 config = GEM_BF(CLK, GEM_CLK_DIV48);
842 else if (macb_hz < 160000000)
843 config = GEM_BF(CLK, GEM_CLK_DIV64);
844 else
845 config = GEM_BF(CLK, GEM_CLK_DIV96);
846
847 return config;
848}
849
Bo Shen0e6624a2013-09-18 15:07:44 +0800850/*
851 * Get the DMA bus width field of the network configuration register that we
852 * should program. We find the width from decoding the design configuration
853 * register to find the maximum supported data bus width.
854 */
855static u32 macb_dbw(struct macb_device *macb)
856{
857 switch (GEM_BFEXT(DBWDEF, gem_readl(macb, DCFG1))) {
858 case 4:
859 return GEM_BF(DBW, GEM_DBW128);
860 case 2:
861 return GEM_BF(DBW, GEM_DBW64);
862 case 1:
863 default:
864 return GEM_BF(DBW, GEM_DBW32);
865 }
Simon Glass5ad27512016-05-05 07:28:09 -0600866}
867
868static void _macb_eth_initialize(struct macb_device *macb)
869{
870 int id = 0; /* This is not used by functions we call */
871 u32 ncfgr;
872
873 /* TODO: we need check the rx/tx_ring_dma is dcache line aligned */
874 macb->rx_buffer = dma_alloc_coherent(MACB_RX_BUFFER_SIZE,
875 &macb->rx_buffer_dma);
876 macb->rx_ring = dma_alloc_coherent(MACB_RX_DMA_DESC_SIZE,
877 &macb->rx_ring_dma);
878 macb->tx_ring = dma_alloc_coherent(MACB_TX_DMA_DESC_SIZE,
879 &macb->tx_ring_dma);
880 macb->dummy_desc = dma_alloc_coherent(MACB_TX_DUMMY_DMA_DESC_SIZE,
881 &macb->dummy_desc_dma);
882
883 /*
884 * Do some basic initialization so that we at least can talk
885 * to the PHY
886 */
887 if (macb_is_gem(macb)) {
888 ncfgr = gem_mdc_clk_div(id, macb);
889 ncfgr |= macb_dbw(macb);
890 } else {
891 ncfgr = macb_mdc_clk_div(id, macb);
892 }
893
894 macb_writel(macb, NCFGR, ncfgr);
895}
896
Simon Glass75c5d182016-05-05 07:28:11 -0600897#ifndef CONFIG_DM_ETH
Simon Glass5ad27512016-05-05 07:28:09 -0600898static int macb_send(struct eth_device *netdev, void *packet, int length)
899{
900 struct macb_device *macb = to_macb(netdev);
901
902 return _macb_send(macb, netdev->name, packet, length);
Bo Shen0e6624a2013-09-18 15:07:44 +0800903}
904
Simon Glass5ad27512016-05-05 07:28:09 -0600905static int macb_recv(struct eth_device *netdev)
906{
907 struct macb_device *macb = to_macb(netdev);
908 uchar *packet;
909 int length;
910
911 macb->wrapped = false;
912 for (;;) {
913 macb->next_rx_tail = macb->rx_tail;
914 length = _macb_recv(macb, &packet);
915 if (length >= 0) {
916 net_process_received_packet(packet, length);
917 reclaim_rx_buffers(macb, macb->next_rx_tail);
Heinrich Schuchardt6c4aae92018-03-18 11:32:53 +0100918 } else {
Simon Glass5ad27512016-05-05 07:28:09 -0600919 return length;
920 }
921 }
922}
923
924static int macb_init(struct eth_device *netdev, bd_t *bd)
925{
926 struct macb_device *macb = to_macb(netdev);
927
928 return _macb_init(macb, netdev->name);
929}
930
931static void macb_halt(struct eth_device *netdev)
932{
933 struct macb_device *macb = to_macb(netdev);
934
935 return _macb_halt(macb);
936}
937
938static int macb_write_hwaddr(struct eth_device *netdev)
939{
940 struct macb_device *macb = to_macb(netdev);
941
942 return _macb_write_hwaddr(macb, netdev->enetaddr);
943}
944
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100945int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
946{
947 struct macb_device *macb;
948 struct eth_device *netdev;
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100949
950 macb = malloc(sizeof(struct macb_device));
951 if (!macb) {
952 printf("Error: Failed to allocate memory for MACB%d\n", id);
953 return -1;
954 }
955 memset(macb, 0, sizeof(struct macb_device));
956
957 netdev = &macb->netdev;
958
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100959 macb->regs = regs;
960 macb->phy_addr = phy_addr;
961
Bo Shen6f7d7d92013-04-24 15:59:28 +0800962 if (macb_is_gem(macb))
963 sprintf(netdev->name, "gmac%d", id);
964 else
965 sprintf(netdev->name, "macb%d", id);
966
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100967 netdev->init = macb_init;
968 netdev->halt = macb_halt;
969 netdev->send = macb_send;
970 netdev->recv = macb_recv;
Ben Warren33f84312010-06-01 11:55:42 -0700971 netdev->write_hwaddr = macb_write_hwaddr;
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100972
Simon Glass5ad27512016-05-05 07:28:09 -0600973 _macb_eth_initialize(macb);
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100974
975 eth_register(netdev);
976
Bo Shen7d91deb2013-04-24 15:59:27 +0800977#if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
Joe Hershberger1fbcbed2016-08-08 11:28:38 -0500978 int retval;
979 struct mii_dev *mdiodev = mdio_alloc();
980 if (!mdiodev)
981 return -ENOMEM;
982 strncpy(mdiodev->name, netdev->name, MDIO_NAME_LEN);
983 mdiodev->read = macb_miiphy_read;
984 mdiodev->write = macb_miiphy_write;
985
986 retval = mdio_register(mdiodev);
987 if (retval < 0)
988 return retval;
Bo Shen7d91deb2013-04-24 15:59:27 +0800989 macb->bus = miiphy_get_dev_by_name(netdev->name);
Semih Hazar790088e2009-12-17 15:07:15 +0200990#endif
Simon Glass75c5d182016-05-05 07:28:11 -0600991 return 0;
992}
993#endif /* !CONFIG_DM_ETH */
994
995#ifdef CONFIG_DM_ETH
996
997static int macb_start(struct udevice *dev)
998{
Wenyou Yang7b811852016-05-17 13:11:35 +0800999 return _macb_init(dev, dev->name);
Simon Glass75c5d182016-05-05 07:28:11 -06001000}
1001
1002static int macb_send(struct udevice *dev, void *packet, int length)
1003{
1004 struct macb_device *macb = dev_get_priv(dev);
1005
1006 return _macb_send(macb, dev->name, packet, length);
1007}
1008
1009static int macb_recv(struct udevice *dev, int flags, uchar **packetp)
1010{
1011 struct macb_device *macb = dev_get_priv(dev);
1012
1013 macb->next_rx_tail = macb->rx_tail;
1014 macb->wrapped = false;
1015
1016 return _macb_recv(macb, packetp);
1017}
1018
1019static int macb_free_pkt(struct udevice *dev, uchar *packet, int length)
1020{
1021 struct macb_device *macb = dev_get_priv(dev);
1022
1023 reclaim_rx_buffers(macb, macb->next_rx_tail);
1024
1025 return 0;
1026}
1027
1028static void macb_stop(struct udevice *dev)
1029{
1030 struct macb_device *macb = dev_get_priv(dev);
1031
1032 _macb_halt(macb);
1033}
1034
1035static int macb_write_hwaddr(struct udevice *dev)
1036{
1037 struct eth_pdata *plat = dev_get_platdata(dev);
1038 struct macb_device *macb = dev_get_priv(dev);
1039
1040 return _macb_write_hwaddr(macb, plat->enetaddr);
1041}
1042
1043static const struct eth_ops macb_eth_ops = {
1044 .start = macb_start,
1045 .send = macb_send,
1046 .recv = macb_recv,
1047 .stop = macb_stop,
1048 .free_pkt = macb_free_pkt,
1049 .write_hwaddr = macb_write_hwaddr,
1050};
1051
Wenyou Yang19449362017-02-14 16:24:40 +08001052#ifdef CONFIG_CLK
Wenyou Yang3d8d3482016-11-02 10:06:56 +08001053static int macb_enable_clk(struct udevice *dev)
1054{
1055 struct macb_device *macb = dev_get_priv(dev);
1056 struct clk clk;
1057 ulong clk_rate;
1058 int ret;
1059
1060 ret = clk_get_by_index(dev, 0, &clk);
1061 if (ret)
1062 return -EINVAL;
1063
Wilson Lee41d6d1e2017-08-22 20:25:07 -07001064 /*
1065 * Zynq clock driver didn't support for enable or disable
1066 * clock. Hence, clk_enable() didn't apply for Zynq
1067 */
1068#ifndef CONFIG_MACB_ZYNQ
Wenyou Yang3d8d3482016-11-02 10:06:56 +08001069 ret = clk_enable(&clk);
1070 if (ret)
1071 return ret;
Wilson Lee41d6d1e2017-08-22 20:25:07 -07001072#endif
Wenyou Yang3d8d3482016-11-02 10:06:56 +08001073
1074 clk_rate = clk_get_rate(&clk);
1075 if (!clk_rate)
1076 return -EINVAL;
1077
1078 macb->pclk_rate = clk_rate;
1079
1080 return 0;
1081}
Wenyou Yang19449362017-02-14 16:24:40 +08001082#endif
Wenyou Yang3d8d3482016-11-02 10:06:56 +08001083
Simon Glass75c5d182016-05-05 07:28:11 -06001084static int macb_eth_probe(struct udevice *dev)
1085{
1086 struct eth_pdata *pdata = dev_get_platdata(dev);
1087 struct macb_device *macb = dev_get_priv(dev);
Wenyou Yang7b811852016-05-17 13:11:35 +08001088 const char *phy_mode;
Wenyou Yang44835ea2017-04-14 14:36:04 +08001089 __maybe_unused int ret;
Wenyou Yang7b811852016-05-17 13:11:35 +08001090
Simon Glassdd79d6e2017-01-17 16:52:55 -07001091 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
1092 NULL);
Wenyou Yang7b811852016-05-17 13:11:35 +08001093 if (phy_mode)
1094 macb->phy_interface = phy_get_interface_by_name(phy_mode);
1095 if (macb->phy_interface == -1) {
1096 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
1097 return -EINVAL;
1098 }
Wenyou Yang7b811852016-05-17 13:11:35 +08001099
Simon Glass75c5d182016-05-05 07:28:11 -06001100 macb->regs = (void *)pdata->iobase;
1101
Wenyou Yang19449362017-02-14 16:24:40 +08001102#ifdef CONFIG_CLK
Wenyou Yang44835ea2017-04-14 14:36:04 +08001103 ret = macb_enable_clk(dev);
Wenyou Yang3d8d3482016-11-02 10:06:56 +08001104 if (ret)
1105 return ret;
Wenyou Yang19449362017-02-14 16:24:40 +08001106#endif
Wenyou Yang3d8d3482016-11-02 10:06:56 +08001107
Simon Glass75c5d182016-05-05 07:28:11 -06001108 _macb_eth_initialize(macb);
Wenyou Yang3d8d3482016-11-02 10:06:56 +08001109
Simon Glass75c5d182016-05-05 07:28:11 -06001110#if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
Wenyou Yang44835ea2017-04-14 14:36:04 +08001111 macb->bus = mdio_alloc();
1112 if (!macb->bus)
Joe Hershberger1fbcbed2016-08-08 11:28:38 -05001113 return -ENOMEM;
Wenyou Yang44835ea2017-04-14 14:36:04 +08001114 strncpy(macb->bus->name, dev->name, MDIO_NAME_LEN);
1115 macb->bus->read = macb_miiphy_read;
1116 macb->bus->write = macb_miiphy_write;
Joe Hershberger1fbcbed2016-08-08 11:28:38 -05001117
Wenyou Yang44835ea2017-04-14 14:36:04 +08001118 ret = mdio_register(macb->bus);
1119 if (ret < 0)
1120 return ret;
Simon Glass75c5d182016-05-05 07:28:11 -06001121 macb->bus = miiphy_get_dev_by_name(dev->name);
1122#endif
Wenyou Yang44835ea2017-04-14 14:36:04 +08001123
1124 return 0;
1125}
1126
1127static int macb_eth_remove(struct udevice *dev)
1128{
1129 struct macb_device *macb = dev_get_priv(dev);
1130
1131#ifdef CONFIG_PHYLIB
1132 free(macb->phydev);
1133#endif
1134 mdio_unregister(macb->bus);
1135 mdio_free(macb->bus);
Simon Glass75c5d182016-05-05 07:28:11 -06001136
Wilson Lee41d6d1e2017-08-22 20:25:07 -07001137 return 0;
1138}
1139
1140/**
1141 * macb_late_eth_ofdata_to_platdata
1142 * @dev: udevice struct
1143 * Returns 0 when operation success and negative errno number
1144 * when operation failed.
1145 */
1146int __weak macb_late_eth_ofdata_to_platdata(struct udevice *dev)
1147{
Simon Glass75c5d182016-05-05 07:28:11 -06001148 return 0;
1149}
1150
1151static int macb_eth_ofdata_to_platdata(struct udevice *dev)
1152{
1153 struct eth_pdata *pdata = dev_get_platdata(dev);
1154
Simon Glassba1dea42017-05-17 17:18:05 -06001155 pdata->iobase = devfdt_get_addr(dev);
Wilson Lee41d6d1e2017-08-22 20:25:07 -07001156
1157 return macb_late_eth_ofdata_to_platdata(dev);
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +01001158}
1159
Simon Glass75c5d182016-05-05 07:28:11 -06001160static const struct udevice_id macb_eth_ids[] = {
1161 { .compatible = "cdns,macb" },
Wenyou Yang8f155402017-04-14 14:36:05 +08001162 { .compatible = "cdns,at91sam9260-macb" },
1163 { .compatible = "atmel,sama5d2-gem" },
1164 { .compatible = "atmel,sama5d3-gem" },
1165 { .compatible = "atmel,sama5d4-gem" },
Wilson Lee41d6d1e2017-08-22 20:25:07 -07001166 { .compatible = "cdns,zynq-gem" },
Simon Glass75c5d182016-05-05 07:28:11 -06001167 { }
1168};
1169
1170U_BOOT_DRIVER(eth_macb) = {
1171 .name = "eth_macb",
1172 .id = UCLASS_ETH,
1173 .of_match = macb_eth_ids,
1174 .ofdata_to_platdata = macb_eth_ofdata_to_platdata,
1175 .probe = macb_eth_probe,
Wenyou Yang44835ea2017-04-14 14:36:04 +08001176 .remove = macb_eth_remove,
Simon Glass75c5d182016-05-05 07:28:11 -06001177 .ops = &macb_eth_ops,
1178 .priv_auto_alloc_size = sizeof(struct macb_device),
1179 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1180};
1181#endif
1182
Jon Loeligerb1d408a2007-07-09 17:30:01 -05001183#endif