blob: 43bb8781171903f0f69fb6f51a560e2a66ec6ee7 [file] [log] [blame]
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +01001/*
2 * Copyright (C) 2005-2006 Atmel Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18#include <common.h>
19
20#if defined(CONFIG_MACB) && (CONFIG_COMMANDS & (CFG_CMD_NET | CFG_CMD_MII))
21
22/*
23 * The u-boot networking stack is a little weird. It seems like the
24 * networking core allocates receive buffers up front without any
25 * regard to the hardware that's supposed to actually receive those
26 * packets.
27 *
28 * The MACB receives packets into 128-byte receive buffers, so the
29 * buffers allocated by the core isn't very practical to use. We'll
30 * allocate our own, but we need one such buffer in case a packet
31 * wraps around the DMA ring so that we have to copy it.
32 *
33 * Therefore, define CFG_RX_ETH_BUFFER to 1 in the board-specific
34 * configuration header. This way, the core allocates one RX buffer
35 * and one TX buffer, each of which can hold a ethernet packet of
36 * maximum size.
37 *
38 * For some reason, the networking core unconditionally specifies a
39 * 32-byte packet "alignment" (which really should be called
40 * "padding"). MACB shouldn't need that, but we'll refrain from any
41 * core modifications here...
42 */
43
44#include <net.h>
45#include <malloc.h>
46
47#include <linux/mii.h>
48#include <asm/io.h>
49#include <asm/dma-mapping.h>
50#include <asm/arch/clk.h>
51
52#include "macb.h"
53
Haavard Skinnemoen996e1472007-05-02 13:22:38 +020054#define barrier() asm volatile("" ::: "memory")
55
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +010056#define CFG_MACB_RX_BUFFER_SIZE 4096
57#define CFG_MACB_RX_RING_SIZE (CFG_MACB_RX_BUFFER_SIZE / 128)
58#define CFG_MACB_TX_RING_SIZE 16
59#define CFG_MACB_TX_TIMEOUT 1000
60#define CFG_MACB_AUTONEG_TIMEOUT 5000000
61
62struct macb_dma_desc {
63 u32 addr;
64 u32 ctrl;
65};
66
67#define RXADDR_USED 0x00000001
68#define RXADDR_WRAP 0x00000002
69
70#define RXBUF_FRMLEN_MASK 0x00000fff
71#define RXBUF_FRAME_START 0x00004000
72#define RXBUF_FRAME_END 0x00008000
73#define RXBUF_TYPEID_MATCH 0x00400000
74#define RXBUF_ADDR4_MATCH 0x00800000
75#define RXBUF_ADDR3_MATCH 0x01000000
76#define RXBUF_ADDR2_MATCH 0x02000000
77#define RXBUF_ADDR1_MATCH 0x04000000
78#define RXBUF_BROADCAST 0x80000000
79
80#define TXBUF_FRMLEN_MASK 0x000007ff
81#define TXBUF_FRAME_END 0x00008000
82#define TXBUF_NOCRC 0x00010000
83#define TXBUF_EXHAUSTED 0x08000000
84#define TXBUF_UNDERRUN 0x10000000
85#define TXBUF_MAXRETRY 0x20000000
86#define TXBUF_WRAP 0x40000000
87#define TXBUF_USED 0x80000000
88
89struct macb_device {
90 void *regs;
91
92 unsigned int rx_tail;
93 unsigned int tx_head;
94 unsigned int tx_tail;
95
96 void *rx_buffer;
97 void *tx_buffer;
98 struct macb_dma_desc *rx_ring;
99 struct macb_dma_desc *tx_ring;
100
101 unsigned long rx_buffer_dma;
102 unsigned long rx_ring_dma;
103 unsigned long tx_ring_dma;
104
105 const struct device *dev;
106 struct eth_device netdev;
107 unsigned short phy_addr;
108};
109#define to_macb(_nd) container_of(_nd, struct macb_device, netdev)
110
111static void macb_mdio_write(struct macb_device *macb, u8 reg, u16 value)
112{
113 unsigned long netctl;
114 unsigned long netstat;
115 unsigned long frame;
116
117 netctl = macb_readl(macb, NCR);
118 netctl |= MACB_BIT(MPE);
119 macb_writel(macb, NCR, netctl);
120
121 frame = (MACB_BF(SOF, 1)
122 | MACB_BF(RW, 1)
123 | MACB_BF(PHYA, macb->phy_addr)
124 | MACB_BF(REGA, reg)
125 | MACB_BF(CODE, 2)
126 | MACB_BF(DATA, value));
127 macb_writel(macb, MAN, frame);
128
129 do {
130 netstat = macb_readl(macb, NSR);
131 } while (!(netstat & MACB_BIT(IDLE)));
132
133 netctl = macb_readl(macb, NCR);
134 netctl &= ~MACB_BIT(MPE);
135 macb_writel(macb, NCR, netctl);
136}
137
138static u16 macb_mdio_read(struct macb_device *macb, u8 reg)
139{
140 unsigned long netctl;
141 unsigned long netstat;
142 unsigned long frame;
143
144 netctl = macb_readl(macb, NCR);
145 netctl |= MACB_BIT(MPE);
146 macb_writel(macb, NCR, netctl);
147
148 frame = (MACB_BF(SOF, 1)
149 | MACB_BF(RW, 2)
150 | MACB_BF(PHYA, macb->phy_addr)
151 | MACB_BF(REGA, reg)
152 | MACB_BF(CODE, 2));
153 macb_writel(macb, MAN, frame);
154
155 do {
156 netstat = macb_readl(macb, NSR);
157 } while (!(netstat & MACB_BIT(IDLE)));
158
159 frame = macb_readl(macb, MAN);
160
161 netctl = macb_readl(macb, NCR);
162 netctl &= ~MACB_BIT(MPE);
163 macb_writel(macb, NCR, netctl);
164
165 return MACB_BFEXT(DATA, frame);
166}
167
168#if (CONFIG_COMMANDS & CFG_CMD_NET)
169
170static int macb_send(struct eth_device *netdev, volatile void *packet,
171 int length)
172{
173 struct macb_device *macb = to_macb(netdev);
174 unsigned long paddr, ctrl;
175 unsigned int tx_head = macb->tx_head;
176 int i;
177
178 paddr = dma_map_single(packet, length, DMA_TO_DEVICE);
179
180 ctrl = length & TXBUF_FRMLEN_MASK;
181 ctrl |= TXBUF_FRAME_END;
182 if (tx_head == (CFG_MACB_TX_RING_SIZE - 1)) {
183 ctrl |= TXBUF_WRAP;
184 macb->tx_head = 0;
185 } else
186 macb->tx_head++;
187
188 macb->tx_ring[tx_head].ctrl = ctrl;
189 macb->tx_ring[tx_head].addr = paddr;
Haavard Skinnemoen996e1472007-05-02 13:22:38 +0200190 barrier();
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100191 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
192
193 /*
194 * I guess this is necessary because the networking core may
195 * re-use the transmit buffer as soon as we return...
196 */
Haavard Skinnemoen996e1472007-05-02 13:22:38 +0200197 for (i = 0; i <= CFG_MACB_TX_TIMEOUT; i++) {
198 barrier();
199 ctrl = macb->tx_ring[tx_head].ctrl;
200 if (ctrl & TXBUF_USED)
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100201 break;
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100202 udelay(1);
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100203 }
204
205 dma_unmap_single(packet, length, paddr);
206
207 if (i <= CFG_MACB_TX_TIMEOUT) {
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100208 if (ctrl & TXBUF_UNDERRUN)
209 printf("%s: TX underrun\n", netdev->name);
210 if (ctrl & TXBUF_EXHAUSTED)
211 printf("%s: TX buffers exhausted in mid frame\n",
212 netdev->name);
Haavard Skinnemoen996e1472007-05-02 13:22:38 +0200213 } else {
214 printf("%s: TX timeout\n", netdev->name);
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100215 }
216
217 /* No one cares anyway */
218 return 0;
219}
220
221static void reclaim_rx_buffers(struct macb_device *macb,
222 unsigned int new_tail)
223{
224 unsigned int i;
225
226 i = macb->rx_tail;
227 while (i > new_tail) {
228 macb->rx_ring[i].addr &= ~RXADDR_USED;
229 i++;
230 if (i > CFG_MACB_RX_RING_SIZE)
231 i = 0;
232 }
233
234 while (i < new_tail) {
235 macb->rx_ring[i].addr &= ~RXADDR_USED;
236 i++;
237 }
238
Haavard Skinnemoen996e1472007-05-02 13:22:38 +0200239 barrier();
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100240 macb->rx_tail = new_tail;
241}
242
243static int macb_recv(struct eth_device *netdev)
244{
245 struct macb_device *macb = to_macb(netdev);
246 unsigned int rx_tail = macb->rx_tail;
247 void *buffer;
248 int length;
249 int wrapped = 0;
250 u32 status;
251
252 for (;;) {
253 if (!(macb->rx_ring[rx_tail].addr & RXADDR_USED))
254 return -1;
255
256 status = macb->rx_ring[rx_tail].ctrl;
257 if (status & RXBUF_FRAME_START) {
258 if (rx_tail != macb->rx_tail)
259 reclaim_rx_buffers(macb, rx_tail);
260 wrapped = 0;
261 }
262
263 if (status & RXBUF_FRAME_END) {
264 buffer = macb->rx_buffer + 128 * macb->rx_tail;
265 length = status & RXBUF_FRMLEN_MASK;
266 if (wrapped) {
267 unsigned int headlen, taillen;
268
269 headlen = 128 * (CFG_MACB_RX_RING_SIZE
270 - macb->rx_tail);
271 taillen = length - headlen;
272 memcpy((void *)NetRxPackets[0],
273 buffer, headlen);
274 memcpy((void *)NetRxPackets[0] + headlen,
275 macb->rx_buffer, taillen);
276 buffer = (void *)NetRxPackets[0];
277 }
278
279 NetReceive(buffer, length);
280 if (++rx_tail >= CFG_MACB_RX_RING_SIZE)
281 rx_tail = 0;
282 reclaim_rx_buffers(macb, rx_tail);
283 } else {
284 if (++rx_tail >= CFG_MACB_RX_RING_SIZE) {
285 wrapped = 1;
286 rx_tail = 0;
287 }
288 }
Haavard Skinnemoen996e1472007-05-02 13:22:38 +0200289 barrier();
Haavard Skinnemoen51c8f242006-01-20 10:03:34 +0100290 }
291
292 return 0;
293}
294
295static int macb_phy_init(struct macb_device *macb)
296{
297 struct eth_device *netdev = &macb->netdev;
298 u32 ncfgr;
299 u16 phy_id, status, adv, lpa;
300 int media, speed, duplex;
301 int i;
302
303 /* Check if the PHY is up to snuff... */
304 phy_id = macb_mdio_read(macb, MII_PHYSID1);
305 if (phy_id == 0xffff) {
306 printf("%s: No PHY present\n", netdev->name);
307 return 0;
308 }
309
310 adv = ADVERTISE_CSMA | ADVERTISE_ALL;
311 macb_mdio_write(macb, MII_ADVERTISE, adv);
312 printf("%s: Starting autonegotiation...\n", netdev->name);
313 macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE
314 | BMCR_ANRESTART));
315
316#if 0
317 for (i = 0; i < 9; i++)
318 printf("mii%d: 0x%04x\n", i, macb_mdio_read(macb, i));
319#endif
320
321 for (i = 0; i < CFG_MACB_AUTONEG_TIMEOUT / 100; i++) {
322 status = macb_mdio_read(macb, MII_BMSR);
323 if (status & BMSR_ANEGCOMPLETE)
324 break;
325 udelay(100);
326 }
327
328 if (status & BMSR_ANEGCOMPLETE)
329 printf("%s: Autonegotiation complete\n", netdev->name);
330 else
331 printf("%s: Autonegotiation timed out (status=0x%04x)\n",
332 netdev->name, status);
333
334 if (!(status & BMSR_LSTATUS)) {
335 for (i = 0; i < CFG_MACB_AUTONEG_TIMEOUT / 100; i++) {
336 udelay(100);
337 status = macb_mdio_read(macb, MII_BMSR);
338 if (status & BMSR_LSTATUS)
339 break;
340 }
341 }
342
343 if (!(status & BMSR_LSTATUS)) {
344 printf("%s: link down (status: 0x%04x)\n",
345 netdev->name, status);
346 return 0;
347 } else {
348 lpa = macb_mdio_read(macb, MII_LPA);
349 media = mii_nway_result(lpa & adv);
350 speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
351 ? 1 : 0);
352 duplex = (media & ADVERTISE_FULL) ? 1 : 0;
353 printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n",
354 netdev->name,
355 speed ? "100" : "10",
356 duplex ? "full" : "half",
357 lpa);
358
359 ncfgr = macb_readl(macb, NCFGR);
360 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
361 if (speed)
362 ncfgr |= MACB_BIT(SPD);
363 if (duplex)
364 ncfgr |= MACB_BIT(FD);
365 macb_writel(macb, NCFGR, ncfgr);
366 return 1;
367 }
368}
369
370static int macb_init(struct eth_device *netdev, bd_t *bd)
371{
372 struct macb_device *macb = to_macb(netdev);
373 unsigned long paddr;
374 u32 hwaddr_bottom;
375 u16 hwaddr_top;
376 int i;
377
378 /*
379 * macb_halt should have been called at some point before now,
380 * so we'll assume the controller is idle.
381 */
382
383 /* initialize DMA descriptors */
384 paddr = macb->rx_buffer_dma;
385 for (i = 0; i < CFG_MACB_RX_RING_SIZE; i++) {
386 if (i == (CFG_MACB_RX_RING_SIZE - 1))
387 paddr |= RXADDR_WRAP;
388 macb->rx_ring[i].addr = paddr;
389 macb->rx_ring[i].ctrl = 0;
390 paddr += 128;
391 }
392 for (i = 0; i < CFG_MACB_TX_RING_SIZE; i++) {
393 macb->tx_ring[i].addr = 0;
394 if (i == (CFG_MACB_TX_RING_SIZE - 1))
395 macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP;
396 else
397 macb->tx_ring[i].ctrl = TXBUF_USED;
398 }
399 macb->rx_tail = macb->tx_head = macb->tx_tail = 0;
400
401 macb_writel(macb, RBQP, macb->rx_ring_dma);
402 macb_writel(macb, TBQP, macb->tx_ring_dma);
403
404 /* set hardware address */
405 hwaddr_bottom = cpu_to_le32(*((u32 *)netdev->enetaddr));
406 macb_writel(macb, SA1B, hwaddr_bottom);
407 hwaddr_top = cpu_to_le16(*((u16 *)(netdev->enetaddr + 4)));
408 macb_writel(macb, SA1T, hwaddr_top);
409
410 /* choose RMII or MII mode. This depends on the board */
411#ifdef CONFIG_RMII
412 macb_writel(macb, USRIO, 0);
413#else
414 macb_writel(macb, USRIO, MACB_BIT(MII));
415#endif
416
417 if (!macb_phy_init(macb))
418 return 0;
419
420 /* Enable TX and RX */
421 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE));
422
423 return 1;
424}
425
426static void macb_halt(struct eth_device *netdev)
427{
428 struct macb_device *macb = to_macb(netdev);
429 u32 ncr, tsr;
430
431 /* Halt the controller and wait for any ongoing transmission to end. */
432 ncr = macb_readl(macb, NCR);
433 ncr |= MACB_BIT(THALT);
434 macb_writel(macb, NCR, ncr);
435
436 do {
437 tsr = macb_readl(macb, TSR);
438 } while (tsr & MACB_BIT(TGO));
439
440 /* Disable TX and RX, and clear statistics */
441 macb_writel(macb, NCR, MACB_BIT(CLRSTAT));
442}
443
444int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
445{
446 struct macb_device *macb;
447 struct eth_device *netdev;
448 unsigned long macb_hz;
449 u32 ncfgr;
450
451 macb = malloc(sizeof(struct macb_device));
452 if (!macb) {
453 printf("Error: Failed to allocate memory for MACB%d\n", id);
454 return -1;
455 }
456 memset(macb, 0, sizeof(struct macb_device));
457
458 netdev = &macb->netdev;
459
460 macb->rx_buffer = dma_alloc_coherent(CFG_MACB_RX_BUFFER_SIZE,
461 &macb->rx_buffer_dma);
462 macb->rx_ring = dma_alloc_coherent(CFG_MACB_RX_RING_SIZE
463 * sizeof(struct macb_dma_desc),
464 &macb->rx_ring_dma);
465 macb->tx_ring = dma_alloc_coherent(CFG_MACB_TX_RING_SIZE
466 * sizeof(struct macb_dma_desc),
467 &macb->tx_ring_dma);
468
469 macb->regs = regs;
470 macb->phy_addr = phy_addr;
471
472 sprintf(netdev->name, "macb%d", id);
473 netdev->init = macb_init;
474 netdev->halt = macb_halt;
475 netdev->send = macb_send;
476 netdev->recv = macb_recv;
477
478 /*
479 * Do some basic initialization so that we at least can talk
480 * to the PHY
481 */
482 macb_hz = get_macb_pclk_rate(id);
483 if (macb_hz < 20000000)
484 ncfgr = MACB_BF(CLK, MACB_CLK_DIV8);
485 else if (macb_hz < 40000000)
486 ncfgr = MACB_BF(CLK, MACB_CLK_DIV16);
487 else if (macb_hz < 80000000)
488 ncfgr = MACB_BF(CLK, MACB_CLK_DIV32);
489 else
490 ncfgr = MACB_BF(CLK, MACB_CLK_DIV64);
491
492 macb_writel(macb, NCFGR, ncfgr);
493
494 eth_register(netdev);
495
496 return 0;
497}
498
499#endif /* (CONFIG_COMMANDS & CFG_CMD_NET) */
500
501#if (CONFIG_COMMANDS & CFG_CMD_MII)
502
503int miiphy_read(unsigned char addr, unsigned char reg, unsigned short *value)
504{
505 unsigned long netctl;
506 unsigned long netstat;
507 unsigned long frame;
508 int iflag;
509
510 iflag = disable_interrupts();
511 netctl = macb_readl(&macb, EMACB_NCR);
512 netctl |= MACB_BIT(MPE);
513 macb_writel(&macb, EMACB_NCR, netctl);
514 if (iflag)
515 enable_interrupts();
516
517 frame = (MACB_BF(SOF, 1)
518 | MACB_BF(RW, 2)
519 | MACB_BF(PHYA, addr)
520 | MACB_BF(REGA, reg)
521 | MACB_BF(CODE, 2));
522 macb_writel(&macb, EMACB_MAN, frame);
523
524 do {
525 netstat = macb_readl(&macb, EMACB_NSR);
526 } while (!(netstat & MACB_BIT(IDLE)));
527
528 frame = macb_readl(&macb, EMACB_MAN);
529 *value = MACB_BFEXT(DATA, frame);
530
531 iflag = disable_interrupts();
532 netctl = macb_readl(&macb, EMACB_NCR);
533 netctl &= ~MACB_BIT(MPE);
534 macb_writel(&macb, EMACB_NCR, netctl);
535 if (iflag)
536 enable_interrupts();
537
538 return 0;
539}
540
541int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value)
542{
543 unsigned long netctl;
544 unsigned long netstat;
545 unsigned long frame;
546 int iflag;
547
548 iflag = disable_interrupts();
549 netctl = macb_readl(&macb, EMACB_NCR);
550 netctl |= MACB_BIT(MPE);
551 macb_writel(&macb, EMACB_NCR, netctl);
552 if (iflag)
553 enable_interrupts();
554
555 frame = (MACB_BF(SOF, 1)
556 | MACB_BF(RW, 1)
557 | MACB_BF(PHYA, addr)
558 | MACB_BF(REGA, reg)
559 | MACB_BF(CODE, 2)
560 | MACB_BF(DATA, value));
561 macb_writel(&macb, EMACB_MAN, frame);
562
563 do {
564 netstat = macb_readl(&macb, EMACB_NSR);
565 } while (!(netstat & MACB_BIT(IDLE)));
566
567 iflag = disable_interrupts();
568 netctl = macb_readl(&macb, EMACB_NCR);
569 netctl &= ~MACB_BIT(MPE);
570 macb_writel(&macb, EMACB_NCR, netctl);
571 if (iflag)
572 enable_interrupts();
573
574 return 0;
575}
576
577#endif /* (CONFIG_COMMANDS & CFG_CMD_MII) */
578
579#endif /* CONFIG_MACB */