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git01.mediatek.com / filogic / uboot / debdf8abb1e3df4246221543dd79469a82121c1e / . / arch / arm / include / asm / arch-tegra124 / pinmux.h
blob: 3aba17d21e495ddf31cb36114a2ffa6cc7b534e7 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Tom Warrenb7ea6d12014-01-24 12:46:13 -0700[diff] [blame]2/*
Stephen Warren6685f042014-03-21 12:29:01 -0600[diff] [blame]3 * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
Tom Warrenb7ea6d12014-01-24 12:46:13 -0700[diff] [blame]4 */
5
6#ifndef _TEGRA124_PINMUX_H_
7#define _TEGRA124_PINMUX_H_
8
Tom Warrenb7ea6d12014-01-24 12:46:13 -0700[diff] [blame]9enum pmux_pingrp {
Stephen Warren6685f042014-03-21 12:29:01 -0600[diff] [blame]10 PMUX_PINGRP_ULPI_DATA0_PO1,
11 PMUX_PINGRP_ULPI_DATA1_PO2,
12 PMUX_PINGRP_ULPI_DATA2_PO3,
13 PMUX_PINGRP_ULPI_DATA3_PO4,
14 PMUX_PINGRP_ULPI_DATA4_PO5,
15 PMUX_PINGRP_ULPI_DATA5_PO6,
16 PMUX_PINGRP_ULPI_DATA6_PO7,
17 PMUX_PINGRP_ULPI_DATA7_PO0,
18 PMUX_PINGRP_ULPI_CLK_PY0,
19 PMUX_PINGRP_ULPI_DIR_PY1,
20 PMUX_PINGRP_ULPI_NXT_PY2,
21 PMUX_PINGRP_ULPI_STP_PY3,
22 PMUX_PINGRP_DAP3_FS_PP0,
23 PMUX_PINGRP_DAP3_DIN_PP1,
24 PMUX_PINGRP_DAP3_DOUT_PP2,
25 PMUX_PINGRP_DAP3_SCLK_PP3,
26 PMUX_PINGRP_PV0,
27 PMUX_PINGRP_PV1,
28 PMUX_PINGRP_SDMMC1_CLK_PZ0,
29 PMUX_PINGRP_SDMMC1_CMD_PZ1,
30 PMUX_PINGRP_SDMMC1_DAT3_PY4,
31 PMUX_PINGRP_SDMMC1_DAT2_PY5,
32 PMUX_PINGRP_SDMMC1_DAT1_PY6,
33 PMUX_PINGRP_SDMMC1_DAT0_PY7,
34 PMUX_PINGRP_CLK2_OUT_PW5 = (0x68 / 4),
35 PMUX_PINGRP_CLK2_REQ_PCC5,
36 PMUX_PINGRP_HDMI_INT_PN7 = (0x110 / 4),
37 PMUX_PINGRP_DDC_SCL_PV4,
38 PMUX_PINGRP_DDC_SDA_PV5,
39 PMUX_PINGRP_UART2_RXD_PC3 = (0x164 / 4),
40 PMUX_PINGRP_UART2_TXD_PC2,
41 PMUX_PINGRP_UART2_RTS_N_PJ6,
42 PMUX_PINGRP_UART2_CTS_N_PJ5,
43 PMUX_PINGRP_UART3_TXD_PW6,
44 PMUX_PINGRP_UART3_RXD_PW7,
45 PMUX_PINGRP_UART3_CTS_N_PA1,
46 PMUX_PINGRP_UART3_RTS_N_PC0,
47 PMUX_PINGRP_PU0,
48 PMUX_PINGRP_PU1,
49 PMUX_PINGRP_PU2,
50 PMUX_PINGRP_PU3,
51 PMUX_PINGRP_PU4,
52 PMUX_PINGRP_PU5,
53 PMUX_PINGRP_PU6,
54 PMUX_PINGRP_GEN1_I2C_SDA_PC5,
55 PMUX_PINGRP_GEN1_I2C_SCL_PC4,
56 PMUX_PINGRP_DAP4_FS_PP4,
57 PMUX_PINGRP_DAP4_DIN_PP5,
58 PMUX_PINGRP_DAP4_DOUT_PP6,
59 PMUX_PINGRP_DAP4_SCLK_PP7,
60 PMUX_PINGRP_CLK3_OUT_PEE0,
61 PMUX_PINGRP_CLK3_REQ_PEE1,
62 PMUX_PINGRP_PC7,
63 PMUX_PINGRP_PI5,
64 PMUX_PINGRP_PI7,
65 PMUX_PINGRP_PK0,
66 PMUX_PINGRP_PK1,
67 PMUX_PINGRP_PJ0,
68 PMUX_PINGRP_PJ2,
69 PMUX_PINGRP_PK3,
70 PMUX_PINGRP_PK4,
71 PMUX_PINGRP_PK2,
72 PMUX_PINGRP_PI3,
73 PMUX_PINGRP_PI6,
74 PMUX_PINGRP_PG0,
75 PMUX_PINGRP_PG1,
76 PMUX_PINGRP_PG2,
77 PMUX_PINGRP_PG3,
78 PMUX_PINGRP_PG4,
79 PMUX_PINGRP_PG5,
80 PMUX_PINGRP_PG6,
81 PMUX_PINGRP_PG7,
82 PMUX_PINGRP_PH0,
83 PMUX_PINGRP_PH1,
84 PMUX_PINGRP_PH2,
85 PMUX_PINGRP_PH3,
86 PMUX_PINGRP_PH4,
87 PMUX_PINGRP_PH5,
88 PMUX_PINGRP_PH6,
89 PMUX_PINGRP_PH7,
90 PMUX_PINGRP_PJ7,
91 PMUX_PINGRP_PB0,
92 PMUX_PINGRP_PB1,
93 PMUX_PINGRP_PK7,
94 PMUX_PINGRP_PI0,
95 PMUX_PINGRP_PI1,
96 PMUX_PINGRP_PI2,
97 PMUX_PINGRP_PI4,
98 PMUX_PINGRP_GEN2_I2C_SCL_PT5,
99 PMUX_PINGRP_GEN2_I2C_SDA_PT6,
100 PMUX_PINGRP_SDMMC4_CLK_PCC4,
101 PMUX_PINGRP_SDMMC4_CMD_PT7,
102 PMUX_PINGRP_SDMMC4_DAT0_PAA0,
103 PMUX_PINGRP_SDMMC4_DAT1_PAA1,
104 PMUX_PINGRP_SDMMC4_DAT2_PAA2,
105 PMUX_PINGRP_SDMMC4_DAT3_PAA3,
106 PMUX_PINGRP_SDMMC4_DAT4_PAA4,
107 PMUX_PINGRP_SDMMC4_DAT5_PAA5,
108 PMUX_PINGRP_SDMMC4_DAT6_PAA6,
109 PMUX_PINGRP_SDMMC4_DAT7_PAA7,
110 PMUX_PINGRP_CAM_MCLK_PCC0 = (0x284 / 4),
111 PMUX_PINGRP_PCC1,
112 PMUX_PINGRP_PBB0,
113 PMUX_PINGRP_CAM_I2C_SCL_PBB1,
114 PMUX_PINGRP_CAM_I2C_SDA_PBB2,
115 PMUX_PINGRP_PBB3,
116 PMUX_PINGRP_PBB4,
117 PMUX_PINGRP_PBB5,
118 PMUX_PINGRP_PBB6,
119 PMUX_PINGRP_PBB7,
120 PMUX_PINGRP_PCC2,
121 PMUX_PINGRP_JTAG_RTCK,
122 PMUX_PINGRP_PWR_I2C_SCL_PZ6,
123 PMUX_PINGRP_PWR_I2C_SDA_PZ7,
124 PMUX_PINGRP_KB_ROW0_PR0,
125 PMUX_PINGRP_KB_ROW1_PR1,
126 PMUX_PINGRP_KB_ROW2_PR2,
127 PMUX_PINGRP_KB_ROW3_PR3,
128 PMUX_PINGRP_KB_ROW4_PR4,
129 PMUX_PINGRP_KB_ROW5_PR5,
130 PMUX_PINGRP_KB_ROW6_PR6,
131 PMUX_PINGRP_KB_ROW7_PR7,
132 PMUX_PINGRP_KB_ROW8_PS0,
133 PMUX_PINGRP_KB_ROW9_PS1,
134 PMUX_PINGRP_KB_ROW10_PS2,
135 PMUX_PINGRP_KB_ROW11_PS3,
136 PMUX_PINGRP_KB_ROW12_PS4,
137 PMUX_PINGRP_KB_ROW13_PS5,
138 PMUX_PINGRP_KB_ROW14_PS6,
139 PMUX_PINGRP_KB_ROW15_PS7,
140 PMUX_PINGRP_KB_COL0_PQ0,
141 PMUX_PINGRP_KB_COL1_PQ1,
142 PMUX_PINGRP_KB_COL2_PQ2,
143 PMUX_PINGRP_KB_COL3_PQ3,
144 PMUX_PINGRP_KB_COL4_PQ4,
145 PMUX_PINGRP_KB_COL5_PQ5,
146 PMUX_PINGRP_KB_COL6_PQ6,
147 PMUX_PINGRP_KB_COL7_PQ7,
148 PMUX_PINGRP_CLK_32K_OUT_PA0,
149 PMUX_PINGRP_CORE_PWR_REQ = (0x324 / 4),
150 PMUX_PINGRP_CPU_PWR_REQ,
151 PMUX_PINGRP_PWR_INT_N,
152 PMUX_PINGRP_CLK_32K_IN,
153 PMUX_PINGRP_OWR,
154 PMUX_PINGRP_DAP1_FS_PN0,
155 PMUX_PINGRP_DAP1_DIN_PN1,
156 PMUX_PINGRP_DAP1_DOUT_PN2,
157 PMUX_PINGRP_DAP1_SCLK_PN3,
158 PMUX_PINGRP_DAP_MCLK1_REQ_PEE2,
159 PMUX_PINGRP_DAP_MCLK1_PW4,
160 PMUX_PINGRP_SPDIF_IN_PK6,
161 PMUX_PINGRP_SPDIF_OUT_PK5,
162 PMUX_PINGRP_DAP2_FS_PA2,
163 PMUX_PINGRP_DAP2_DIN_PA4,
164 PMUX_PINGRP_DAP2_DOUT_PA5,
165 PMUX_PINGRP_DAP2_SCLK_PA3,
166 PMUX_PINGRP_DVFS_PWM_PX0,
167 PMUX_PINGRP_GPIO_X1_AUD_PX1,
168 PMUX_PINGRP_GPIO_X3_AUD_PX3,
169 PMUX_PINGRP_DVFS_CLK_PX2,
170 PMUX_PINGRP_GPIO_X4_AUD_PX4,
171 PMUX_PINGRP_GPIO_X5_AUD_PX5,
172 PMUX_PINGRP_GPIO_X6_AUD_PX6,
173 PMUX_PINGRP_GPIO_X7_AUD_PX7,
174 PMUX_PINGRP_SDMMC3_CLK_PA6 = (0x390 / 4),
175 PMUX_PINGRP_SDMMC3_CMD_PA7,
176 PMUX_PINGRP_SDMMC3_DAT0_PB7,
177 PMUX_PINGRP_SDMMC3_DAT1_PB6,
178 PMUX_PINGRP_SDMMC3_DAT2_PB5,
179 PMUX_PINGRP_SDMMC3_DAT3_PB4,
180 PMUX_PINGRP_PEX_L0_RST_N_PDD1 = (0x3bc / 4),
181 PMUX_PINGRP_PEX_L0_CLKREQ_N_PDD2,
182 PMUX_PINGRP_PEX_WAKE_N_PDD3,
183 PMUX_PINGRP_PEX_L1_RST_N_PDD5 = (0x3cc / 4),
184 PMUX_PINGRP_PEX_L1_CLKREQ_N_PDD6,
185 PMUX_PINGRP_HDMI_CEC_PEE3 = (0x3e0 / 4),
186 PMUX_PINGRP_SDMMC1_WP_N_PV3,
187 PMUX_PINGRP_SDMMC3_CD_N_PV2,
188 PMUX_PINGRP_GPIO_W2_AUD_PW2,
189 PMUX_PINGRP_GPIO_W3_AUD_PW3,
190 PMUX_PINGRP_USB_VBUS_EN0_PN4,
191 PMUX_PINGRP_USB_VBUS_EN1_PN5,
192 PMUX_PINGRP_SDMMC3_CLK_LB_IN_PEE5,
193 PMUX_PINGRP_SDMMC3_CLK_LB_OUT_PEE4,
194 PMUX_PINGRP_GMI_CLK_LB,
195 PMUX_PINGRP_RESET_OUT_N,
196 PMUX_PINGRP_KB_ROW16_PT0,
197 PMUX_PINGRP_KB_ROW17_PT1,
198 PMUX_PINGRP_USB_VBUS_EN2_PFF1,
199 PMUX_PINGRP_PFF2,
200 PMUX_PINGRP_DP_HPD_PFF0 = (0x430 / 4),
Stephen Warrenf4df6052014-03-21 12:28:56 -0600[diff] [blame]201 PMUX_PINGRP_COUNT,
Tom Warrenb7ea6d12014-01-24 12:46:13 -0700[diff] [blame]202};
203
Stephen Warrenf4df6052014-03-21 12:28:56 -0600[diff] [blame]204enum pmux_drvgrp {
Stephen Warren6685f042014-03-21 12:29:01 -0600[diff] [blame]205 PMUX_DRVGRP_AO1,
206 PMUX_DRVGRP_AO2,
207 PMUX_DRVGRP_AT1,
208 PMUX_DRVGRP_AT2,
209 PMUX_DRVGRP_AT3,
210 PMUX_DRVGRP_AT4,
211 PMUX_DRVGRP_AT5,
212 PMUX_DRVGRP_CDEV1,
213 PMUX_DRVGRP_CDEV2,
214 PMUX_DRVGRP_DAP1 = (0x28 / 4),
215 PMUX_DRVGRP_DAP2,
216 PMUX_DRVGRP_DAP3,
217 PMUX_DRVGRP_DAP4,
218 PMUX_DRVGRP_DBG,
219 PMUX_DRVGRP_SDIO3 = (0x48 / 4),
220 PMUX_DRVGRP_SPI,
221 PMUX_DRVGRP_UAA,
222 PMUX_DRVGRP_UAB,
223 PMUX_DRVGRP_UART2,
224 PMUX_DRVGRP_UART3,
225 PMUX_DRVGRP_SDIO1 = (0x84 / 4),
226 PMUX_DRVGRP_DDC = (0x94 / 4),
227 PMUX_DRVGRP_GMA,
228 PMUX_DRVGRP_GME = (0xa8 / 4),
229 PMUX_DRVGRP_GMF,
230 PMUX_DRVGRP_GMG,
231 PMUX_DRVGRP_GMH,
232 PMUX_DRVGRP_OWR,
233 PMUX_DRVGRP_UDA,
234 PMUX_DRVGRP_GPV,
235 PMUX_DRVGRP_DEV3,
236 PMUX_DRVGRP_CEC = (0xd0 / 4),
237 PMUX_DRVGRP_AT6 = (0x12c / 4),
238 PMUX_DRVGRP_DAP5,
239 PMUX_DRVGRP_USB_VBUS_EN,
240 PMUX_DRVGRP_AO3 = (0x140 / 4),
241 PMUX_DRVGRP_AO0 = (0x148 / 4),
242 PMUX_DRVGRP_HV0,
243 PMUX_DRVGRP_SDIO4 = (0x15c / 4),
244 PMUX_DRVGRP_AO4,
Stephen Warrenf4df6052014-03-21 12:28:56 -0600[diff] [blame]245 PMUX_DRVGRP_COUNT,
Tom Warrenb7ea6d12014-01-24 12:46:13 -0700[diff] [blame]246};
247
Stephen Warrend937fb52015-03-25 12:04:37 -0600[diff] [blame]248enum pmux_mipipadctrlgrp {
249 PMUX_MIPIPADCTRLGRP_DSI_B,
250 PMUX_MIPIPADCTRLGRP_COUNT,
251};
252
Tom Warrenb7ea6d12014-01-24 12:46:13 -0700[diff] [blame]253enum pmux_func {
Stephen Warren7d9fae52014-04-22 14:37:52 -0600[diff] [blame]254 PMUX_FUNC_DEFAULT,
Tom Warrenb7ea6d12014-01-24 12:46:13 -0700[diff] [blame]255 PMUX_FUNC_BLINK,
Stephen Warren6685f042014-03-21 12:29:01 -0600[diff] [blame]256 PMUX_FUNC_CCLA,
Tom Warrenb7ea6d12014-01-24 12:46:13 -0700[diff] [blame]257 PMUX_FUNC_CEC,
Stephen Warren6685f042014-03-21 12:29:01 -0600[diff] [blame]258 PMUX_FUNC_CLDVFS,
259 PMUX_FUNC_CLK,
Tom Warrenb7ea6d12014-01-24 12:46:13 -0700[diff] [blame]260 PMUX_FUNC_CLK12,
Stephen Warren6685f042014-03-21 12:29:01 -0600[diff] [blame]261 PMUX_FUNC_CPU,
Stephen Warrend937fb52015-03-25 12:04:37 -0600[diff] [blame]262 PMUX_FUNC_CSI,
Tom Warrenb7ea6d12014-01-24 12:46:13 -0700[diff] [blame]263 PMUX_FUNC_DAP,
Stephen Warren6685f042014-03-21 12:29:01 -0600[diff] [blame]264 PMUX_FUNC_DAP1,
265 PMUX_FUNC_DAP2,
Tom Warrenb7ea6d12014-01-24 12:46:13 -0700[diff] [blame]266 PMUX_FUNC_DEV3,
Stephen Warren6685f042014-03-21 12:29:01 -0600[diff] [blame]267 PMUX_FUNC_DISPLAYA,
268 PMUX_FUNC_DISPLAYA_ALT,
269 PMUX_FUNC_DISPLAYB,
270 PMUX_FUNC_DP,
Stephen Warrend937fb52015-03-25 12:04:37 -0600[diff] [blame]271 PMUX_FUNC_DSI_B,
Tom Warrenb7ea6d12014-01-24 12:46:13 -0700[diff] [blame]272 PMUX_FUNC_DTV,
Tom Warrenb7ea6d12014-01-24 12:46:13 -0700[diff] [blame]273 PMUX_FUNC_EXTPERIPH1,
274 PMUX_FUNC_EXTPERIPH2,
275 PMUX_FUNC_EXTPERIPH3,
Stephen Warren6685f042014-03-21 12:29:01 -0600[diff] [blame]276 PMUX_FUNC_GMI,
Tom Warrenb7ea6d12014-01-24 12:46:13 -0700[diff] [blame]277 PMUX_FUNC_GMI_ALT,
278 PMUX_FUNC_HDA,
279 PMUX_FUNC_HSI,
Stephen Warren6685f042014-03-21 12:29:01 -0600[diff] [blame]280 PMUX_FUNC_I2C1,
281 PMUX_FUNC_I2C2,
282 PMUX_FUNC_I2C3,
Tom Warrenb7ea6d12014-01-24 12:46:13 -0700[diff] [blame]283 PMUX_FUNC_I2C4,
Tom Warrenb7ea6d12014-01-24 12:46:13 -0700[diff] [blame]284 PMUX_FUNC_I2CPWR,
285 PMUX_FUNC_I2S0,
286 PMUX_FUNC_I2S1,
287 PMUX_FUNC_I2S2,
288 PMUX_FUNC_I2S3,
289 PMUX_FUNC_I2S4,
Stephen Warren6685f042014-03-21 12:29:01 -0600[diff] [blame]290 PMUX_FUNC_IRDA,
291 PMUX_FUNC_KBC,
292 PMUX_FUNC_OWR,
293 PMUX_FUNC_PE,
294 PMUX_FUNC_PE0,
295 PMUX_FUNC_PE1,
296 PMUX_FUNC_PMI,
Tom Warrenb7ea6d12014-01-24 12:46:13 -0700[diff] [blame]297 PMUX_FUNC_PWM0,
298 PMUX_FUNC_PWM1,
299 PMUX_FUNC_PWM2,
300 PMUX_FUNC_PWM3,
Stephen Warren6685f042014-03-21 12:29:01 -0600[diff] [blame]301 PMUX_FUNC_PWRON,
302 PMUX_FUNC_RESET_OUT_N,
303 PMUX_FUNC_RTCK,
Tom Warrenb7ea6d12014-01-24 12:46:13 -0700[diff] [blame]304 PMUX_FUNC_SATA,
Stephen Warren6685f042014-03-21 12:29:01 -0600[diff] [blame]305 PMUX_FUNC_SDMMC1,
306 PMUX_FUNC_SDMMC2,
307 PMUX_FUNC_SDMMC3,
308 PMUX_FUNC_SDMMC4,
309 PMUX_FUNC_SOC,
310 PMUX_FUNC_SPDIF,
311 PMUX_FUNC_SPI1,
312 PMUX_FUNC_SPI2,
313 PMUX_FUNC_SPI3,
314 PMUX_FUNC_SPI4,
Tom Warrenb7ea6d12014-01-24 12:46:13 -0700[diff] [blame]315 PMUX_FUNC_SPI5,
316 PMUX_FUNC_SPI6,
Stephen Warren6685f042014-03-21 12:29:01 -0600[diff] [blame]317 PMUX_FUNC_SYS,
318 PMUX_FUNC_TMDS,
319 PMUX_FUNC_TRACE,
320 PMUX_FUNC_UARTA,
321 PMUX_FUNC_UARTB,
322 PMUX_FUNC_UARTC,
323 PMUX_FUNC_UARTD,
324 PMUX_FUNC_ULPI,
325 PMUX_FUNC_USB,
Tom Warrenb7ea6d12014-01-24 12:46:13 -0700[diff] [blame]326 PMUX_FUNC_VGP1,
327 PMUX_FUNC_VGP2,
328 PMUX_FUNC_VGP3,
329 PMUX_FUNC_VGP4,
330 PMUX_FUNC_VGP5,
331 PMUX_FUNC_VGP6,
Stephen Warren6685f042014-03-21 12:29:01 -0600[diff] [blame]332 PMUX_FUNC_VI,
333 PMUX_FUNC_VI_ALT1,
334 PMUX_FUNC_VI_ALT3,
335 PMUX_FUNC_VIMCLK2,
336 PMUX_FUNC_VIMCLK2_ALT,
Stephen Warren70b080f2014-03-21 15:58:03 -0600[diff] [blame]337 PMUX_FUNC_RSVD1,
338 PMUX_FUNC_RSVD2,
339 PMUX_FUNC_RSVD3,
340 PMUX_FUNC_RSVD4,
Stephen Warren9026dfd2014-03-21 12:28:54 -0600[diff] [blame]341 PMUX_FUNC_COUNT,
Tom Warrenb7ea6d12014-01-24 12:46:13 -0700[diff] [blame]342};
343
Svyatoslav Ryhelc53f4c02023-11-26 17:54:03 +0200[diff] [blame]344static const char * const tegra_pinctrl_to_pingrp[] = {
345 [PMUX_PINGRP_ULPI_DATA0_PO1] = "ulpi_data0_po1",
346 [PMUX_PINGRP_ULPI_DATA1_PO2] = "ulpi_data1_po2",
347 [PMUX_PINGRP_ULPI_DATA2_PO3] = "ulpi_data2_po3",
348 [PMUX_PINGRP_ULPI_DATA3_PO4] = "ulpi_data3_po4",
349 [PMUX_PINGRP_ULPI_DATA4_PO5] = "ulpi_data4_po5",
350 [PMUX_PINGRP_ULPI_DATA5_PO6] = "ulpi_data5_po6",
351 [PMUX_PINGRP_ULPI_DATA6_PO7] = "ulpi_data6_po7",
352 [PMUX_PINGRP_ULPI_DATA7_PO0] = "ulpi_data7_po0",
353 [PMUX_PINGRP_ULPI_CLK_PY0] = "ulpi_clk_py0",
354 [PMUX_PINGRP_ULPI_DIR_PY1] = "ulpi_dir_py1",
355 [PMUX_PINGRP_ULPI_NXT_PY2] = "ulpi_nxt_py2",
356 [PMUX_PINGRP_ULPI_STP_PY3] = "ulpi_stp_py3",
357 [PMUX_PINGRP_DAP3_FS_PP0] = "dap3_fs_pp0",
358 [PMUX_PINGRP_DAP3_DIN_PP1] = "dap3_din_pp1",
359 [PMUX_PINGRP_DAP3_DOUT_PP2] = "dap3_dout_pp2",
360 [PMUX_PINGRP_DAP3_SCLK_PP3] = "dap3_sclk_pp3",
361 [PMUX_PINGRP_PV0] = "pv0",
362 [PMUX_PINGRP_PV1] = "pv1",
363 [PMUX_PINGRP_SDMMC1_CLK_PZ0] = "sdmmc1_clk_pz0",
364 [PMUX_PINGRP_SDMMC1_CMD_PZ1] = "sdmmc1_cmd_pz1",
365 [PMUX_PINGRP_SDMMC1_DAT3_PY4] = "sdmmc1_dat3_py4",
366 [PMUX_PINGRP_SDMMC1_DAT2_PY5] = "sdmmc1_dat2_py5",
367 [PMUX_PINGRP_SDMMC1_DAT1_PY6] = "sdmmc1_dat1_py6",
368 [PMUX_PINGRP_SDMMC1_DAT0_PY7] = "sdmmc1_dat0_py7",
369 [PMUX_PINGRP_CLK2_OUT_PW5] = "clk2_out_pw5",
370 [PMUX_PINGRP_CLK2_REQ_PCC5] = "clk2_req_pcc5",
371 [PMUX_PINGRP_HDMI_INT_PN7] = "hdmi_int_pn7",
372 [PMUX_PINGRP_DDC_SCL_PV4] = "ddc_scl_pv4",
373 [PMUX_PINGRP_DDC_SDA_PV5] = "ddc_sda_pv5",
374 [PMUX_PINGRP_UART2_RXD_PC3] = "uart2_rxd_pc3",
375 [PMUX_PINGRP_UART2_TXD_PC2] = "uart2_txd_pc2",
376 [PMUX_PINGRP_UART2_RTS_N_PJ6] = "uart2_rts_n_pj6",
377 [PMUX_PINGRP_UART2_CTS_N_PJ5] = "uart2_cts_n_pj5",
378 [PMUX_PINGRP_UART3_TXD_PW6] = "uart3_txd_pw6",
379 [PMUX_PINGRP_UART3_RXD_PW7] = "uart3_rxd_pw7",
380 [PMUX_PINGRP_UART3_CTS_N_PA1] = "uart3_cts_n_pa1",
381 [PMUX_PINGRP_UART3_RTS_N_PC0] = "uart3_rts_n_pc0",
382 [PMUX_PINGRP_PU0] = "pu0",
383 [PMUX_PINGRP_PU1] = "pu1",
384 [PMUX_PINGRP_PU2] = "pu2",
385 [PMUX_PINGRP_PU3] = "pu3",
386 [PMUX_PINGRP_PU4] = "pu4",
387 [PMUX_PINGRP_PU5] = "pu5",
388 [PMUX_PINGRP_PU6] = "pu6",
389 [PMUX_PINGRP_GEN1_I2C_SDA_PC5] = "gen1_i2c_sda_pc5",
390 [PMUX_PINGRP_GEN1_I2C_SCL_PC4] = "gen1_i2c_scl_pc4",
391 [PMUX_PINGRP_DAP4_FS_PP4] = "dap4_fs_pp4",
392 [PMUX_PINGRP_DAP4_DIN_PP5] = "dap4_din_pp5",
393 [PMUX_PINGRP_DAP4_DOUT_PP6] = "dap4_dout_pp6",
394 [PMUX_PINGRP_DAP4_SCLK_PP7] = "dap4_sclk_pp7",
395 [PMUX_PINGRP_CLK3_OUT_PEE0] = "clk3_out_pee0",
396 [PMUX_PINGRP_CLK3_REQ_PEE1] = "clk3_req_pee1",
397 [PMUX_PINGRP_PC7] = "pc7",
398 [PMUX_PINGRP_PI5] = "pi5",
399 [PMUX_PINGRP_PI7] = "pi7",
400 [PMUX_PINGRP_PK0] = "pk0",
401 [PMUX_PINGRP_PK1] = "pk1",
402 [PMUX_PINGRP_PJ0] = "pj0",
403 [PMUX_PINGRP_PJ2] = "pj2",
404 [PMUX_PINGRP_PK3] = "pk3",
405 [PMUX_PINGRP_PK4] = "pk4",
406 [PMUX_PINGRP_PK2] = "pk2",
407 [PMUX_PINGRP_PI3] = "pi3",
408 [PMUX_PINGRP_PI6] = "pi6",
409 [PMUX_PINGRP_PG0] = "pg0",
410 [PMUX_PINGRP_PG1] = "pg1",
411 [PMUX_PINGRP_PG2] = "pg2",
412 [PMUX_PINGRP_PG3] = "pg3",
413 [PMUX_PINGRP_PG4] = "pg4",
414 [PMUX_PINGRP_PG5] = "pg5",
415 [PMUX_PINGRP_PG6] = "pg6",
416 [PMUX_PINGRP_PG7] = "pg7",
417 [PMUX_PINGRP_PH0] = "ph0",
418 [PMUX_PINGRP_PH1] = "ph1",
419 [PMUX_PINGRP_PH2] = "ph2",
420 [PMUX_PINGRP_PH3] = "ph3",
421 [PMUX_PINGRP_PH4] = "ph4",
422 [PMUX_PINGRP_PH5] = "ph5",
423 [PMUX_PINGRP_PH6] = "ph6",
424 [PMUX_PINGRP_PH7] = "ph7",
425 [PMUX_PINGRP_PJ7] = "pj7",
426 [PMUX_PINGRP_PB0] = "pb0",
427 [PMUX_PINGRP_PB1] = "pb1",
428 [PMUX_PINGRP_PK7] = "pk7",
429 [PMUX_PINGRP_PI0] = "pi0",
430 [PMUX_PINGRP_PI1] = "pi1",
431 [PMUX_PINGRP_PI2] = "pi2",
432 [PMUX_PINGRP_PI4] = "pi4",
433 [PMUX_PINGRP_GEN2_I2C_SCL_PT5] = "gen2_i2c_scl_pt5",
434 [PMUX_PINGRP_GEN2_I2C_SDA_PT6] = "gen2_i2c_sda_pt6",
435 [PMUX_PINGRP_SDMMC4_CLK_PCC4] = "sdmmc4_clk_pcc4",
436 [PMUX_PINGRP_SDMMC4_CMD_PT7] = "sdmmc4_cmd_pt7",
437 [PMUX_PINGRP_SDMMC4_DAT0_PAA0] = "sdmmc4_dat0_paa0",
438 [PMUX_PINGRP_SDMMC4_DAT1_PAA1] = "sdmmc4_dat1_paa1",
439 [PMUX_PINGRP_SDMMC4_DAT2_PAA2] = "sdmmc4_dat2_paa2",
440 [PMUX_PINGRP_SDMMC4_DAT3_PAA3] = "sdmmc4_dat3_paa3",
441 [PMUX_PINGRP_SDMMC4_DAT4_PAA4] = "sdmmc4_dat4_paa4",
442 [PMUX_PINGRP_SDMMC4_DAT5_PAA5] = "sdmmc4_dat5_paa5",
443 [PMUX_PINGRP_SDMMC4_DAT6_PAA6] = "sdmmc4_dat6_paa6",
444 [PMUX_PINGRP_SDMMC4_DAT7_PAA7] = "sdmmc4_dat7_paa7",
445 [PMUX_PINGRP_CAM_MCLK_PCC0] = "cam_mclk_pcc0",
446 [PMUX_PINGRP_PCC1] = "pcc1",
447 [PMUX_PINGRP_PBB0] = "pbb0",
448 [PMUX_PINGRP_CAM_I2C_SCL_PBB1] = "cam_i2c_scl_pbb1",
449 [PMUX_PINGRP_CAM_I2C_SDA_PBB2] = "cam_i2c_sda_pbb2",
450 [PMUX_PINGRP_PBB3] = "pbb3",
451 [PMUX_PINGRP_PBB4] = "pbb4",
452 [PMUX_PINGRP_PBB5] = "pbb5",
453 [PMUX_PINGRP_PBB6] = "pbb6",
454 [PMUX_PINGRP_PBB7] = "pbb7",
455 [PMUX_PINGRP_PCC2] = "pcc2",
456 [PMUX_PINGRP_JTAG_RTCK] = "jtag_rtck",
457 [PMUX_PINGRP_PWR_I2C_SCL_PZ6] = "pwr_i2c_scl_pz6",
458 [PMUX_PINGRP_PWR_I2C_SDA_PZ7] = "pwr_i2c_sda_pz7",
459 [PMUX_PINGRP_KB_ROW0_PR0] = "kb_row0_pr0",
460 [PMUX_PINGRP_KB_ROW1_PR1] = "kb_row1_pr1",
461 [PMUX_PINGRP_KB_ROW2_PR2] = "kb_row2_pr2",
462 [PMUX_PINGRP_KB_ROW3_PR3] = "kb_row3_pr3",
463 [PMUX_PINGRP_KB_ROW4_PR4] = "kb_row4_pr4",
464 [PMUX_PINGRP_KB_ROW5_PR5] = "kb_row5_pr5",
465 [PMUX_PINGRP_KB_ROW6_PR6] = "kb_row6_pr6",
466 [PMUX_PINGRP_KB_ROW7_PR7] = "kb_row7_pr7",
467 [PMUX_PINGRP_KB_ROW8_PS0] = "kb_row8_ps0",
468 [PMUX_PINGRP_KB_ROW9_PS1] = "kb_row9_ps1",
469 [PMUX_PINGRP_KB_ROW10_PS2] = "kb_row10_ps2",
470 [PMUX_PINGRP_KB_ROW11_PS3] = "kb_row11_ps3",
471 [PMUX_PINGRP_KB_ROW12_PS4] = "kb_row12_ps4",
472 [PMUX_PINGRP_KB_ROW13_PS5] = "kb_row13_ps5",
473 [PMUX_PINGRP_KB_ROW14_PS6] = "kb_row14_ps6",
474 [PMUX_PINGRP_KB_ROW15_PS7] = "kb_row15_ps7",
475 [PMUX_PINGRP_KB_COL0_PQ0] = "kb_col0_pq0",
476 [PMUX_PINGRP_KB_COL1_PQ1] = "kb_col1_pq1",
477 [PMUX_PINGRP_KB_COL2_PQ2] = "kb_col2_pq2",
478 [PMUX_PINGRP_KB_COL3_PQ3] = "kb_col3_pq3",
479 [PMUX_PINGRP_KB_COL4_PQ4] = "kb_col4_pq4",
480 [PMUX_PINGRP_KB_COL5_PQ5] = "kb_col5_pq5",
481 [PMUX_PINGRP_KB_COL6_PQ6] = "kb_col6_pq6",
482 [PMUX_PINGRP_KB_COL7_PQ7] = "kb_col7_pq7",
483 [PMUX_PINGRP_CLK_32K_OUT_PA0] = "clk_32k_out_pa0",
484 [PMUX_PINGRP_CORE_PWR_REQ] = "core_pwr_req",
485 [PMUX_PINGRP_CPU_PWR_REQ] = "cpu_pwr_req",
486 [PMUX_PINGRP_PWR_INT_N] = "pwr_int_n",
487 [PMUX_PINGRP_CLK_32K_IN] = "clk_32k_in",
488 [PMUX_PINGRP_OWR] = "owr",
489 [PMUX_PINGRP_DAP1_FS_PN0] = "dap1_fs_pn0",
490 [PMUX_PINGRP_DAP1_DIN_PN1] = "dap1_din_pn1",
491 [PMUX_PINGRP_DAP1_DOUT_PN2] = "dap1_dout_pn2",
492 [PMUX_PINGRP_DAP1_SCLK_PN3] = "dap1_sclk_pn3",
493 [PMUX_PINGRP_DAP_MCLK1_REQ_PEE2] = "dap_mclk1_req_pee2",
494 [PMUX_PINGRP_DAP_MCLK1_PW4] = "dap_mclk1_pw4",
495 [PMUX_PINGRP_SPDIF_IN_PK6] = "spdif_in_pk6",
496 [PMUX_PINGRP_SPDIF_OUT_PK5] = "spdif_out_pk5",
497 [PMUX_PINGRP_DAP2_FS_PA2] = "dap2_fs_pa2",
498 [PMUX_PINGRP_DAP2_DIN_PA4] = "dap2_din_pa4",
499 [PMUX_PINGRP_DAP2_DOUT_PA5] = "dap2_dout_pa5",
500 [PMUX_PINGRP_DAP2_SCLK_PA3] = "dap2_sclk_pa3",
501 [PMUX_PINGRP_DVFS_PWM_PX0] = "dvfs_pwm_px0",
502 [PMUX_PINGRP_GPIO_X1_AUD_PX1] = "gpio_x1_aud_px1",
503 [PMUX_PINGRP_GPIO_X3_AUD_PX3] = "gpio_x3_aud_px3",
504 [PMUX_PINGRP_DVFS_CLK_PX2] = "dvfs_clk_px2",
505 [PMUX_PINGRP_GPIO_X4_AUD_PX4] = "gpio_x4_aud_px4",
506 [PMUX_PINGRP_GPIO_X5_AUD_PX5] = "gpio_x5_aud_px5",
507 [PMUX_PINGRP_GPIO_X6_AUD_PX6] = "gpio_x6_aud_px6",
508 [PMUX_PINGRP_GPIO_X7_AUD_PX7] = "gpio_x7_aud_px7",
509 [PMUX_PINGRP_SDMMC3_CLK_PA6] = "sdmmc3_clk_pa6",
510 [PMUX_PINGRP_SDMMC3_CMD_PA7] = "sdmmc3_cmd_pa7",
511 [PMUX_PINGRP_SDMMC3_DAT0_PB7] = "sdmmc3_dat0_pb7",
512 [PMUX_PINGRP_SDMMC3_DAT1_PB6] = "sdmmc3_dat1_pb6",
513 [PMUX_PINGRP_SDMMC3_DAT2_PB5] = "sdmmc3_dat2_pb5",
514 [PMUX_PINGRP_SDMMC3_DAT3_PB4] = "sdmmc3_dat3_pb4",
515 [PMUX_PINGRP_PEX_L0_RST_N_PDD1] = "pex_l0_rst_n_pdd1",
516 [PMUX_PINGRP_PEX_L0_CLKREQ_N_PDD2] = "pex_l0_clkreq_n_pdd2",
517 [PMUX_PINGRP_PEX_WAKE_N_PDD3] = "pex_wake_n_pdd3",
518 [PMUX_PINGRP_PEX_L1_RST_N_PDD5] = "pex_l1_rst_n_pdd5",
519 [PMUX_PINGRP_PEX_L1_CLKREQ_N_PDD6] = "pex_l1_clkreq_n_pdd6",
520 [PMUX_PINGRP_HDMI_CEC_PEE3] = "hdmi_cec_pee3",
521 [PMUX_PINGRP_SDMMC1_WP_N_PV3] = "sdmmc1_wp_n_pv3",
522 [PMUX_PINGRP_SDMMC3_CD_N_PV2] = "sdmmc3_cd_n_pv2",
523 [PMUX_PINGRP_GPIO_W2_AUD_PW2] = "gpio_w2_aud_pw2",
524 [PMUX_PINGRP_GPIO_W3_AUD_PW3] = "gpio_w3_aud_pw3",
525 [PMUX_PINGRP_USB_VBUS_EN0_PN4] = "usb_vbus_en0_pn4",
526 [PMUX_PINGRP_USB_VBUS_EN1_PN5] = "usb_vbus_en1_pn5",
527 [PMUX_PINGRP_SDMMC3_CLK_LB_IN_PEE5] = "sdmmc3_clk_lb_in_pee5",
528 [PMUX_PINGRP_SDMMC3_CLK_LB_OUT_PEE4] = "sdmmc3_clk_lb_out_pee4",
529 [PMUX_PINGRP_GMI_CLK_LB] = "gmi_clk_lb",
530 [PMUX_PINGRP_RESET_OUT_N] = "reset_out_n",
531 [PMUX_PINGRP_KB_ROW16_PT0] = "kb_row16_pt0",
532 [PMUX_PINGRP_KB_ROW17_PT1] = "kb_row17_pt1",
533 [PMUX_PINGRP_USB_VBUS_EN2_PFF1] = "usb_vbus_en2_pff1",
534 [PMUX_PINGRP_PFF2] = "pff2",
535 [PMUX_PINGRP_DP_HPD_PFF0] = "dp_hpd_pff0",
536};
537
538static const char * const tegra_pinctrl_to_drvgrp[] = {
539 [PMUX_DRVGRP_AO1] = "ao1",
540 [PMUX_DRVGRP_AO2] = "ao2",
541 [PMUX_DRVGRP_AT1] = "at1",
542 [PMUX_DRVGRP_AT2] = "at2",
543 [PMUX_DRVGRP_AT3] = "at3",
544 [PMUX_DRVGRP_AT4] = "at4",
545 [PMUX_DRVGRP_AT5] = "at5",
546 [PMUX_DRVGRP_CDEV1] = "cdev1",
547 [PMUX_DRVGRP_CDEV2] = "cdev2",
548 [PMUX_DRVGRP_DAP1] = "dap1",
549 [PMUX_DRVGRP_DAP2] = "dap2",
550 [PMUX_DRVGRP_DAP3] = "dap3",
551 [PMUX_DRVGRP_DAP4] = "dap4",
552 [PMUX_DRVGRP_DBG] = "dbg",
553 [PMUX_DRVGRP_SDIO3] = "sdio3",
554 [PMUX_DRVGRP_SPI] = "spi",
555 [PMUX_DRVGRP_UAA] = "uaa",
556 [PMUX_DRVGRP_UAB] = "uab",
557 [PMUX_DRVGRP_UART2] = "uart2",
558 [PMUX_DRVGRP_UART3] = "uart3",
559 [PMUX_DRVGRP_SDIO1] = "sdio1",
560 [PMUX_DRVGRP_DDC] = "ddc",
561 [PMUX_DRVGRP_GMA] = "gma",
562 [PMUX_DRVGRP_GME] = "gme",
563 [PMUX_DRVGRP_GMF] = "gmf",
564 [PMUX_DRVGRP_GMG] = "gmg",
565 [PMUX_DRVGRP_GMH] = "gmh",
566 [PMUX_DRVGRP_OWR] = "owr",
567 [PMUX_DRVGRP_UDA] = "uda",
568 [PMUX_DRVGRP_GPV] = "gpv",
569 [PMUX_DRVGRP_DEV3] = "dev3",
570 [PMUX_DRVGRP_CEC] = "cec",
571 [PMUX_DRVGRP_AT6] = "at6",
572 [PMUX_DRVGRP_DAP5] = "dap5",
573 [PMUX_DRVGRP_USB_VBUS_EN] = "usb_vbus_en",
574 [PMUX_DRVGRP_AO3] = "ao3",
575 [PMUX_DRVGRP_AO0] = "ao0",
576 [PMUX_DRVGRP_HV0] = "hv0",
577 [PMUX_DRVGRP_SDIO4] = "sdio4",
578 [PMUX_DRVGRP_AO4] = "ao4",
579};
580
581static const char * const tegra_pinctrl_to_func[] = {
582 [PMUX_FUNC_DEFAULT] = "default",
583 [PMUX_FUNC_BLINK] = "blink",
584 [PMUX_FUNC_CCLA] = "ccla",
585 [PMUX_FUNC_CEC] = "cec",
586 [PMUX_FUNC_CLDVFS] = "cldvfs",
587 [PMUX_FUNC_CLK] = "clk",
588 [PMUX_FUNC_CLK12] = "clk12",
589 [PMUX_FUNC_CPU] = "cpu",
590 [PMUX_FUNC_CSI] = "csi",
591 [PMUX_FUNC_DAP] = "dap",
592 [PMUX_FUNC_DAP1] = "dap1",
593 [PMUX_FUNC_DAP2] = "dap2",
594 [PMUX_FUNC_DEV3] = "dev3",
595 [PMUX_FUNC_DISPLAYA] = "displaya",
596 [PMUX_FUNC_DISPLAYA_ALT] = "displaya_alt",
597 [PMUX_FUNC_DISPLAYB] = "displayb",
598 [PMUX_FUNC_DP] = "dp",
599 [PMUX_FUNC_DSI_B] = "dsi_b",
600 [PMUX_FUNC_DTV] = "dtv",
601 [PMUX_FUNC_EXTPERIPH1] = "extperiph1",
602 [PMUX_FUNC_EXTPERIPH2] = "extperiph2",
603 [PMUX_FUNC_EXTPERIPH3] = "extperiph3",
604 [PMUX_FUNC_GMI] = "gmi",
605 [PMUX_FUNC_GMI_ALT] = "gmi_alt",
606 [PMUX_FUNC_HDA] = "hda",
607 [PMUX_FUNC_HSI] = "hsi",
608 [PMUX_FUNC_I2C1] = "i2c1",
609 [PMUX_FUNC_I2C2] = "i2c2",
610 [PMUX_FUNC_I2C3] = "i2c3",
611 [PMUX_FUNC_I2C4] = "i2c4",
612 [PMUX_FUNC_I2CPWR] = "i2cpwr",
613 [PMUX_FUNC_I2S0] = "i2s0",
614 [PMUX_FUNC_I2S1] = "i2s1",
615 [PMUX_FUNC_I2S2] = "i2s2",
616 [PMUX_FUNC_I2S3] = "i2s3",
617 [PMUX_FUNC_I2S4] = "i2s4",
618 [PMUX_FUNC_IRDA] = "irda",
619 [PMUX_FUNC_KBC] = "kbc",
620 [PMUX_FUNC_OWR] = "owr",
621 [PMUX_FUNC_PE] = "pe",
622 [PMUX_FUNC_PE0] = "pe0",
623 [PMUX_FUNC_PE1] = "pe1",
624 [PMUX_FUNC_PMI] = "pmi",
625 [PMUX_FUNC_PWM0] = "pwm0",
626 [PMUX_FUNC_PWM1] = "pwm1",
627 [PMUX_FUNC_PWM2] = "pwm2",
628 [PMUX_FUNC_PWM3] = "pwm3",
629 [PMUX_FUNC_PWRON] = "pwron",
630 [PMUX_FUNC_RESET_OUT_N] = "reset_out_n",
631 [PMUX_FUNC_RTCK] = "rtck",
632 [PMUX_FUNC_SATA] = "sata",
633 [PMUX_FUNC_SDMMC1] = "sdmmc1",
634 [PMUX_FUNC_SDMMC2] = "sdmmc2",
635 [PMUX_FUNC_SDMMC3] = "sdmmc3",
636 [PMUX_FUNC_SDMMC4] = "sdmmc4",
637 [PMUX_FUNC_SOC] = "soc",
638 [PMUX_FUNC_SPDIF] = "spdif",
639 [PMUX_FUNC_SPI1] = "spi1",
640 [PMUX_FUNC_SPI2] = "spi2",
641 [PMUX_FUNC_SPI3] = "spi3",
642 [PMUX_FUNC_SPI4] = "spi4",
643 [PMUX_FUNC_SPI5] = "spi5",
644 [PMUX_FUNC_SPI6] = "spi6",
645 [PMUX_FUNC_SYS] = "sys",
646 [PMUX_FUNC_TMDS] = "tmds",
647 [PMUX_FUNC_TRACE] = "trace",
648 [PMUX_FUNC_UARTA] = "uarta",
649 [PMUX_FUNC_UARTB] = "uartb",
650 [PMUX_FUNC_UARTC] = "uartc",
651 [PMUX_FUNC_UARTD] = "uartd",
652 [PMUX_FUNC_ULPI] = "ulpi",
653 [PMUX_FUNC_USB] = "usb",
654 [PMUX_FUNC_VGP1] = "vgp1",
655 [PMUX_FUNC_VGP2] = "vgp2",
656 [PMUX_FUNC_VGP3] = "vgp3",
657 [PMUX_FUNC_VGP4] = "vgp4",
658 [PMUX_FUNC_VGP5] = "vgp5",
659 [PMUX_FUNC_VGP6] = "vgp6",
660 [PMUX_FUNC_VI] = "vi",
661 [PMUX_FUNC_VI_ALT1] = "vi_alt1",
662 [PMUX_FUNC_VI_ALT3] = "vi_alt3",
663 [PMUX_FUNC_VIMCLK2] = "vimclk2",
664 [PMUX_FUNC_VIMCLK2_ALT] = "vimclk2_alt",
665 [PMUX_FUNC_RSVD1] = "rsvd1",
666 [PMUX_FUNC_RSVD2] = "rsvd2",
667 [PMUX_FUNC_RSVD3] = "rsvd3",
668 [PMUX_FUNC_RSVD4] = "rsvd4",
669};
670
Stephen Warren51f9e722015-02-24 14:08:29 -0700[diff] [blame]671#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
Stephen Warrend937fb52015-03-25 12:04:37 -0600[diff] [blame]672#define TEGRA_PMX_SOC_MIPIPADCTRL_BASE_REG 0x820
Stephen Warren22d57fe2015-02-24 14:08:24 -0700[diff] [blame]673#define TEGRA_PMX_SOC_HAS_IO_CLAMPING
674#define TEGRA_PMX_SOC_HAS_DRVGRPS
Stephen Warrend937fb52015-03-25 12:04:37 -0600[diff] [blame]675#define TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS
Stephen Warren3e9fb7b2015-02-24 14:08:25 -0700[diff] [blame]676#define TEGRA_PMX_GRPS_HAVE_LPMD
677#define TEGRA_PMX_GRPS_HAVE_SCHMT
678#define TEGRA_PMX_GRPS_HAVE_HSM
Stephen Warren22d57fe2015-02-24 14:08:24 -0700[diff] [blame]679#define TEGRA_PMX_PINS_HAVE_E_INPUT
680#define TEGRA_PMX_PINS_HAVE_LOCK
681#define TEGRA_PMX_PINS_HAVE_OD
682#define TEGRA_PMX_PINS_HAVE_IO_RESET
683#define TEGRA_PMX_PINS_HAVE_RCV_SEL
Stephen Warren9026dfd2014-03-21 12:28:54 -0600[diff] [blame]684#include <asm/arch-tegra/pinmux.h>
Tom Warrenb7ea6d12014-01-24 12:46:13 -0700[diff] [blame]685
Stephen Warren9026dfd2014-03-21 12:28:54 -0600[diff] [blame]686#endif /* _TEGRA124_PINMUX_H_ */