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git01.mediatek.com / filogic / uboot / f4df60515232c75472a43d1b5ba25f3724e74619 / . / arch / arm / include / asm / arch-tegra124 / pinmux.h
blob: b3759067120290c912162daace8a0fd4d64c93d4 [file] [log] [blame]
Tom Warrenb7ea6d12014-01-24 12:46:13 -0700[diff] [blame]1/*
2 * (C) Copyright 2013
3 * NVIDIA Corporation <www.nvidia.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#ifndef _TEGRA124_PINMUX_H_
9#define _TEGRA124_PINMUX_H_
10
11/*
12 * Pin groups which we adjust. There are three basic attributes of each pin
13 * group which use this enum:
14 *
15 * - function
16 * - pullup / pulldown
17 * - tristate or normal
18 */
19enum pmux_pingrp {
20 PINGRP_ULPI_DATA0 = 0, /* offset 0x3000 */
21 PINGRP_ULPI_DATA1,
22 PINGRP_ULPI_DATA2,
23 PINGRP_ULPI_DATA3,
24 PINGRP_ULPI_DATA4,
25 PINGRP_ULPI_DATA5,
26 PINGRP_ULPI_DATA6,
27 PINGRP_ULPI_DATA7,
28 PINGRP_ULPI_CLK,
29 PINGRP_ULPI_DIR,
30 PINGRP_ULPI_NXT,
31 PINGRP_ULPI_STP,
32 PINGRP_DAP3_FS,
33 PINGRP_DAP3_DIN,
34 PINGRP_DAP3_DOUT,
35 PINGRP_DAP3_SCLK,
36 PINGRP_GPIO_PV0,
37 PINGRP_GPIO_PV1,
38 PINGRP_SDMMC1_CLK,
39 PINGRP_SDMMC1_CMD,
40 PINGRP_SDMMC1_DAT3,
41 PINGRP_SDMMC1_DAT2,
42 PINGRP_SDMMC1_DAT1,
43 PINGRP_SDMMC1_DAT0,
44 PINGRP_CLK2_OUT = PINGRP_SDMMC1_DAT0 + 3,
45 PINGRP_CLK2_REQ,
46 PINGRP_HDMI_INT = PINGRP_CLK2_REQ + 41,
47 PINGRP_DDC_SCL,
48 PINGRP_DDC_SDA,
49 PINGRP_UART2_RXD = PINGRP_DDC_SDA + 19,
50 PINGRP_UART2_TXD,
51 PINGRP_UART2_RTS_N,
52 PINGRP_UART2_CTS_N,
53 PINGRP_UART3_TXD,
54 PINGRP_UART3_RXD,
55 PINGRP_UART3_CTS_N,
56 PINGRP_UART3_RTS_N,
57 PINGRP_GPIO_PU0,
58 PINGRP_GPIO_PU1,
59 PINGRP_GPIO_PU2,
60 PINGRP_GPIO_PU3,
61 PINGRP_GPIO_PU4,
62 PINGRP_GPIO_PU5,
63 PINGRP_GPIO_PU6,
64 PINGRP_GEN1_I2C_SDA,
65 PINGRP_GEN1_I2C_SCL,
66 PINGRP_DAP4_FS,
67 PINGRP_DAP4_DIN,
68 PINGRP_DAP4_DOUT,
69 PINGRP_DAP4_SCLK,
70 PINGRP_CLK3_OUT,
71 PINGRP_CLK3_REQ,
72 /* Renamed on Tegra124, from GMI_xx to GPIO_Pxx */
73 PINGRP_GPIO_PC7, /* offset 0x31c0 */
74 PINGRP_GPIO_PI5,
75 PINGRP_GPIO_PI7,
76 PINGRP_GPIO_PK0,
77 PINGRP_GPIO_PK1,
78 PINGRP_GPIO_PJ0,
79 PINGRP_GPIO_PJ2,
80 PINGRP_GPIO_PK3,
81 PINGRP_GPIO_PK4,
82 PINGRP_GPIO_PK2,
83 PINGRP_GPIO_PI3,
84 PINGRP_GPIO_PI6,
85 PINGRP_GPIO_PG0,
86 PINGRP_GPIO_PG1,
87 PINGRP_GPIO_PG2,
88 PINGRP_GPIO_PG3,
89 PINGRP_GPIO_PG4,
90 PINGRP_GPIO_PG5,
91 PINGRP_GPIO_PG6,
92 PINGRP_GPIO_PG7,
93 PINGRP_GPIO_PH0,
94 PINGRP_GPIO_PH1,
95 PINGRP_GPIO_PH2,
96 PINGRP_GPIO_PH3,
97 PINGRP_GPIO_PH4,
98 PINGRP_GPIO_PH5,
99 PINGRP_GPIO_PH6,
100 PINGRP_GPIO_PH7,
101 PINGRP_GPIO_PJ7,
102 PINGRP_GPIO_PB0,
103 PINGRP_GPIO_PB1,
104 PINGRP_GPIO_PK7,
105 PINGRP_GPIO_PI0,
106 PINGRP_GPIO_PI1,
107 PINGRP_GPIO_PI2,
108 PINGRP_GPIO_PI4, /* offset 0x324c */
109 PINGRP_GEN2_I2C_SCL,
110 PINGRP_GEN2_I2C_SDA,
111 PINGRP_SDMMC4_CLK,
112 PINGRP_SDMMC4_CMD,
113 PINGRP_SDMMC4_DAT0,
114 PINGRP_SDMMC4_DAT1,
115 PINGRP_SDMMC4_DAT2,
116 PINGRP_SDMMC4_DAT3,
117 PINGRP_SDMMC4_DAT4,
118 PINGRP_SDMMC4_DAT5,
119 PINGRP_SDMMC4_DAT6,
120 PINGRP_SDMMC4_DAT7,
121 PINGRP_CAM_MCLK = PINGRP_SDMMC4_DAT7 + 2,
122 PINGRP_GPIO_PCC1,
123 PINGRP_GPIO_PBB0,
124 PINGRP_CAM_I2C_SCL,
125 PINGRP_CAM_I2C_SDA,
126 PINGRP_GPIO_PBB3,
127 PINGRP_GPIO_PBB4,
128 PINGRP_GPIO_PBB5,
129 PINGRP_GPIO_PBB6,
130 PINGRP_GPIO_PBB7,
131 PINGRP_GPIO_PCC2,
132 PINGRP_JTAG_RTCK,
133 PINGRP_PWR_I2C_SCL,
134 PINGRP_PWR_I2C_SDA,
135 PINGRP_KB_ROW0,
136 PINGRP_KB_ROW1,
137 PINGRP_KB_ROW2,
138 PINGRP_KB_ROW3,
139 PINGRP_KB_ROW4,
140 PINGRP_KB_ROW5,
141 PINGRP_KB_ROW6,
142 PINGRP_KB_ROW7,
143 PINGRP_KB_ROW8,
144 PINGRP_KB_ROW9,
145 PINGRP_KB_ROW10,
146 PINGRP_KB_ROW11,
147 PINGRP_KB_ROW12,
148 PINGRP_KB_ROW13,
149 PINGRP_KB_ROW14,
150 PINGRP_KB_ROW15,
151 PINGRP_KB_COL0, /* offset 0x32fc */
152 PINGRP_KB_COL1,
153 PINGRP_KB_COL2,
154 PINGRP_KB_COL3,
155 PINGRP_KB_COL4,
156 PINGRP_KB_COL5,
157 PINGRP_KB_COL6,
158 PINGRP_KB_COL7,
159 PINGRP_CLK_32K_OUT,
160 PINGRP_CORE_PWR_REQ = PINGRP_CLK_32K_OUT + 2, /* offset 0x3324 */
161 PINGRP_CPU_PWR_REQ,
162 PINGRP_PWR_INT_N,
163 PINGRP_CLK_32K_IN,
164 PINGRP_OWR,
165 PINGRP_DAP1_FS,
166 PINGRP_DAP1_DIN,
167 PINGRP_DAP1_DOUT,
168 PINGRP_DAP1_SCLK,
169 PINGRP_CLK1_REQ,
170 PINGRP_CLK1_OUT,
171 PINGRP_SPDIF_IN,
172 PINGRP_SPDIF_OUT,
173 PINGRP_DAP2_FS,
174 PINGRP_DAP2_DIN,
175 PINGRP_DAP2_DOUT,
176 PINGRP_DAP2_SCLK,
177 PINGRP_DVFS_PWM,
178 PINGRP_GPIO_X1_AUD,
179 PINGRP_GPIO_X3_AUD,
180 PINGRP_DVFS_CLK,
181 PINGRP_GPIO_X4_AUD,
182 PINGRP_GPIO_X5_AUD,
183 PINGRP_GPIO_X6_AUD,
184 PINGRP_GPIO_X7_AUD,
185 PINGRP_SDMMC3_CLK = PINGRP_GPIO_X7_AUD + 3,
186 PINGRP_SDMMC3_CMD,
187 PINGRP_SDMMC3_DAT0,
188 PINGRP_SDMMC3_DAT1,
189 PINGRP_SDMMC3_DAT2,
190 PINGRP_SDMMC3_DAT3,
191 PINGRP_PEX_L0_RST = PINGRP_SDMMC3_DAT3 + 6, /* offset 0x33bc */
192 PINGRP_PEX_L0_CLKREQ,
193 PINGRP_PEX_WAKE,
194 PINGRP_PEX_L1_RST = PINGRP_PEX_WAKE + 2,
195 PINGRP_PEX_L1_CLKREQ,
196 PINGRP_HDMI_CEC = PINGRP_PEX_L1_CLKREQ + 4, /* offset 0x33e0 */
197 PINGRP_SDMMC1_WP_N,
198 PINGRP_SDMMC3_CD_N,
199 PINGRP_GPIO_W2_AUD,
200 PINGRP_GPIO_W3_AUD,
201 PINGRP_USB_VBUS_EN0,
202 PINGRP_USB_VBUS_EN1,
203 PINGRP_SDMMC3_CLK_LB_IN,
204 PINGRP_SDMMC3_CLK_LB_OUT,
205 PINGRP_GMI_CLK_LB,
206 PINGRP_RESET_OUT_N,
207 PINGRP_KB_ROW16, /* offset 0x340c */
208 PINGRP_KB_ROW17,
209 PINGRP_USB_VBUS_EN2,
210 PINGRP_GPIO_PFF2,
211 PINGRP_DP_HPD, /* last reg offset = 0x3430 */
Stephen Warrenf4df6052014-03-21 12:28:56 -0600[diff] [blame^]212 PMUX_PINGRP_COUNT,
Tom Warrenb7ea6d12014-01-24 12:46:13 -0700[diff] [blame]213};
214
Stephen Warrenf4df6052014-03-21 12:28:56 -0600[diff] [blame^]215enum pmux_drvgrp {
Tom Warrenb7ea6d12014-01-24 12:46:13 -0700[diff] [blame]216 PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */
217 PDRIVE_PINGROUP_AO2,
218 PDRIVE_PINGROUP_AT1,
219 PDRIVE_PINGROUP_AT2,
220 PDRIVE_PINGROUP_AT3,
221 PDRIVE_PINGROUP_AT4,
222 PDRIVE_PINGROUP_AT5,
223 PDRIVE_PINGROUP_CDEV1,
224 PDRIVE_PINGROUP_CDEV2,
225 PDRIVE_PINGROUP_DAP1 = 10, /* offset 0x890 */
226 PDRIVE_PINGROUP_DAP2,
227 PDRIVE_PINGROUP_DAP3,
228 PDRIVE_PINGROUP_DAP4,
229 PDRIVE_PINGROUP_DBG,
230 PDRIVE_PINGROUP_SDIO3 = 18, /* offset 0x8B0 */
231 PDRIVE_PINGROUP_SPI,
232 PDRIVE_PINGROUP_UAA,
233 PDRIVE_PINGROUP_UAB,
234 PDRIVE_PINGROUP_UART2,
235 PDRIVE_PINGROUP_UART3,
236 PDRIVE_PINGROUP_SDIO1 = 33, /* offset 0x8EC */
237 PDRIVE_PINGROUP_DDC = 37, /* offset 0x8FC */
238 PDRIVE_PINGROUP_GMA,
239 PDRIVE_PINGROUP_GME = 42, /* offset 0x910 */
240 PDRIVE_PINGROUP_GMF,
241 PDRIVE_PINGROUP_GMG,
242 PDRIVE_PINGROUP_GMH,
243 PDRIVE_PINGROUP_OWR,
244 PDRIVE_PINGROUP_UAD,
245 PDRIVE_PINGROUP_DEV3 = 49, /* offset 0x92c */
246 PDRIVE_PINGROUP_CEC = 52, /* offset 0x938 */
247 PDRIVE_PINGROUP_AT6 = 75, /* offset 0x994 */
248 PDRIVE_PINGROUP_DAP5,
249 PDRIVE_PINGROUP_VBUS,
250 PDRIVE_PINGROUP_AO3,
251 PDRIVE_PINGROUP_HVC,
252 PDRIVE_PINGROUP_SDIO4,
253 PDRIVE_PINGROUP_AO0,
Stephen Warrenf4df6052014-03-21 12:28:56 -0600[diff] [blame^]254 PMUX_DRVGRP_COUNT,
Tom Warrenb7ea6d12014-01-24 12:46:13 -0700[diff] [blame]255};
256
257/*
258 * Functions which can be assigned to each of the pin groups. The values here
259 * bear no relation to the values programmed into pinmux registers and are
260 * purely a convenience. The translation is done through a table search.
261 */
262enum pmux_func {
263 PMUX_FUNC_AHB_CLK,
264 PMUX_FUNC_APB_CLK,
265 PMUX_FUNC_AUDIO_SYNC,
266 PMUX_FUNC_CRT,
267 PMUX_FUNC_DAP1,
268 PMUX_FUNC_DAP2,
269 PMUX_FUNC_DAP3,
270 PMUX_FUNC_DAP4,
271 PMUX_FUNC_DAP5,
272 PMUX_FUNC_DISPA,
273 PMUX_FUNC_DISPB,
274 PMUX_FUNC_EMC_TEST0_DLL,
275 PMUX_FUNC_EMC_TEST1_DLL,
276 PMUX_FUNC_GMI,
277 PMUX_FUNC_GMI_INT,
278 PMUX_FUNC_HDMI,
279 PMUX_FUNC_I2C1,
280 PMUX_FUNC_I2C2,
281 PMUX_FUNC_I2C3,
282 PMUX_FUNC_IDE,
283 PMUX_FUNC_KBC,
284 PMUX_FUNC_MIO,
285 PMUX_FUNC_MIPI_HS,
286 PMUX_FUNC_NAND,
287 PMUX_FUNC_OSC,
288 PMUX_FUNC_OWR,
289 PMUX_FUNC_PCIE,
290 PMUX_FUNC_PLLA_OUT,
291 PMUX_FUNC_PLLC_OUT1,
292 PMUX_FUNC_PLLM_OUT1,
293 PMUX_FUNC_PLLP_OUT2,
294 PMUX_FUNC_PLLP_OUT3,
295 PMUX_FUNC_PLLP_OUT4,
296 PMUX_FUNC_PWM,
297 PMUX_FUNC_PWR_INTR,
298 PMUX_FUNC_PWR_ON,
299 PMUX_FUNC_RTCK,
300 PMUX_FUNC_SDMMC1,
301 PMUX_FUNC_SDMMC2,
302 PMUX_FUNC_SDMMC3,
303 PMUX_FUNC_SDMMC4,
304 PMUX_FUNC_SFLASH,
305 PMUX_FUNC_SPDIF,
306 PMUX_FUNC_SPI1,
307 PMUX_FUNC_SPI2,
308 PMUX_FUNC_SPI2_ALT,
309 PMUX_FUNC_SPI3,
310 PMUX_FUNC_SPI4,
311 PMUX_FUNC_TRACE,
312 PMUX_FUNC_TWC,
313 PMUX_FUNC_UARTA,
314 PMUX_FUNC_UARTB,
315 PMUX_FUNC_UARTC,
316 PMUX_FUNC_UARTD,
317 PMUX_FUNC_UARTE,
318 PMUX_FUNC_ULPI,
319 PMUX_FUNC_VI,
320 PMUX_FUNC_VI_SENSOR_CLK,
321 PMUX_FUNC_XIO,
322 /* End of Tegra2 MUX selectors */
323 PMUX_FUNC_BLINK,
324 PMUX_FUNC_CEC,
325 PMUX_FUNC_CLK12,
326 PMUX_FUNC_DAP,
327 PMUX_FUNC_DAPSDMMC2,
328 PMUX_FUNC_DDR,
329 PMUX_FUNC_DEV3,
330 PMUX_FUNC_DTV,
331 PMUX_FUNC_VI_ALT1,
332 PMUX_FUNC_VI_ALT2,
333 PMUX_FUNC_VI_ALT3,
334 PMUX_FUNC_EMC_DLL,
335 PMUX_FUNC_EXTPERIPH1,
336 PMUX_FUNC_EXTPERIPH2,
337 PMUX_FUNC_EXTPERIPH3,
338 PMUX_FUNC_GMI_ALT,
339 PMUX_FUNC_HDA,
340 PMUX_FUNC_HSI,
341 PMUX_FUNC_I2C4,
342 PMUX_FUNC_I2C5,
343 PMUX_FUNC_I2CPWR,
344 PMUX_FUNC_I2S0,
345 PMUX_FUNC_I2S1,
346 PMUX_FUNC_I2S2,
347 PMUX_FUNC_I2S3,
348 PMUX_FUNC_I2S4,
349 PMUX_FUNC_NAND_ALT,
350 PMUX_FUNC_POPSDIO4,
351 PMUX_FUNC_POPSDMMC4,
352 PMUX_FUNC_PWM0,
353 PMUX_FUNC_PWM1,
354 PMUX_FUNC_PWM2,
355 PMUX_FUNC_PWM3,
356 PMUX_FUNC_SATA,
357 PMUX_FUNC_SPI5,
358 PMUX_FUNC_SPI6,
359 PMUX_FUNC_SYSCLK,
360 PMUX_FUNC_VGP1,
361 PMUX_FUNC_VGP2,
362 PMUX_FUNC_VGP3,
363 PMUX_FUNC_VGP4,
364 PMUX_FUNC_VGP5,
365 PMUX_FUNC_VGP6,
366 /* End of Tegra3 MUX selectors */
367 PMUX_FUNC_USB,
368 PMUX_FUNC_SOC,
369 PMUX_FUNC_CPU,
370 PMUX_FUNC_CLK,
371 PMUX_FUNC_PWRON,
372 PMUX_FUNC_PMI,
373 PMUX_FUNC_CLDVFS,
374 PMUX_FUNC_RESET_OUT_N,
375 /* End of Tegra114 MUX selectors */
376
Stephen Warren9026dfd2014-03-21 12:28:54 -0600[diff] [blame]377 PMUX_FUNC_COUNT,
Tom Warrenb7ea6d12014-01-24 12:46:13 -0700[diff] [blame]378
379 PMUX_FUNC_INVALID = 0x4000,
380 PMUX_FUNC_RSVD1 = 0x8000,
381 PMUX_FUNC_RSVD2 = 0x8001,
382 PMUX_FUNC_RSVD3 = 0x8002,
383 PMUX_FUNC_RSVD4 = 0x8003,
384};
385
Stephen Warren9026dfd2014-03-21 12:28:54 -0600[diff] [blame]386#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC
387#define TEGRA_PMX_HAS_RCV_SEL
Stephen Warrenf4df6052014-03-21 12:28:56 -0600[diff] [blame^]388#define TEGRA_PMX_HAS_DRVGRPS
Stephen Warren9026dfd2014-03-21 12:28:54 -0600[diff] [blame]389#include <asm/arch-tegra/pinmux.h>
Tom Warrenb7ea6d12014-01-24 12:46:13 -0700[diff] [blame]390
Stephen Warren9026dfd2014-03-21 12:28:54 -0600[diff] [blame]391#endif /* _TEGRA124_PINMUX_H_ */