blob: 7810cf22d4ea2e268d36434a7cbca8ec33b810a1 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Lei Wen20014762011-02-09 18:06:58 +05302/*
3 * (C) Copyright 2011
4 * Marvell Semiconductor <www.marvell.com>
5 * Written-by: Lei Wen <leiwen@marvell.com>
Lei Wen20014762011-02-09 18:06:58 +05306 */
7
8/*
9 * This file should be included in board config header file.
10 *
11 * It supports common definitions for Kirkwood platform
12 */
13
14#ifndef _KW_CONFIG_H
15#define _KW_CONFIG_H
16
17#if defined (CONFIG_KW88F6281)
18#include <asm/arch/kw88f6281.h>
19#elif defined (CONFIG_KW88F6192)
20#include <asm/arch/kw88f6192.h>
21#else
22#error "SOC Name not defined"
23#endif /* CONFIG_KW88F6281 */
24
Stefan Roesec2437842014-10-22 12:13:06 +020025#include <asm/arch/soc.h>
Lei Wen20014762011-02-09 18:06:58 +053026#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
27#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
28#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */
29
Lei Wen20014762011-02-09 18:06:58 +053030/* Kirkwood has 2k of Security SRAM, use it for SP */
31#define CONFIG_SYS_INIT_SP_ADDR 0xC8012000
Lei Wen20014762011-02-09 18:06:58 +053032
Paul Kocialkowski2fae3e72015-04-10 23:09:51 +020033#define CONFIG_I2C_MVTWSI_BASE0 KW_TWSI_BASE
Lei Wen20014762011-02-09 18:06:58 +053034#define MV_UART_CONSOLE_BASE KW_UART0_BASE
35#define MV_SATA_BASE KW_SATA_BASE
36#define MV_SATA_PORT0_OFFSET KW_SATA_PORT0_OFFSET
37#define MV_SATA_PORT1_OFFSET KW_SATA_PORT1_OFFSET
38
39/*
40 * NAND configuration
41 */
42#ifdef CONFIG_CMD_NAND
43#define CONFIG_NAND_KIRKWOOD
44#define CONFIG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */
45#define NAND_ALLOW_ERASE_ALL 1
46#endif
47
48/*
Lei Wen20014762011-02-09 18:06:58 +053049 * IDE Support on SATA ports
50 */
Simon Glassb569a012017-05-17 03:25:30 -060051#ifdef CONFIG_IDE
Lei Wen20014762011-02-09 18:06:58 +053052#define __io
Lei Wen20014762011-02-09 18:06:58 +053053/* Data, registers and alternate blocks are at the same offset */
Lei Wen20014762011-02-09 18:06:58 +053054/* Each 8-bit ATA register is aligned to a 4-bytes address */
Lei Wen20014762011-02-09 18:06:58 +053055/* Controller supports 48-bits LBA addressing */
56#define CONFIG_LBA48
Simon Glassb569a012017-05-17 03:25:30 -060057/* CONFIG_IDE requires some #defines for ATA registers */
Lei Wen20014762011-02-09 18:06:58 +053058/* ATA registers base is at SATA controller base */
Simon Glassb569a012017-05-17 03:25:30 -060059#endif /* CONFIG_IDE */
Lei Wen20014762011-02-09 18:06:58 +053060
Stefan Roese64174892015-10-22 12:36:31 +020061/* Use common timer */
62#define CONFIG_SYS_TIMER_COUNTS_DOWN
63#define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14)
64#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_TCLK
65
Lei Wen20014762011-02-09 18:06:58 +053066#endif /* _KW_CONFIG_H */