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git01.mediatek.com / filogic / uboot / 64174890b7aad8148f3d077a8181c54012dd428c / . / arch / arm / mach-kirkwood / include / mach / config.h
blob: 0c4309ff0078aea57302f0784d9c549f29ec3446 [file] [log] [blame]
Lei Wen20014762011-02-09 18:06:58 +0530[diff] [blame]1/*
2 * (C) Copyright 2011
3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Lei Wen <leiwen@marvell.com>
5 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]6 * SPDX-License-Identifier: GPL-2.0+
Lei Wen20014762011-02-09 18:06:58 +0530[diff] [blame]7 */
8
9/*
10 * This file should be included in board config header file.
11 *
12 * It supports common definitions for Kirkwood platform
13 */
14
15#ifndef _KW_CONFIG_H
16#define _KW_CONFIG_H
17
18#if defined (CONFIG_KW88F6281)
19#include <asm/arch/kw88f6281.h>
20#elif defined (CONFIG_KW88F6192)
21#include <asm/arch/kw88f6192.h>
22#else
23#error "SOC Name not defined"
24#endif /* CONFIG_KW88F6281 */
25
Stefan Roesec2437842014-10-22 12:13:06 +0200[diff] [blame]26#include <asm/arch/soc.h>
Michael Walle5b519822011-10-31 20:22:58 +0530[diff] [blame]27#define CONFIG_SYS_CACHELINE_SIZE 32
28 /* default Dcache Line length for kirkwood */
Lei Wen20014762011-02-09 18:06:58 +0530[diff] [blame]29#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
30#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
31#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
32#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */
33
34/*
35 * By default kwbimage.cfg from board specific folder is used
36 * If for some board, different configuration file need to be used,
37 * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
38 */
39#ifndef CONFIG_SYS_KWD_CONFIG
Masahiro Yamadad6acdf22014-03-11 11:05:17 +0900[diff] [blame]40#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg
Lei Wen20014762011-02-09 18:06:58 +0530[diff] [blame]41#endif /* CONFIG_SYS_KWD_CONFIG */
42
43/* Kirkwood has 2k of Security SRAM, use it for SP */
44#define CONFIG_SYS_INIT_SP_ADDR 0xC8012000
45#define CONFIG_NR_DRAM_BANKS_MAX 2
46
Paul Kocialkowski2fae3e72015-04-10 23:09:51 +0200[diff] [blame]47#define CONFIG_I2C_MVTWSI_BASE0 KW_TWSI_BASE
Lei Wen20014762011-02-09 18:06:58 +0530[diff] [blame]48#define MV_UART_CONSOLE_BASE KW_UART0_BASE
49#define MV_SATA_BASE KW_SATA_BASE
50#define MV_SATA_PORT0_OFFSET KW_SATA_PORT0_OFFSET
51#define MV_SATA_PORT1_OFFSET KW_SATA_PORT1_OFFSET
52
53/*
54 * NAND configuration
55 */
56#ifdef CONFIG_CMD_NAND
57#define CONFIG_NAND_KIRKWOOD
58#define CONFIG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */
59#define NAND_ALLOW_ERASE_ALL 1
60#endif
61
62/*
63 * SPI Flash configuration
64 */
65#ifdef CONFIG_CMD_SF
66#define CONFIG_HARD_SPI 1
67#define CONFIG_KIRKWOOD_SPI 1
Valentin Longchampb69ee002012-06-13 03:03:52 +0000[diff] [blame]68#ifndef CONFIG_ENV_SPI_BUS
69# define CONFIG_ENV_SPI_BUS 0
70#endif
71#ifndef CONFIG_ENV_SPI_CS
72# define CONFIG_ENV_SPI_CS 0
73#endif
74#ifndef CONFIG_ENV_SPI_MAX_HZ
75# define CONFIG_ENV_SPI_MAX_HZ 50000000
76#endif
Lei Wen20014762011-02-09 18:06:58 +0530[diff] [blame]77#endif
78
79/*
80 * Ethernet Driver configuration
81 */
82#ifdef CONFIG_CMD_NET
83#define CONFIG_CMD_MII
84#define CONFIG_NETCONSOLE /* include NetConsole support */
Lei Wen20014762011-02-09 18:06:58 +0530[diff] [blame]85#define CONFIG_MII /* expose smi ove miiphy interface */
86#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */
87#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
88#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
89#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
90#endif /* CONFIG_CMD_NET */
91
92/*
93 * USB/EHCI
94 */
95#ifdef CONFIG_CMD_USB
Albert ARIBAUDa31f2f52012-02-06 20:39:29 +0530[diff] [blame]96#define CONFIG_USB_EHCI_MARVELL
Lei Wen20014762011-02-09 18:06:58 +0530[diff] [blame]97#define CONFIG_EHCI_IS_TDI
98#endif /* CONFIG_CMD_USB */
99
100/*
101 * IDE Support on SATA ports
102 */
103#ifdef CONFIG_CMD_IDE
104#define __io
105#define CONFIG_CMD_EXT2
106#define CONFIG_MVSATA_IDE
107#define CONFIG_IDE_PREINIT
108#define CONFIG_MVSATA_IDE_USE_PORT1
109/* Needs byte-swapping for ATA data register */
110#define CONFIG_IDE_SWAP_IO
111/* Data, registers and alternate blocks are at the same offset */
112#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100)
113#define CONFIG_SYS_ATA_REG_OFFSET (0x0100)
114#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100)
115/* Each 8-bit ATA register is aligned to a 4-bytes address */
116#define CONFIG_SYS_ATA_STRIDE 4
117/* Controller supports 48-bits LBA addressing */
118#define CONFIG_LBA48
119/* CONFIG_CMD_IDE requires some #defines for ATA registers */
120#define CONFIG_SYS_IDE_MAXBUS 2
121#define CONFIG_SYS_IDE_MAXDEVICE 2
122/* ATA registers base is at SATA controller base */
123#define CONFIG_SYS_ATA_BASE_ADDR MV_SATA_BASE
124#endif /* CONFIG_CMD_IDE */
125
126/*
127 * I2C related stuff
128 */
129#ifdef CONFIG_CMD_I2C
Heiko Schocher479a4cf2013-01-29 08:53:15 +0100[diff] [blame]130#ifndef CONFIG_SYS_I2C_SOFT
Hans de Goede9830f1c2014-06-13 22:55:48 +0200[diff] [blame]131#define CONFIG_SYS_I2C
132#define CONFIG_SYS_I2C_MVTWSI
Holger Brunckf3f93d22011-06-16 18:11:15 +0530[diff] [blame]133#endif
Lei Wen20014762011-02-09 18:06:58 +0530[diff] [blame]134#define CONFIG_SYS_I2C_SLAVE 0x0
135#define CONFIG_SYS_I2C_SPEED 100000
136#endif
137
Stefan Roese64174892015-10-22 12:36:31 +0200[diff] [blame^]138/* Use common timer */
139#define CONFIG_SYS_TIMER_COUNTS_DOWN
140#define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14)
141#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_TCLK
142
Lei Wen20014762011-02-09 18:06:58 +0530[diff] [blame]143#endif /* _KW_CONFIG_H */