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git01.mediatek.com / filogic / uboot / d942f97328083f42d1f86cb75a5a5304ae36ee2a / . / arch / arm / dts / k3-am642-sk-u-boot.dtsi
blob: ea200a1ee1c6490075955940387c94216b5c8301 [file] [log] [blame]
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
Neha Malcom Francis9a1b2712023-07-22 00:14:34 +0530[diff] [blame]6#include "k3-am64x-binman.dtsi"
7
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]8/ {
9 chosen {
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame]10 tick-timer = &main_timer0;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]11 };
Aswath Govindrajua15380e2021-07-26 20:58:03 +0530[diff] [blame]12
Georgi Vlaevd4d0db12022-05-20 15:30:26 +0300[diff] [blame]13 memory@80000000 {
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]14 bootph-all;
Georgi Vlaevd4d0db12022-05-20 15:30:26 +0300[diff] [blame]15 };
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]16};
17
18&cbass_main{
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]19 bootph-all;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]20};
21
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame]22&main_timer0 {
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]23 bootph-all;
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame]24 clock-frequency = <200000000>;
25};
26
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]27&main_conf {
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]28 bootph-all;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]29 chipid@14 {
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]30 bootph-all;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]31 };
32};
33
34&main_pmx0 {
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]35 bootph-all;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]36};
37
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame]38&main_i2c0_pins_default {
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]39 bootph-all;
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame]40};
41
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]42&main_i2c0 {
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]43 bootph-all;
Roger Quadrosaf6e2a72023-08-05 11:14:40 +0300[diff] [blame]44};
45
46&main_uart0_pins_default {
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]47 bootph-all;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]48};
49
50&main_uart0 {
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]51 bootph-all;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]52};
53
54&dmss {
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]55 bootph-all;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]56};
57
58&secure_proxy_main {
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]59 bootph-all;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]60};
61
62&dmsc {
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]63 bootph-all;
Suman Anna91eda102021-05-13 20:10:57 -0500[diff] [blame]64 k3_sysreset: sysreset-controller {
65 compatible = "ti,sci-sysreset";
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]66 bootph-all;
Suman Anna91eda102021-05-13 20:10:57 -0500[diff] [blame]67 };
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]68};
69
70&k3_pds {
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]71 bootph-all;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]72};
73
74&k3_clks {
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]75 bootph-all;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]76};
77
78&k3_reset {
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]79 bootph-all;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]80};
81
82&sdhci0 {
Aswath Govindrajua15380e2021-07-26 20:58:03 +0530[diff] [blame]83 status = "disabled";
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]84 bootph-all;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]85};
86
87&sdhci1 {
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]88 bootph-all;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]89};
90
91&main_mmc1_pins_default {
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]92 bootph-all;
Lokesh Vutla3d10ca82021-05-06 16:44:59 +0530[diff] [blame]93};
Vignesh Raghavendrac23d7f32021-05-10 20:06:13 +0530[diff] [blame]94
Roger Quadrosc9b17ae2023-09-29 16:46:44 +0300[diff] [blame]95&inta_main_dmss {
96 bootph-all;
97};
98
Roger Quadrosc9b17ae2023-09-29 16:46:44 +0300[diff] [blame]99&mdio1_pins_default {
100 bootph-all;
101};
102
103&cpsw3g_mdio {
104 bootph-all;
105};
106
107&cpsw3g_phy0 {
108 bootph-all;
109};
110
111&cpsw3g_phy1 {
112 bootph-all;
113};
114
115&rgmii1_pins_default {
116 bootph-all;
117};
118
119&rgmii2_pins_default {
120 bootph-all;
121};
122
Vignesh Raghavendrac23d7f32021-05-10 20:06:13 +0530[diff] [blame]123&cpsw3g {
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]124 bootph-all;
Vignesh Raghavendrac23d7f32021-05-10 20:06:13 +0530[diff] [blame]125
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]126 ethernet-ports {
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]127 bootph-all;
Vignesh Raghavendrac23d7f32021-05-10 20:06:13 +0530[diff] [blame]128 };
129};
130
Roger Quadrosc9b17ae2023-09-29 16:46:44 +0300[diff] [blame]131&phy_gmii_sel {
132 bootph-all;
133};
134
Vignesh Raghavendrac23d7f32021-05-10 20:06:13 +0530[diff] [blame]135&cpsw_port2 {
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]136 bootph-all;
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]137};
138
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]139&main_bcdma {
Siddharth Vadapallie4f41ae2023-10-28 20:36:03 +0300[diff] [blame]140 reg = <0x00 0x485c0100 0x00 0x100>,
141 <0x00 0x4c000000 0x00 0x20000>,
142 <0x00 0x4a820000 0x00 0x20000>,
143 <0x00 0x4aa40000 0x00 0x20000>,
144 <0x00 0x4bc00000 0x00 0x100000>,
145 <0x00 0x48600000 0x00 0x8000>,
146 <0x00 0x484a4000 0x00 0x2000>,
147 <0x00 0x484c2000 0x00 0x2000>;
148 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt",
149 "cfg", "tchan", "rchan";
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]150 bootph-all;
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]151};
152
153&main_pktdma {
Siddharth Vadapallie4f41ae2023-10-28 20:36:03 +0300[diff] [blame]154 reg = <0x00 0x485c0000 0x00 0x100>,
155 <0x00 0x4a800000 0x00 0x20000>,
156 <0x00 0x4aa00000 0x00 0x40000>,
157 <0x00 0x4b800000 0x00 0x400000>,
158 <0x00 0x485e0000 0x00 0x20000>,
159 <0x00 0x484a0000 0x00 0x4000>,
160 <0x00 0x484c0000 0x00 0x2000>,
161 <0x00 0x48430000 0x00 0x4000>;
162 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", "cfg",
163 "tchan", "rchan", "rflow";
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]164 bootph-all;
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]165};
166
167&rgmii1_pins_default {
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]168 bootph-all;
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]169};
170
171&rgmii2_pins_default {
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]172 bootph-all;
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]173};
174
175&mdio1_pins_default {
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]176 bootph-all;
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]177};
178
Vignesh Raghavendra14953582021-12-24 12:55:35 +0530[diff] [blame]179&cpsw3g_phy1 {
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]180 bootph-all;
Vignesh Raghavendrac23d7f32021-05-10 20:06:13 +0530[diff] [blame]181};
Kishon Vijay Abraham I35c392c2021-10-20 21:09:12 +0530[diff] [blame]182
183&main_usb0_pins_default {
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]184 bootph-all;
Kishon Vijay Abraham I35c392c2021-10-20 21:09:12 +0530[diff] [blame]185};
186
Roger Quadros672caea2024-01-31 15:33:48 +0200[diff] [blame]187&serdes_ln_ctrl {
188 bootph-all;
189};
190
Kishon Vijay Abraham I35c392c2021-10-20 21:09:12 +0530[diff] [blame]191&usbss0 {
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]192 bootph-all;
Kishon Vijay Abraham I35c392c2021-10-20 21:09:12 +0530[diff] [blame]193};
194
195&usb0 {
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]196 bootph-all;
Kishon Vijay Abraham I35c392c2021-10-20 21:09:12 +0530[diff] [blame]197};
198
199&serdes_wiz0 {
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]200 bootph-all;
Kishon Vijay Abraham I35c392c2021-10-20 21:09:12 +0530[diff] [blame]201};
202
203&serdes0_usb_link {
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]204 bootph-all;
Kishon Vijay Abraham I35c392c2021-10-20 21:09:12 +0530[diff] [blame]205};
206
207&serdes0 {
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]208 bootph-all;
Kishon Vijay Abraham I35c392c2021-10-20 21:09:12 +0530[diff] [blame]209};
210
211&serdes_refclk {
Roger Quadrose58cbb42023-09-29 16:46:43 +0300[diff] [blame]212 bootph-all;
Kishon Vijay Abraham I35c392c2021-10-20 21:09:12 +0530[diff] [blame]213};