Jason Liu | dec1112 | 2011-11-25 00:18:02 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2007 |
| 3 | * Sascha Hauer, Pengutronix |
| 4 | * |
| 5 | * (C) Copyright 2009 Freescale Semiconductor, Inc. |
| 6 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 7 | * SPDX-License-Identifier: GPL-2.0+ |
Jason Liu | dec1112 | 2011-11-25 00:18:02 +0000 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #include <common.h> |
Fabio Estevam | 1340929 | 2014-01-29 17:39:49 -0200 | [diff] [blame] | 11 | #include <asm/armv7.h> |
Jeroen Hofstee | 1abf3a1 | 2014-10-08 22:57:52 +0200 | [diff] [blame] | 12 | #include <asm/bootm.h> |
Fabio Estevam | 1340929 | 2014-01-29 17:39:49 -0200 | [diff] [blame] | 13 | #include <asm/pl310.h> |
Jason Liu | dec1112 | 2011-11-25 00:18:02 +0000 | [diff] [blame] | 14 | #include <asm/errno.h> |
| 15 | #include <asm/io.h> |
| 16 | #include <asm/arch/imx-regs.h> |
| 17 | #include <asm/arch/clock.h> |
| 18 | #include <asm/arch/sys_proto.h> |
Troy Kisky | 0ca618c | 2012-08-15 10:31:20 +0000 | [diff] [blame] | 19 | #include <asm/imx-common/boot_mode.h> |
Stefan Roese | 8338d1d | 2013-04-15 21:14:12 +0000 | [diff] [blame] | 20 | #include <asm/imx-common/dma.h> |
Fabio Estevam | 48e65b0 | 2013-02-07 06:45:23 +0000 | [diff] [blame] | 21 | #include <stdbool.h> |
Pardeep Kumar Singla | c1fa130 | 2013-07-25 12:12:13 -0500 | [diff] [blame] | 22 | #include <asm/arch/mxc_hdmi.h> |
| 23 | #include <asm/arch/crm_regs.h> |
Eric Nelson | 357a4e4 | 2014-09-30 15:40:02 -0700 | [diff] [blame] | 24 | #include <asm/bootm.h> |
Ye.Li | f19692c | 2014-11-20 21:14:14 +0800 | [diff] [blame] | 25 | #include <dm.h> |
| 26 | #include <imx_thermal.h> |
Jason Liu | dec1112 | 2011-11-25 00:18:02 +0000 | [diff] [blame] | 27 | |
Fabio Estevam | a47ec52 | 2013-12-26 14:51:33 -0200 | [diff] [blame] | 28 | enum ldo_reg { |
| 29 | LDO_ARM, |
| 30 | LDO_SOC, |
| 31 | LDO_PU, |
| 32 | }; |
| 33 | |
Troy Kisky | 5839493 | 2012-10-23 10:57:46 +0000 | [diff] [blame] | 34 | struct scu_regs { |
| 35 | u32 ctrl; |
| 36 | u32 config; |
| 37 | u32 status; |
| 38 | u32 invalidate; |
| 39 | u32 fpga_rev; |
| 40 | }; |
| 41 | |
Ye.Li | f19692c | 2014-11-20 21:14:14 +0800 | [diff] [blame] | 42 | #if defined(CONFIG_IMX6_THERMAL) |
| 43 | static const struct imx_thermal_plat imx6_thermal_plat = { |
| 44 | .regs = (void *)ANATOP_BASE_ADDR, |
| 45 | .fuse_bank = 1, |
| 46 | .fuse_word = 6, |
| 47 | }; |
| 48 | |
| 49 | U_BOOT_DEVICE(imx6_thermal) = { |
| 50 | .name = "imx_thermal", |
| 51 | .platdata = &imx6_thermal_plat, |
| 52 | }; |
| 53 | #endif |
| 54 | |
Gabriel Huau | 170ceaf | 2014-07-26 11:35:43 -0700 | [diff] [blame] | 55 | u32 get_nr_cpus(void) |
| 56 | { |
| 57 | struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR; |
| 58 | return readl(&scu->config) & 3; |
| 59 | } |
| 60 | |
Jason Liu | dec1112 | 2011-11-25 00:18:02 +0000 | [diff] [blame] | 61 | u32 get_cpu_rev(void) |
| 62 | { |
Fabio Estevam | 46e9733 | 2012-03-20 04:21:45 +0000 | [diff] [blame] | 63 | struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; |
Troy Kisky | 5839493 | 2012-10-23 10:57:46 +0000 | [diff] [blame] | 64 | u32 reg = readl(&anatop->digprog_sololite); |
| 65 | u32 type = ((reg >> 16) & 0xff); |
Fabio Estevam | 46e9733 | 2012-03-20 04:21:45 +0000 | [diff] [blame] | 66 | |
Troy Kisky | 5839493 | 2012-10-23 10:57:46 +0000 | [diff] [blame] | 67 | if (type != MXC_CPU_MX6SL) { |
| 68 | reg = readl(&anatop->digprog); |
Fabio Estevam | f3d5a2c | 2014-01-26 15:06:41 -0200 | [diff] [blame] | 69 | struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR; |
| 70 | u32 cfg = readl(&scu->config) & 3; |
Troy Kisky | 5839493 | 2012-10-23 10:57:46 +0000 | [diff] [blame] | 71 | type = ((reg >> 16) & 0xff); |
| 72 | if (type == MXC_CPU_MX6DL) { |
Troy Kisky | 5839493 | 2012-10-23 10:57:46 +0000 | [diff] [blame] | 73 | if (!cfg) |
| 74 | type = MXC_CPU_MX6SOLO; |
| 75 | } |
Fabio Estevam | f3d5a2c | 2014-01-26 15:06:41 -0200 | [diff] [blame] | 76 | |
| 77 | if (type == MXC_CPU_MX6Q) { |
| 78 | if (cfg == 1) |
| 79 | type = MXC_CPU_MX6D; |
| 80 | } |
| 81 | |
Troy Kisky | 5839493 | 2012-10-23 10:57:46 +0000 | [diff] [blame] | 82 | } |
| 83 | reg &= 0xff; /* mx6 silicon revision */ |
| 84 | return (type << 12) | (reg + 0x10); |
Jason Liu | dec1112 | 2011-11-25 00:18:02 +0000 | [diff] [blame] | 85 | } |
| 86 | |
Fabio Estevam | 435998b | 2013-03-27 07:36:55 +0000 | [diff] [blame] | 87 | #ifdef CONFIG_REVISION_TAG |
| 88 | u32 __weak get_board_rev(void) |
| 89 | { |
| 90 | u32 cpurev = get_cpu_rev(); |
| 91 | u32 type = ((cpurev >> 12) & 0xff); |
| 92 | if (type == MXC_CPU_MX6SOLO) |
| 93 | cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF); |
| 94 | |
Fabio Estevam | f3d5a2c | 2014-01-26 15:06:41 -0200 | [diff] [blame] | 95 | if (type == MXC_CPU_MX6D) |
| 96 | cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF); |
| 97 | |
Fabio Estevam | 435998b | 2013-03-27 07:36:55 +0000 | [diff] [blame] | 98 | return cpurev; |
| 99 | } |
| 100 | #endif |
| 101 | |
Jason Liu | dec1112 | 2011-11-25 00:18:02 +0000 | [diff] [blame] | 102 | void init_aips(void) |
| 103 | { |
Jason Liu | bb25e07 | 2012-01-10 00:52:59 +0000 | [diff] [blame] | 104 | struct aipstz_regs *aips1, *aips2; |
Fabio Estevam | 712ab88 | 2014-06-24 17:40:58 -0300 | [diff] [blame] | 105 | #ifdef CONFIG_MX6SX |
| 106 | struct aipstz_regs *aips3; |
| 107 | #endif |
Jason Liu | bb25e07 | 2012-01-10 00:52:59 +0000 | [diff] [blame] | 108 | |
| 109 | aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR; |
| 110 | aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR; |
Fabio Estevam | 712ab88 | 2014-06-24 17:40:58 -0300 | [diff] [blame] | 111 | #ifdef CONFIG_MX6SX |
| 112 | aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR; |
| 113 | #endif |
Jason Liu | dec1112 | 2011-11-25 00:18:02 +0000 | [diff] [blame] | 114 | |
| 115 | /* |
| 116 | * Set all MPROTx to be non-bufferable, trusted for R/W, |
| 117 | * not forced to user-mode. |
| 118 | */ |
Jason Liu | bb25e07 | 2012-01-10 00:52:59 +0000 | [diff] [blame] | 119 | writel(0x77777777, &aips1->mprot0); |
| 120 | writel(0x77777777, &aips1->mprot1); |
| 121 | writel(0x77777777, &aips2->mprot0); |
| 122 | writel(0x77777777, &aips2->mprot1); |
Jason Liu | dec1112 | 2011-11-25 00:18:02 +0000 | [diff] [blame] | 123 | |
Jason Liu | bb25e07 | 2012-01-10 00:52:59 +0000 | [diff] [blame] | 124 | /* |
| 125 | * Set all OPACRx to be non-bufferable, not require |
| 126 | * supervisor privilege level for access,allow for |
| 127 | * write access and untrusted master access. |
| 128 | */ |
| 129 | writel(0x00000000, &aips1->opacr0); |
| 130 | writel(0x00000000, &aips1->opacr1); |
| 131 | writel(0x00000000, &aips1->opacr2); |
| 132 | writel(0x00000000, &aips1->opacr3); |
| 133 | writel(0x00000000, &aips1->opacr4); |
| 134 | writel(0x00000000, &aips2->opacr0); |
| 135 | writel(0x00000000, &aips2->opacr1); |
| 136 | writel(0x00000000, &aips2->opacr2); |
| 137 | writel(0x00000000, &aips2->opacr3); |
| 138 | writel(0x00000000, &aips2->opacr4); |
Fabio Estevam | 712ab88 | 2014-06-24 17:40:58 -0300 | [diff] [blame] | 139 | |
| 140 | #ifdef CONFIG_MX6SX |
| 141 | /* |
| 142 | * Set all MPROTx to be non-bufferable, trusted for R/W, |
| 143 | * not forced to user-mode. |
| 144 | */ |
| 145 | writel(0x77777777, &aips3->mprot0); |
| 146 | writel(0x77777777, &aips3->mprot1); |
| 147 | |
| 148 | /* |
| 149 | * Set all OPACRx to be non-bufferable, not require |
| 150 | * supervisor privilege level for access,allow for |
| 151 | * write access and untrusted master access. |
| 152 | */ |
| 153 | writel(0x00000000, &aips3->opacr0); |
| 154 | writel(0x00000000, &aips3->opacr1); |
| 155 | writel(0x00000000, &aips3->opacr2); |
| 156 | writel(0x00000000, &aips3->opacr3); |
| 157 | writel(0x00000000, &aips3->opacr4); |
| 158 | #endif |
Jason Liu | dec1112 | 2011-11-25 00:18:02 +0000 | [diff] [blame] | 159 | } |
| 160 | |
Fabio Estevam | cf621ff | 2013-12-26 14:51:31 -0200 | [diff] [blame] | 161 | static void clear_ldo_ramp(void) |
| 162 | { |
| 163 | struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; |
| 164 | int reg; |
| 165 | |
| 166 | /* ROM may modify LDO ramp up time according to fuse setting, so in |
| 167 | * order to be in the safe side we neeed to reset these settings to |
| 168 | * match the reset value: 0'b00 |
| 169 | */ |
| 170 | reg = readl(&anatop->ana_misc2); |
| 171 | reg &= ~(0x3f << 24); |
| 172 | writel(reg, &anatop->ana_misc2); |
| 173 | } |
| 174 | |
Dirk Behme | 8c46594 | 2012-05-02 02:12:17 +0000 | [diff] [blame] | 175 | /* |
Fabio Estevam | 2e95fe1 | 2014-06-13 01:42:37 -0300 | [diff] [blame] | 176 | * Set the PMU_REG_CORE register |
Dirk Behme | 8c46594 | 2012-05-02 02:12:17 +0000 | [diff] [blame] | 177 | * |
Fabio Estevam | 2e95fe1 | 2014-06-13 01:42:37 -0300 | [diff] [blame] | 178 | * Set LDO_SOC/PU/ARM regulators to the specified millivolt level. |
Dirk Behme | 8c46594 | 2012-05-02 02:12:17 +0000 | [diff] [blame] | 179 | * Possible values are from 0.725V to 1.450V in steps of |
| 180 | * 0.025V (25mV). |
| 181 | */ |
Fabio Estevam | a47ec52 | 2013-12-26 14:51:33 -0200 | [diff] [blame] | 182 | static int set_ldo_voltage(enum ldo_reg ldo, u32 mv) |
Dirk Behme | 8c46594 | 2012-05-02 02:12:17 +0000 | [diff] [blame] | 183 | { |
| 184 | struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; |
Fabio Estevam | 99b370b | 2013-12-26 14:51:34 -0200 | [diff] [blame] | 185 | u32 val, step, old, reg = readl(&anatop->reg_core); |
Fabio Estevam | a47ec52 | 2013-12-26 14:51:33 -0200 | [diff] [blame] | 186 | u8 shift; |
Dirk Behme | 8c46594 | 2012-05-02 02:12:17 +0000 | [diff] [blame] | 187 | |
| 188 | if (mv < 725) |
| 189 | val = 0x00; /* Power gated off */ |
| 190 | else if (mv > 1450) |
| 191 | val = 0x1F; /* Power FET switched full on. No regulation */ |
| 192 | else |
| 193 | val = (mv - 700) / 25; |
| 194 | |
Fabio Estevam | cf621ff | 2013-12-26 14:51:31 -0200 | [diff] [blame] | 195 | clear_ldo_ramp(); |
| 196 | |
Fabio Estevam | a47ec52 | 2013-12-26 14:51:33 -0200 | [diff] [blame] | 197 | switch (ldo) { |
| 198 | case LDO_SOC: |
| 199 | shift = 18; |
| 200 | break; |
| 201 | case LDO_PU: |
| 202 | shift = 9; |
| 203 | break; |
| 204 | case LDO_ARM: |
| 205 | shift = 0; |
| 206 | break; |
| 207 | default: |
| 208 | return -EINVAL; |
| 209 | } |
| 210 | |
Fabio Estevam | 99b370b | 2013-12-26 14:51:34 -0200 | [diff] [blame] | 211 | old = (reg & (0x1F << shift)) >> shift; |
| 212 | step = abs(val - old); |
| 213 | if (step == 0) |
| 214 | return 0; |
| 215 | |
Fabio Estevam | a47ec52 | 2013-12-26 14:51:33 -0200 | [diff] [blame] | 216 | reg = (reg & ~(0x1F << shift)) | (val << shift); |
Dirk Behme | 8c46594 | 2012-05-02 02:12:17 +0000 | [diff] [blame] | 217 | writel(reg, &anatop->reg_core); |
Fabio Estevam | a47ec52 | 2013-12-26 14:51:33 -0200 | [diff] [blame] | 218 | |
Fabio Estevam | 99b370b | 2013-12-26 14:51:34 -0200 | [diff] [blame] | 219 | /* |
| 220 | * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per |
| 221 | * step |
| 222 | */ |
| 223 | udelay(3 * step); |
| 224 | |
Fabio Estevam | a47ec52 | 2013-12-26 14:51:33 -0200 | [diff] [blame] | 225 | return 0; |
Dirk Behme | 8c46594 | 2012-05-02 02:12:17 +0000 | [diff] [blame] | 226 | } |
| 227 | |
Fabio Estevam | 48e65b0 | 2013-02-07 06:45:23 +0000 | [diff] [blame] | 228 | static void imx_set_wdog_powerdown(bool enable) |
| 229 | { |
| 230 | struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR; |
| 231 | struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR; |
| 232 | |
| 233 | /* Write to the PDE (Power Down Enable) bit */ |
| 234 | writew(enable, &wdog1->wmcr); |
| 235 | writew(enable, &wdog2->wmcr); |
| 236 | } |
| 237 | |
Anson Huang | 05a464f | 2014-01-23 14:00:18 +0800 | [diff] [blame] | 238 | static void set_ahb_rate(u32 val) |
| 239 | { |
| 240 | struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
| 241 | u32 reg, div; |
| 242 | |
| 243 | div = get_periph_clk() / val - 1; |
| 244 | reg = readl(&mxc_ccm->cbcdr); |
| 245 | |
| 246 | writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) | |
| 247 | (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr); |
| 248 | } |
| 249 | |
Anson Huang | 9a149bc | 2014-01-23 14:00:19 +0800 | [diff] [blame] | 250 | static void clear_mmdc_ch_mask(void) |
| 251 | { |
| 252 | struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
| 253 | |
| 254 | /* Clear MMDC channel mask */ |
| 255 | writel(0, &mxc_ccm->ccdr); |
| 256 | } |
| 257 | |
Ye.Li | 622dfbd | 2014-10-30 18:20:58 +0800 | [diff] [blame] | 258 | #ifdef CONFIG_MX6SL |
| 259 | static void set_preclk_from_osc(void) |
| 260 | { |
| 261 | struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
| 262 | u32 reg; |
| 263 | |
| 264 | reg = readl(&mxc_ccm->cscmr1); |
| 265 | reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK; |
| 266 | writel(reg, &mxc_ccm->cscmr1); |
| 267 | } |
| 268 | #endif |
| 269 | |
Jason Liu | dec1112 | 2011-11-25 00:18:02 +0000 | [diff] [blame] | 270 | int arch_cpu_init(void) |
| 271 | { |
| 272 | init_aips(); |
| 273 | |
Anson Huang | 9a149bc | 2014-01-23 14:00:19 +0800 | [diff] [blame] | 274 | /* Need to clear MMDC_CHx_MASK to make warm reset work. */ |
| 275 | clear_mmdc_ch_mask(); |
| 276 | |
Anson Huang | 05a464f | 2014-01-23 14:00:18 +0800 | [diff] [blame] | 277 | /* |
| 278 | * When low freq boot is enabled, ROM will not set AHB |
| 279 | * freq, so we need to ensure AHB freq is 132MHz in such |
| 280 | * scenario. |
| 281 | */ |
| 282 | if (mxc_get_clock(MXC_ARM_CLK) == 396000000) |
| 283 | set_ahb_rate(132000000); |
| 284 | |
Ye.Li | 622dfbd | 2014-10-30 18:20:58 +0800 | [diff] [blame] | 285 | /* Set perclk to source from OSC 24MHz */ |
| 286 | #if defined(CONFIG_MX6SL) |
| 287 | set_preclk_from_osc(); |
| 288 | #endif |
| 289 | |
Fabio Estevam | 48e65b0 | 2013-02-07 06:45:23 +0000 | [diff] [blame] | 290 | imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */ |
Stefan Roese | 8338d1d | 2013-04-15 21:14:12 +0000 | [diff] [blame] | 291 | |
| 292 | #ifdef CONFIG_APBH_DMA |
| 293 | /* Start APBH DMA */ |
| 294 | mxs_dma_init(); |
| 295 | #endif |
| 296 | |
Jason Liu | dec1112 | 2011-11-25 00:18:02 +0000 | [diff] [blame] | 297 | return 0; |
| 298 | } |
Jason Liu | dec1112 | 2011-11-25 00:18:02 +0000 | [diff] [blame] | 299 | |
Fabio Estevam | 99b370b | 2013-12-26 14:51:34 -0200 | [diff] [blame] | 300 | int board_postclk_init(void) |
| 301 | { |
| 302 | set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */ |
| 303 | |
| 304 | return 0; |
| 305 | } |
| 306 | |
Eric Nelson | c94ce4a | 2012-03-04 11:47:38 +0000 | [diff] [blame] | 307 | #ifndef CONFIG_SYS_DCACHE_OFF |
| 308 | void enable_caches(void) |
| 309 | { |
Nitin Garg | b1ce701 | 2014-09-16 13:33:25 -0500 | [diff] [blame] | 310 | #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) |
| 311 | enum dcache_option option = DCACHE_WRITETHROUGH; |
| 312 | #else |
| 313 | enum dcache_option option = DCACHE_WRITEBACK; |
| 314 | #endif |
| 315 | |
Frank Li | 40c4100 | 2013-11-14 00:58:46 +0800 | [diff] [blame] | 316 | /* Avoid random hang when download by usb */ |
| 317 | invalidate_dcache_all(); |
Nitin Garg | b1ce701 | 2014-09-16 13:33:25 -0500 | [diff] [blame] | 318 | |
Eric Nelson | c94ce4a | 2012-03-04 11:47:38 +0000 | [diff] [blame] | 319 | /* Enable D-cache. I-cache is already enabled in start.S */ |
| 320 | dcache_enable(); |
Nitin Garg | b1ce701 | 2014-09-16 13:33:25 -0500 | [diff] [blame] | 321 | |
| 322 | /* Enable caching on OCRAM and ROM */ |
| 323 | mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR, |
| 324 | ROMCP_ARB_END_ADDR, |
| 325 | option); |
| 326 | mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR, |
| 327 | IRAM_SIZE, |
| 328 | option); |
Eric Nelson | c94ce4a | 2012-03-04 11:47:38 +0000 | [diff] [blame] | 329 | } |
| 330 | #endif |
| 331 | |
Jason Liu | dec1112 | 2011-11-25 00:18:02 +0000 | [diff] [blame] | 332 | #if defined(CONFIG_FEC_MXC) |
Fabio Estevam | 04fc128 | 2011-12-20 05:46:31 +0000 | [diff] [blame] | 333 | void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) |
Jason Liu | dec1112 | 2011-11-25 00:18:02 +0000 | [diff] [blame] | 334 | { |
Benoît Thébaudeau | fa7e395 | 2013-04-23 10:17:38 +0000 | [diff] [blame] | 335 | struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; |
| 336 | struct fuse_bank *bank = &ocotp->bank[4]; |
Jason Liu | dec1112 | 2011-11-25 00:18:02 +0000 | [diff] [blame] | 337 | struct fuse_bank4_regs *fuse = |
| 338 | (struct fuse_bank4_regs *)bank->fuse_regs; |
| 339 | |
Jason Liu | bf651aa | 2011-12-19 02:38:13 +0000 | [diff] [blame] | 340 | u32 value = readl(&fuse->mac_addr_high); |
| 341 | mac[0] = (value >> 8); |
| 342 | mac[1] = value ; |
Jason Liu | dec1112 | 2011-11-25 00:18:02 +0000 | [diff] [blame] | 343 | |
Jason Liu | bf651aa | 2011-12-19 02:38:13 +0000 | [diff] [blame] | 344 | value = readl(&fuse->mac_addr_low); |
| 345 | mac[2] = value >> 24 ; |
| 346 | mac[3] = value >> 16 ; |
| 347 | mac[4] = value >> 8 ; |
| 348 | mac[5] = value ; |
Jason Liu | dec1112 | 2011-11-25 00:18:02 +0000 | [diff] [blame] | 349 | |
| 350 | } |
| 351 | #endif |
Troy Kisky | 0ca618c | 2012-08-15 10:31:20 +0000 | [diff] [blame] | 352 | |
| 353 | void boot_mode_apply(unsigned cfg_val) |
| 354 | { |
| 355 | unsigned reg; |
Eric Nelson | 7b8731a | 2012-09-18 15:26:32 +0000 | [diff] [blame] | 356 | struct src *psrc = (struct src *)SRC_BASE_ADDR; |
Troy Kisky | 0ca618c | 2012-08-15 10:31:20 +0000 | [diff] [blame] | 357 | writel(cfg_val, &psrc->gpr9); |
| 358 | reg = readl(&psrc->gpr10); |
| 359 | if (cfg_val) |
| 360 | reg |= 1 << 28; |
| 361 | else |
| 362 | reg &= ~(1 << 28); |
| 363 | writel(reg, &psrc->gpr10); |
| 364 | } |
| 365 | /* |
| 366 | * cfg_val will be used for |
| 367 | * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0] |
Nikita Kiryanov | 9fba842 | 2014-10-29 19:28:33 +0200 | [diff] [blame] | 368 | * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0] |
| 369 | * instead of SBMR1 to determine the boot device. |
Troy Kisky | 0ca618c | 2012-08-15 10:31:20 +0000 | [diff] [blame] | 370 | */ |
| 371 | const struct boot_mode soc_boot_modes[] = { |
| 372 | {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)}, |
| 373 | /* reserved value should start rom usb */ |
| 374 | {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)}, |
| 375 | {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)}, |
Nikolay Dimitrov | 284d901 | 2014-08-10 20:03:07 +0300 | [diff] [blame] | 376 | {"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)}, |
| 377 | {"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)}, |
| 378 | {"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)}, |
| 379 | {"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)}, |
Troy Kisky | 0ca618c | 2012-08-15 10:31:20 +0000 | [diff] [blame] | 380 | /* 4 bit bus width */ |
| 381 | {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)}, |
| 382 | {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, |
| 383 | {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, |
| 384 | {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, |
| 385 | {NULL, 0}, |
| 386 | }; |
Stephen Warren | 57ab23f | 2013-02-26 12:28:29 +0000 | [diff] [blame] | 387 | |
| 388 | void s_init(void) |
| 389 | { |
Eric Nelson | 2c37d3b | 2013-08-29 12:41:46 -0700 | [diff] [blame] | 390 | struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; |
Ye.Li | 2987687 | 2014-09-09 10:17:00 +0800 | [diff] [blame] | 391 | struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
Eric Nelson | 2c37d3b | 2013-08-29 12:41:46 -0700 | [diff] [blame] | 392 | u32 mask480; |
| 393 | u32 mask528; |
Ye.Li | 2987687 | 2014-09-09 10:17:00 +0800 | [diff] [blame] | 394 | u32 reg, periph1, periph2; |
Fabio Estevam | 6633e3f | 2014-07-09 16:13:29 -0300 | [diff] [blame] | 395 | |
| 396 | if (is_cpu_type(MXC_CPU_MX6SX)) |
| 397 | return; |
| 398 | |
Eric Nelson | 2c37d3b | 2013-08-29 12:41:46 -0700 | [diff] [blame] | 399 | /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs |
| 400 | * to make sure PFD is working right, otherwise, PFDs may |
| 401 | * not output clock after reset, MX6DL and MX6SL have added 396M pfd |
| 402 | * workaround in ROM code, as bus clock need it |
| 403 | */ |
| 404 | |
| 405 | mask480 = ANATOP_PFD_CLKGATE_MASK(0) | |
| 406 | ANATOP_PFD_CLKGATE_MASK(1) | |
| 407 | ANATOP_PFD_CLKGATE_MASK(2) | |
| 408 | ANATOP_PFD_CLKGATE_MASK(3); |
Ye.Li | 2987687 | 2014-09-09 10:17:00 +0800 | [diff] [blame] | 409 | mask528 = ANATOP_PFD_CLKGATE_MASK(1) | |
Eric Nelson | 2c37d3b | 2013-08-29 12:41:46 -0700 | [diff] [blame] | 410 | ANATOP_PFD_CLKGATE_MASK(3); |
| 411 | |
Ye.Li | 2987687 | 2014-09-09 10:17:00 +0800 | [diff] [blame] | 412 | reg = readl(&ccm->cbcmr); |
| 413 | periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) |
| 414 | >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET); |
| 415 | periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) |
| 416 | >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET); |
| 417 | |
| 418 | /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */ |
| 419 | if ((periph2 != 0x2) && (periph1 != 0x2)) |
| 420 | mask528 |= ANATOP_PFD_CLKGATE_MASK(0); |
| 421 | |
| 422 | if ((periph2 != 0x1) && (periph1 != 0x1) && |
| 423 | (periph2 != 0x3) && (periph1 != 0x3)) |
Eric Nelson | 2c37d3b | 2013-08-29 12:41:46 -0700 | [diff] [blame] | 424 | mask528 |= ANATOP_PFD_CLKGATE_MASK(2); |
Ye.Li | 2987687 | 2014-09-09 10:17:00 +0800 | [diff] [blame] | 425 | |
Eric Nelson | 2c37d3b | 2013-08-29 12:41:46 -0700 | [diff] [blame] | 426 | writel(mask480, &anatop->pfd_480_set); |
| 427 | writel(mask528, &anatop->pfd_528_set); |
| 428 | writel(mask480, &anatop->pfd_480_clr); |
| 429 | writel(mask528, &anatop->pfd_528_clr); |
Stephen Warren | 57ab23f | 2013-02-26 12:28:29 +0000 | [diff] [blame] | 430 | } |
Pardeep Kumar Singla | c1fa130 | 2013-07-25 12:12:13 -0500 | [diff] [blame] | 431 | |
| 432 | #ifdef CONFIG_IMX_HDMI |
| 433 | void imx_enable_hdmi_phy(void) |
| 434 | { |
| 435 | struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; |
| 436 | u8 reg; |
| 437 | reg = readb(&hdmi->phy_conf0); |
| 438 | reg |= HDMI_PHY_CONF0_PDZ_MASK; |
| 439 | writeb(reg, &hdmi->phy_conf0); |
| 440 | udelay(3000); |
| 441 | reg |= HDMI_PHY_CONF0_ENTMDS_MASK; |
| 442 | writeb(reg, &hdmi->phy_conf0); |
| 443 | udelay(3000); |
| 444 | reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK; |
| 445 | writeb(reg, &hdmi->phy_conf0); |
| 446 | writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz); |
| 447 | } |
| 448 | |
| 449 | void imx_setup_hdmi(void) |
| 450 | { |
| 451 | struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
| 452 | struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR; |
| 453 | int reg; |
| 454 | |
| 455 | /* Turn on HDMI PHY clock */ |
| 456 | reg = readl(&mxc_ccm->CCGR2); |
| 457 | reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK| |
| 458 | MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK; |
| 459 | writel(reg, &mxc_ccm->CCGR2); |
| 460 | writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz); |
| 461 | reg = readl(&mxc_ccm->chsccdr); |
| 462 | reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK| |
| 463 | MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK| |
| 464 | MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK); |
| 465 | reg |= (CHSCCDR_PODF_DIVIDE_BY_3 |
| 466 | << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) |
| 467 | |(CHSCCDR_IPU_PRE_CLK_540M_PFD |
| 468 | << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET); |
| 469 | writel(reg, &mxc_ccm->chsccdr); |
| 470 | } |
| 471 | #endif |
Fabio Estevam | 1340929 | 2014-01-29 17:39:49 -0200 | [diff] [blame] | 472 | |
| 473 | #ifndef CONFIG_SYS_L2CACHE_OFF |
| 474 | #define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002 |
| 475 | void v7_outer_cache_enable(void) |
| 476 | { |
| 477 | struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE; |
| 478 | unsigned int val; |
| 479 | |
| 480 | #if defined CONFIG_MX6SL |
| 481 | struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; |
| 482 | val = readl(&iomux->gpr[11]); |
| 483 | if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) { |
| 484 | /* L2 cache configured as OCRAM, reset it */ |
| 485 | val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM; |
| 486 | writel(val, &iomux->gpr[11]); |
| 487 | } |
| 488 | #endif |
| 489 | |
Ye.Li | a3e539a | 2014-08-20 17:18:24 +0800 | [diff] [blame] | 490 | /* Must disable the L2 before changing the latency parameters */ |
| 491 | clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); |
| 492 | |
Fabio Estevam | 1340929 | 2014-01-29 17:39:49 -0200 | [diff] [blame] | 493 | writel(0x132, &pl310->pl310_tag_latency_ctrl); |
| 494 | writel(0x132, &pl310->pl310_data_latency_ctrl); |
| 495 | |
| 496 | val = readl(&pl310->pl310_prefetch_ctrl); |
| 497 | |
| 498 | /* Turn on the L2 I/D prefetch */ |
| 499 | val |= 0x30000000; |
| 500 | |
| 501 | /* |
| 502 | * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0 |
| 503 | * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2 |
| 504 | * But according to ARM PL310 errata: 752271 |
| 505 | * ID: 752271: Double linefill feature can cause data corruption |
| 506 | * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2 |
| 507 | * Workaround: The only workaround to this erratum is to disable the |
| 508 | * double linefill feature. This is the default behavior. |
| 509 | */ |
| 510 | |
| 511 | #ifndef CONFIG_MX6Q |
| 512 | val |= 0x40800000; |
| 513 | #endif |
| 514 | writel(val, &pl310->pl310_prefetch_ctrl); |
| 515 | |
| 516 | val = readl(&pl310->pl310_power_ctrl); |
| 517 | val |= L2X0_DYNAMIC_CLK_GATING_EN; |
| 518 | val |= L2X0_STNDBY_MODE_EN; |
| 519 | writel(val, &pl310->pl310_power_ctrl); |
| 520 | |
| 521 | setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); |
| 522 | } |
| 523 | |
| 524 | void v7_outer_cache_disable(void) |
| 525 | { |
| 526 | struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE; |
| 527 | |
| 528 | clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); |
| 529 | } |
| 530 | #endif /* !CONFIG_SYS_L2CACHE_OFF */ |