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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Jon Loeliger77a4f6e2005-07-25 14:05:07 -05002/*
Kumar Galaad4e9d42011-01-04 17:57:59 -06003 * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor.
Biwen Li037fa1a2020-05-01 20:56:37 +08004 * Copyright 2020 NXP
Jon Loeliger77a4f6e2005-07-25 14:05:07 -05005 */
6
7/*
8 * mpc8548cds board configuration file
9 *
10 * Please refer to doc/README.mpc85xxcds for more info.
11 *
12 */
13#ifndef __CONFIG_H
14#define __CONFIG_H
15
Kumar Galaad4e9d42011-01-04 17:57:59 -060016#define CONFIG_SYS_SRIO
17#define CONFIG_SRIO1 /* SRIO port 1 */
18
Ed Swarthout95ae0a02007-07-27 01:50:52 -050019#define CONFIG_PCI1 /* PCI controller 1 */
Robert P. J. Daya8099812016-05-03 19:52:49 -040020#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
Ed Swarthout95ae0a02007-07-27 01:50:52 -050021#undef CONFIG_PCI2
Ed Swarthout95ae0a02007-07-27 01:50:52 -050022
Ed Swarthout95ae0a02007-07-27 01:50:52 -050023#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
Jon Loeliger77a4f6e2005-07-25 14:05:07 -050024
Jon Loeliger77a4f6e2005-07-25 14:05:07 -050025#ifndef __ASSEMBLY__
Simon Glassfb64e362020-05-10 11:40:09 -060026#include <linux/stringify.h>
Jon Loeliger77a4f6e2005-07-25 14:05:07 -050027#endif
Jon Loeliger77a4f6e2005-07-25 14:05:07 -050028
29/*
30 * These can be toggled for performance analysis, otherwise use default.
31 */
Ed Swarthout95ae0a02007-07-27 01:50:52 -050032#define CONFIG_L2_CACHE /* toggle L2 cache */
33#define CONFIG_BTB /* toggle branch predition */
Jon Loeliger77a4f6e2005-07-25 14:05:07 -050034
35/*
36 * Only possible on E500 Version 2 or newer cores.
37 */
38#define CONFIG_ENABLE_36BIT_PHYS 1
39
Timur Tabid8f341c2011-08-04 18:03:41 -050040#define CONFIG_SYS_CCSRBAR 0xe0000000
41#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Jon Loeliger77a4f6e2005-07-25 14:05:07 -050042
Jon Loeligerc378bae2008-03-18 13:51:06 -050043/* DDR Setup */
Jon Loeligerc378bae2008-03-18 13:51:06 -050044#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
Jon Loeligerc378bae2008-03-18 13:51:06 -050045
Jon Loeligerc378bae2008-03-18 13:51:06 -050046#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
47
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020048#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
49#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Jon Loeliger77a4f6e2005-07-25 14:05:07 -050050
Jon Loeligerc378bae2008-03-18 13:51:06 -050051#define CONFIG_DIMM_SLOTS_PER_CTLR 1
52#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
Jon Loeliger77a4f6e2005-07-25 14:05:07 -050053
Jon Loeligerc378bae2008-03-18 13:51:06 -050054/* I2C addresses of SPD EEPROMs */
55#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
56
57/* Make sure required options are set */
Jon Loeliger77a4f6e2005-07-25 14:05:07 -050058#ifndef CONFIG_SPD_EEPROM
59#error ("CONFIG_SPD_EEPROM is required")
60#endif
61
chenhui zhaoe97171e2011-10-13 13:40:59 +080062/*
63 * Physical Address Map
64 *
65 * 32bit:
66 * 0x0000_0000 0x7fff_ffff DDR 2G cacheable
67 * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M cacheable
68 * 0xa000_0000 0xbfff_ffff PCIe MEM 512M cacheable
69 * 0xc000_0000 0xdfff_ffff RapidIO 512M cacheable
70 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
71 * 0xe200_0000 0xe20f_ffff PCI1 IO 1M non-cacheable
72 * 0xe300_0000 0xe30f_ffff PCIe IO 1M non-cacheable
73 * 0xf000_0000 0xf3ff_ffff SDRAM 64M cacheable
74 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS 1M non-cacheable
75 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
76 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable
77 *
chenhui zhaoa9dd52d2011-10-13 13:41:00 +080078 * 36bit:
79 * 0x00000_0000 0x07fff_ffff DDR 2G cacheable
80 * 0xc0000_0000 0xc1fff_ffff PCI1 MEM 512M cacheable
81 * 0xc2000_0000 0xc3fff_ffff PCIe MEM 512M cacheable
82 * 0xc4000_0000 0xc5fff_ffff RapidIO 512M cacheable
83 * 0xfe000_0000 0xfe00f_ffff CCSR 1M non-cacheable
84 * 0xfe200_0000 0xfe20f_ffff PCI1 IO 1M non-cacheable
85 * 0xfe300_0000 0xfe30f_ffff PCIe IO 1M non-cacheable
86 * 0xff000_0000 0xff3ff_ffff SDRAM 64M cacheable
87 * 0xff800_0000 0xff80f_ffff NVRAM/CADMUS 1M non-cacheable
88 * 0xfff00_0000 0xfff7f_ffff FLASH (2nd bank) 8M non-cacheable
89 * 0xfff80_0000 0xfffff_ffff FLASH (boot bank) 8M non-cacheable
90 *
chenhui zhaoe97171e2011-10-13 13:40:59 +080091 */
92
Jon Loeliger77a4f6e2005-07-25 14:05:07 -050093/*
94 * Local Bus Definitions
95 */
96
97/*
98 * FLASH on the Local Bus
99 * Two banks, 8M each, using the CFI driver.
100 * Boot from BR0/OR0 bank at 0xff00_0000
101 * Alternate BR1/OR1 bank at 0xff80_0000
102 *
103 * BR0, BR1:
104 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
105 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
106 * Port Size = 16 bits = BRx[19:20] = 10
107 * Use GPCM = BRx[24:26] = 000
108 * Valid = BRx[31] = 1
109 *
Ed Swarthout95ae0a02007-07-27 01:50:52 -0500110 * 0 4 8 12 16 20 24 28
111 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
112 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500113 *
114 * OR0, OR1:
115 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
116 * Reserved ORx[17:18] = 11, confusion here?
117 * CSNT = ORx[20] = 1
118 * ACS = half cycle delay = ORx[21:22] = 11
119 * SCY = 6 = ORx[24:27] = 0110
120 * TRLX = use relaxed timing = ORx[29] = 1
121 * EAD = use external address latch delay = OR[31] = 1
122 *
Ed Swarthout95ae0a02007-07-27 01:50:52 -0500123 * 0 4 8 12 16 20 24 28
124 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500125 */
126
chenhui zhaoe97171e2011-10-13 13:40:59 +0800127#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
chenhui zhaoa9dd52d2011-10-13 13:41:00 +0800128#ifdef CONFIG_PHYS_64BIT
129#define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull
130#else
chenhui zhaoe97171e2011-10-13 13:40:59 +0800131#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
chenhui zhaoa9dd52d2011-10-13 13:41:00 +0800132#endif
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500133
chenhui zhaoe97171e2011-10-13 13:40:59 +0800134#define CONFIG_SYS_FLASH_BANKS_LIST \
135 {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS}
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200136#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
137#undef CONFIG_SYS_FLASH_CHECKSUM
138#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
139#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500140
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200141#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500142
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200143#define CONFIG_SYS_FLASH_EMPTY_INFO
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500144
chenhui zhao3560dbd2011-09-06 16:41:19 +0000145#define CONFIG_HWCONFIG /* enable hwconfig */
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500146
147/*
148 * SDRAM on the Local Bus
149 */
chenhui zhaoe97171e2011-10-13 13:40:59 +0800150#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
chenhui zhaoa9dd52d2011-10-13 13:41:00 +0800151#ifdef CONFIG_PHYS_64BIT
152#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull
153#else
chenhui zhaoe97171e2011-10-13 13:40:59 +0800154#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE
chenhui zhaoa9dd52d2011-10-13 13:41:00 +0800155#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200156#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500157
158/*
159 * Base Register 2 and Option Register 2 configure SDRAM.
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200160 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500161 *
162 * For BR2, need:
163 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
164 * port-size = 32-bits = BR2[19:20] = 11
165 * no parity checking = BR2[21:22] = 00
166 * SDRAM for MSEL = BR2[24:26] = 011
167 * Valid = BR[31] = 1
168 *
Ed Swarthout95ae0a02007-07-27 01:50:52 -0500169 * 0 4 8 12 16 20 24 28
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500170 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
171 *
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200172 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500173 * FIXME: the top 17 bits of BR2.
174 */
175
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500176/*
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200177 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500178 *
179 * For OR2, need:
180 * 64MB mask for AM, OR2[0:7] = 1111 1100
181 * XAM, OR2[17:18] = 11
182 * 9 columns OR2[19-21] = 010
Ed Swarthout95ae0a02007-07-27 01:50:52 -0500183 * 13 rows OR2[23-25] = 100
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500184 * EAD set for extra time OR[31] = 1
185 *
Ed Swarthout95ae0a02007-07-27 01:50:52 -0500186 * 0 4 8 12 16 20 24 28
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500187 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
188 */
189
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200190#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
191#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
192#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
193#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500194
195/*
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500196 * Common settings for all Local Bus SDRAM commands.
197 * At run time, either BSMA1516 (for CPU 1.1)
Ed Swarthout95ae0a02007-07-27 01:50:52 -0500198 * or BSMA1617 (for CPU 1.0) (old)
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500199 * is OR'ed in too.
200 */
Kumar Gala727c6a62009-03-26 01:34:38 -0500201#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
202 | LSDMR_PRETOACT7 \
203 | LSDMR_ACTTORW7 \
204 | LSDMR_BL8 \
205 | LSDMR_WRC4 \
206 | LSDMR_CL3 \
207 | LSDMR_RFEN \
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500208 )
209
210/*
211 * The CADMUS registers are connected to CS3 on CDS.
212 * The new memory map places CADMUS at 0xf8000000.
213 *
214 * For BR3, need:
215 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
216 * port-size = 8-bits = BR[19:20] = 01
217 * no parity checking = BR[21:22] = 00
Ed Swarthout95ae0a02007-07-27 01:50:52 -0500218 * GPMC for MSEL = BR[24:26] = 000
219 * Valid = BR[31] = 1
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500220 *
Ed Swarthout95ae0a02007-07-27 01:50:52 -0500221 * 0 4 8 12 16 20 24 28
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500222 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
223 *
224 * For OR3, need:
Ed Swarthout95ae0a02007-07-27 01:50:52 -0500225 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500226 * disable buffer ctrl OR[19] = 0
Ed Swarthout95ae0a02007-07-27 01:50:52 -0500227 * CSNT OR[20] = 1
228 * ACS OR[21:22] = 11
229 * XACS OR[23] = 1
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500230 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
Ed Swarthout95ae0a02007-07-27 01:50:52 -0500231 * SETA OR[28] = 0
232 * TRLX OR[29] = 1
233 * EHTR OR[30] = 1
234 * EAD extra time OR[31] = 1
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500235 *
Ed Swarthout95ae0a02007-07-27 01:50:52 -0500236 * 0 4 8 12 16 20 24 28
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500237 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
238 */
239
Jon Loeliger6bcdb402008-03-19 15:02:07 -0500240#define CONFIG_FSL_CADMUS
241
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500242#define CADMUS_BASE_ADDR 0xf8000000
chenhui zhaoa9dd52d2011-10-13 13:41:00 +0800243#ifdef CONFIG_PHYS_64BIT
244#define CADMUS_BASE_ADDR_PHYS 0xff8000000ull
245#else
chenhui zhaoe97171e2011-10-13 13:40:59 +0800246#define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR
chenhui zhaoa9dd52d2011-10-13 13:41:00 +0800247#endif
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500248
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200249#define CONFIG_SYS_INIT_RAM_LOCK 1
250#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200251#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500252
Wolfgang Denk0191e472010-10-26 14:34:52 +0200253#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200254#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500255
Hou Zhiqiang8547bb22019-08-20 09:35:35 +0000256#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500257
258/* Serial Port */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200259#define CONFIG_SYS_NS16550_SERIAL
260#define CONFIG_SYS_NS16550_REG_SIZE 1
261#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500262
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200263#define CONFIG_SYS_BAUDRATE_TABLE \
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500264 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
265
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200266#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
267#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500268
Jon Loeliger43d818f2006-10-20 15:50:15 -0500269/*
270 * I2C
271 */
Igor Opaniukf7c91762021-02-09 13:52:45 +0200272#if !CONFIG_IS_ENABLED(DM_I2C)
Heiko Schocherf2850742012-10-24 13:48:22 +0200273#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
Biwen Li037fa1a2020-05-01 20:56:37 +0800274#else
275#define CONFIG_SYS_SPD_BUS_NUM 0
Biwen Li037fa1a2020-05-01 20:56:37 +0800276#endif
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500277
Timur Tabi0b87d3f2008-07-18 16:52:23 +0200278/* EEPROM */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200279#define CONFIG_SYS_I2C_EEPROM_CCID
Timur Tabi0b87d3f2008-07-18 16:52:23 +0200280
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500281/*
282 * General PCI
Sergei Shtylyov6ffad932006-12-27 22:07:15 +0300283 * Memory space is mapped 1-1, but I/O space must start from 0.
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500284 */
Kumar Galaef43b6e2008-12-02 16:08:39 -0600285#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
chenhui zhaoa9dd52d2011-10-13 13:41:00 +0800286#ifdef CONFIG_PHYS_64BIT
287#define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000
288#define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull
289#else
Kumar Gala3fe80872008-12-02 16:08:36 -0600290#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
Kumar Galaef43b6e2008-12-02 16:08:39 -0600291#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
chenhui zhaoa9dd52d2011-10-13 13:41:00 +0800292#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200293#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
Kumar Gala60ff4642008-12-02 16:08:40 -0600294#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
Kumar Gala64bb6d12008-12-02 16:08:37 -0600295#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
chenhui zhaoa9dd52d2011-10-13 13:41:00 +0800296#ifdef CONFIG_PHYS_64BIT
297#define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull
298#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200299#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
chenhui zhaoa9dd52d2011-10-13 13:41:00 +0800300#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200301#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500302
Ed Swarthout95ae0a02007-07-27 01:50:52 -0500303#ifdef CONFIG_PCIE1
Kumar Galaef43b6e2008-12-02 16:08:39 -0600304#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
chenhui zhaoa9dd52d2011-10-13 13:41:00 +0800305#ifdef CONFIG_PHYS_64BIT
chenhui zhaoa9dd52d2011-10-13 13:41:00 +0800306#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull
307#else
Kumar Galaef43b6e2008-12-02 16:08:39 -0600308#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
chenhui zhaoa9dd52d2011-10-13 13:41:00 +0800309#endif
Kumar Gala60ff4642008-12-02 16:08:40 -0600310#define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000
chenhui zhaoa9dd52d2011-10-13 13:41:00 +0800311#ifdef CONFIG_PHYS_64BIT
312#define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull
313#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200314#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
chenhui zhaoa9dd52d2011-10-13 13:41:00 +0800315#endif
Ed Swarthout95ae0a02007-07-27 01:50:52 -0500316#endif
Zang Roy-r61911a5f77dc2006-12-14 14:14:55 +0800317
318/*
319 * RapidIO MMU
320 */
chenhui zhaoe97171e2011-10-13 13:40:59 +0800321#define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000
chenhui zhaoa9dd52d2011-10-13 13:41:00 +0800322#ifdef CONFIG_PHYS_64BIT
323#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull
324#else
chenhui zhaoe97171e2011-10-13 13:40:59 +0800325#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000
chenhui zhaoa9dd52d2011-10-13 13:41:00 +0800326#endif
Kumar Galaad4e9d42011-01-04 17:57:59 -0600327#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500328
Randy Vinson1dfd6d92007-02-27 19:42:22 -0700329#ifdef CONFIG_LEGACY
330#define BRIDGE_ID 17
331#define VIA_ID 2
332#else
333#define BRIDGE_ID 28
334#define VIA_ID 4
335#endif
336
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500337#if defined(CONFIG_PCI)
chenhui zhao3560dbd2011-09-06 16:41:19 +0000338#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500339#endif /* CONFIG_PCI */
340
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500341#if defined(CONFIG_TSEC_ENET)
342
Kim Phillips177e58f2007-05-16 16:52:19 -0500343#define CONFIG_TSEC1 1
344#define CONFIG_TSEC1_NAME "eTSEC0"
345#define CONFIG_TSEC2 1
346#define CONFIG_TSEC2_NAME "eTSEC1"
347#define CONFIG_TSEC3 1
348#define CONFIG_TSEC3_NAME "eTSEC2"
Ed Swarthout95ae0a02007-07-27 01:50:52 -0500349#define CONFIG_TSEC4
Kim Phillips177e58f2007-05-16 16:52:19 -0500350#define CONFIG_TSEC4_NAME "eTSEC3"
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500351#undef CONFIG_MPC85XX_FEC
352
353#define TSEC1_PHY_ADDR 0
354#define TSEC2_PHY_ADDR 1
355#define TSEC3_PHY_ADDR 2
356#define TSEC4_PHY_ADDR 3
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500357
358#define TSEC1_PHYIDX 0
359#define TSEC2_PHYIDX 0
360#define TSEC3_PHYIDX 0
361#define TSEC4_PHYIDX 0
Andy Fleming09b88df2007-08-15 20:03:25 -0500362#define TSEC1_FLAGS TSEC_GIGABIT
363#define TSEC2_FLAGS TSEC_GIGABIT
364#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
365#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500366
367/* Options are: eTSEC[0-3] */
368#define CONFIG_ETHPRIME "eTSEC0"
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500369#endif /* CONFIG_TSEC_ENET */
370
371/*
372 * Environment
373 */
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500374
375#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200376#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500377
Jon Loeligere63319f2007-06-13 13:22:08 -0500378/*
Jon Loeligered26c742007-07-10 09:10:49 -0500379 * BOOTP options
380 */
381#define CONFIG_BOOTP_BOOTFILESIZE
Jon Loeligered26c742007-07-10 09:10:49 -0500382
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500383/*
384 * Miscellaneous configurable options
385 */
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500386
387/*
388 * For booting Linux, the board info and command line data
Kumar Gala39ffcc12011-04-28 10:13:41 -0500389 * have to be in the first 64 MB of memory, since this is
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500390 * the maximum mapped by the Linux kernel during initialization.
391 */
Kumar Gala39ffcc12011-04-28 10:13:41 -0500392#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
393#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500394
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500395/*
396 * Environment Configuration
397 */
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500398#if defined(CONFIG_TSEC_ENET)
Andy Fleming458c3892007-08-16 16:35:02 -0500399#define CONFIG_HAS_ETH0
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500400#define CONFIG_HAS_ETH1
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500401#define CONFIG_HAS_ETH2
Andy Fleming239e75f2006-09-13 10:34:18 -0500402#define CONFIG_HAS_ETH3
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500403#endif
404
Ed Swarthout95ae0a02007-07-27 01:50:52 -0500405#define CONFIG_IPADDR 192.168.1.253
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500406
Mario Six790d8442018-03-28 14:38:20 +0200407#define CONFIG_HOSTNAME "unknown"
Joe Hershberger257ff782011-10-13 13:03:47 +0000408#define CONFIG_ROOTPATH "/nfsroot"
Joe Hershbergere4da2482011-10-13 13:03:48 +0000409#define CONFIG_BOOTFILE "8548cds/uImage.uboot"
Ed Swarthout95ae0a02007-07-27 01:50:52 -0500410#define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500411
Ed Swarthout95ae0a02007-07-27 01:50:52 -0500412#define CONFIG_SERVERIP 192.168.1.1
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500413#define CONFIG_GATEWAYIP 192.168.1.1
Ed Swarthout95ae0a02007-07-27 01:50:52 -0500414#define CONFIG_NETMASK 255.255.255.0
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500415
chenhui zhao3560dbd2011-09-06 16:41:19 +0000416#define CONFIG_EXTRA_ENV_SETTINGS \
417 "hwconfig=fsl_ddr:ecc=off\0" \
418 "netdev=eth0\0" \
Marek Vasut0b3176c2012-09-23 17:41:24 +0200419 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
chenhui zhao3560dbd2011-09-06 16:41:19 +0000420 "tftpflash=tftpboot $loadaddr $uboot; " \
Marek Vasut0b3176c2012-09-23 17:41:24 +0200421 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
422 " +$filesize; " \
423 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
424 " +$filesize; " \
425 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
426 " $filesize; " \
427 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
428 " +$filesize; " \
429 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
430 " $filesize\0" \
chenhui zhao3560dbd2011-09-06 16:41:19 +0000431 "consoledev=ttyS1\0" \
432 "ramdiskaddr=2000000\0" \
433 "ramdiskfile=ramdisk.uboot\0" \
Scott Woodb7f4b852016-07-19 17:52:06 -0500434 "fdtaddr=1e00000\0" \
chenhui zhao3560dbd2011-09-06 16:41:19 +0000435 "fdtfile=mpc8548cds.dtb\0"
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500436
Jon Loeliger77a4f6e2005-07-25 14:05:07 -0500437#endif /* __CONFIG_H */