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git01.mediatek.com / filogic / uboot / d3998fb69f0359e993ead28dc6f996d97ad4cf17 / . / arch / arm / mach-kirkwood / include / mach / config.h
blob: b6cf629c4f2aa7591fbdbaf077ed44146e0950bd [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Lei Wen20014762011-02-09 18:06:58 +0530[diff] [blame]2/*
3 * (C) Copyright 2011
4 * Marvell Semiconductor <www.marvell.com>
5 * Written-by: Lei Wen <leiwen@marvell.com>
Lei Wen20014762011-02-09 18:06:58 +0530[diff] [blame]6 */
7
8/*
9 * This file should be included in board config header file.
10 *
11 * It supports common definitions for Kirkwood platform
12 */
13
14#ifndef _KW_CONFIG_H
15#define _KW_CONFIG_H
16
17#if defined (CONFIG_KW88F6281)
18#include <asm/arch/kw88f6281.h>
19#elif defined (CONFIG_KW88F6192)
20#include <asm/arch/kw88f6192.h>
21#else
22#error "SOC Name not defined"
23#endif /* CONFIG_KW88F6281 */
24
Stefan Roesec2437842014-10-22 12:13:06 +0200[diff] [blame]25#include <asm/arch/soc.h>
Lei Wen20014762011-02-09 18:06:58 +0530[diff] [blame]26#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
27#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
28#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */
29
30/*
31 * By default kwbimage.cfg from board specific folder is used
32 * If for some board, different configuration file need to be used,
33 * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
34 */
35#ifndef CONFIG_SYS_KWD_CONFIG
Masahiro Yamadad6acdf22014-03-11 11:05:17 +0900[diff] [blame]36#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg
Lei Wen20014762011-02-09 18:06:58 +0530[diff] [blame]37#endif /* CONFIG_SYS_KWD_CONFIG */
38
39/* Kirkwood has 2k of Security SRAM, use it for SP */
40#define CONFIG_SYS_INIT_SP_ADDR 0xC8012000
Lei Wen20014762011-02-09 18:06:58 +0530[diff] [blame]41
Paul Kocialkowski2fae3e72015-04-10 23:09:51 +0200[diff] [blame]42#define CONFIG_I2C_MVTWSI_BASE0 KW_TWSI_BASE
Lei Wen20014762011-02-09 18:06:58 +0530[diff] [blame]43#define MV_UART_CONSOLE_BASE KW_UART0_BASE
44#define MV_SATA_BASE KW_SATA_BASE
45#define MV_SATA_PORT0_OFFSET KW_SATA_PORT0_OFFSET
46#define MV_SATA_PORT1_OFFSET KW_SATA_PORT1_OFFSET
47
48/*
49 * NAND configuration
50 */
51#ifdef CONFIG_CMD_NAND
52#define CONFIG_NAND_KIRKWOOD
53#define CONFIG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */
54#define NAND_ALLOW_ERASE_ALL 1
55#endif
56
57/*
Lei Wen20014762011-02-09 18:06:58 +0530[diff] [blame]58 * Ethernet Driver configuration
59 */
60#ifdef CONFIG_CMD_NET
Lei Wen20014762011-02-09 18:06:58 +0530[diff] [blame]61#define CONFIG_NETCONSOLE /* include NetConsole support */
Lei Wen20014762011-02-09 18:06:58 +0530[diff] [blame]62#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
63#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
64#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
65#endif /* CONFIG_CMD_NET */
66
67/*
68 * USB/EHCI
69 */
70#ifdef CONFIG_CMD_USB
Lei Wen20014762011-02-09 18:06:58 +0530[diff] [blame]71#define CONFIG_EHCI_IS_TDI
72#endif /* CONFIG_CMD_USB */
73
74/*
75 * IDE Support on SATA ports
76 */
Simon Glassb569a012017-05-17 03:25:30 -0600[diff] [blame]77#ifdef CONFIG_IDE
Lei Wen20014762011-02-09 18:06:58 +0530[diff] [blame]78#define __io
Lei Wen20014762011-02-09 18:06:58 +0530[diff] [blame]79#define CONFIG_IDE_PREINIT
80#define CONFIG_MVSATA_IDE_USE_PORT1
81/* Needs byte-swapping for ATA data register */
82#define CONFIG_IDE_SWAP_IO
83/* Data, registers and alternate blocks are at the same offset */
84#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100)
85#define CONFIG_SYS_ATA_REG_OFFSET (0x0100)
86#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100)
87/* Each 8-bit ATA register is aligned to a 4-bytes address */
88#define CONFIG_SYS_ATA_STRIDE 4
89/* Controller supports 48-bits LBA addressing */
90#define CONFIG_LBA48
Simon Glassb569a012017-05-17 03:25:30 -0600[diff] [blame]91/* CONFIG_IDE requires some #defines for ATA registers */
Lei Wen20014762011-02-09 18:06:58 +0530[diff] [blame]92#define CONFIG_SYS_IDE_MAXBUS 2
93#define CONFIG_SYS_IDE_MAXDEVICE 2
94/* ATA registers base is at SATA controller base */
95#define CONFIG_SYS_ATA_BASE_ADDR MV_SATA_BASE
Simon Glassb569a012017-05-17 03:25:30 -0600[diff] [blame]96#endif /* CONFIG_IDE */
Lei Wen20014762011-02-09 18:06:58 +0530[diff] [blame]97
98/*
99 * I2C related stuff
100 */
Chris Packhamd76c9b42018-05-30 20:14:34 +1200[diff] [blame]101#if defined(CONFIG_CMD_I2C) && !defined(CONFIG_DM_I2C)
Heiko Schocher479a4cf2013-01-29 08:53:15 +0100[diff] [blame]102#ifndef CONFIG_SYS_I2C_SOFT
Hans de Goede9830f1c2014-06-13 22:55:48 +0200[diff] [blame]103#define CONFIG_SYS_I2C
104#define CONFIG_SYS_I2C_MVTWSI
Holger Brunckf3f93d22011-06-16 18:11:15 +0530[diff] [blame]105#endif
Lei Wen20014762011-02-09 18:06:58 +0530[diff] [blame]106#define CONFIG_SYS_I2C_SLAVE 0x0
107#define CONFIG_SYS_I2C_SPEED 100000
108#endif
109
Stefan Roese64174892015-10-22 12:36:31 +0200[diff] [blame]110/* Use common timer */
111#define CONFIG_SYS_TIMER_COUNTS_DOWN
112#define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14)
113#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_TCLK
114
Lei Wen20014762011-02-09 18:06:58 +0530[diff] [blame]115#endif /* _KW_CONFIG_H */