blob: f6fc7801b95bca2c2d4622f76a915dec8c462955 [file] [log] [blame]
Alex Marginean7a910c12019-07-03 12:11:40 +03001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * ENETC ethernet controller driver
4 * Copyright 2017-2019 NXP
5 */
6
7#include <common.h>
8#include <dm.h>
9#include <errno.h>
Simon Glass2dc9c342020-05-10 11:40:01 -060010#include <fdt_support.h>
Simon Glass9bc15642020-02-03 07:36:16 -070011#include <malloc.h>
Alex Marginean7a910c12019-07-03 12:11:40 +030012#include <memalign.h>
Simon Glass274e0b02020-05-10 11:39:56 -060013#include <net.h>
14#include <asm/cache.h>
Alex Marginean7a910c12019-07-03 12:11:40 +030015#include <asm/io.h>
16#include <pci.h>
Alex Marginean02155392019-07-03 12:11:41 +030017#include <miiphy.h>
Simon Glassc06c1be2020-05-10 11:40:08 -060018#include <linux/bug.h>
Simon Glassdbd79542020-05-10 11:40:11 -060019#include <linux/delay.h>
Alex Marginean7a910c12019-07-03 12:11:40 +030020
21#include "fsl_enetc.h"
22
Alex Marginean805b8592019-12-10 16:55:39 +020023#define ENETC_DRIVER_NAME "enetc_eth"
24
25/*
26 * sets the MAC address in IERB registers, this setting is persistent and
27 * carried over to Linux.
28 */
29static void enetc_set_ierb_primary_mac(struct udevice *dev, int devfn,
30 const u8 *enetaddr)
31{
32#ifdef CONFIG_ARCH_LS1028A
33/*
34 * LS1028A is the only part with IERB at this time and there are plans to change
35 * its structure, keep this LS1028A specific for now
36 */
37#define IERB_BASE 0x1f0800000ULL
38#define IERB_PFMAC(pf, vf, n) (IERB_BASE + 0x8000 + (pf) * 0x100 + (vf) * 8 \
39 + (n) * 4)
40
41static int ierb_fn_to_pf[] = {0, 1, 2, -1, -1, -1, 3};
42
43 u16 lower = *(const u16 *)(enetaddr + 4);
44 u32 upper = *(const u32 *)enetaddr;
45
46 if (ierb_fn_to_pf[devfn] < 0)
47 return;
48
49 out_le32(IERB_PFMAC(ierb_fn_to_pf[devfn], 0, 0), upper);
50 out_le32(IERB_PFMAC(ierb_fn_to_pf[devfn], 0, 1), (u32)lower);
51#endif
52}
53
54/* sets up primary MAC addresses in DT/IERB */
55void fdt_fixup_enetc_mac(void *blob)
56{
Simon Glassb75b15b2020-12-03 16:55:23 -070057 struct pci_child_plat *ppdata;
Alex Marginean805b8592019-12-10 16:55:39 +020058 struct eth_pdata *pdata;
59 struct udevice *dev;
60 struct uclass *uc;
61 char path[256];
62 int offset;
63 int devfn;
64
65 uclass_get(UCLASS_ETH, &uc);
66 uclass_foreach_dev(dev, uc) {
67 if (!dev->driver || !dev->driver->name ||
68 strcmp(dev->driver->name, ENETC_DRIVER_NAME))
69 continue;
70
Simon Glassfa20e932020-12-03 16:55:20 -070071 pdata = dev_get_plat(dev);
Simon Glass71fa5b42020-12-03 16:55:18 -070072 ppdata = dev_get_parent_plat(dev);
Alex Marginean805b8592019-12-10 16:55:39 +020073 devfn = PCI_FUNC(ppdata->devfn);
74
75 enetc_set_ierb_primary_mac(dev, devfn, pdata->enetaddr);
76
77 snprintf(path, 256, "/soc/pcie@1f0000000/ethernet@%x,%x",
78 PCI_DEV(ppdata->devfn), PCI_FUNC(ppdata->devfn));
79 offset = fdt_path_offset(blob, path);
80 if (offset < 0)
81 continue;
82 fdt_setprop(blob, offset, "mac-address", pdata->enetaddr, 6);
83 }
84}
85
Alex Marginean7a910c12019-07-03 12:11:40 +030086/*
87 * Bind the device:
88 * - set a more explicit name on the interface
89 */
90static int enetc_bind(struct udevice *dev)
91{
92 char name[16];
93 static int eth_num_devices;
94
95 /*
96 * prefer using PCI function numbers to number interfaces, but these
97 * are only available if dts nodes are present. For PCI they are
98 * optional, handle that case too. Just in case some nodes are present
99 * and some are not, use different naming scheme - enetc-N based on
100 * PCI function # and enetc#N based on interface count
101 */
Simon Glassa7ece582020-12-19 10:40:14 -0700102 if (ofnode_valid(dev_ofnode(dev)))
Alex Marginean7a910c12019-07-03 12:11:40 +0300103 sprintf(name, "enetc-%u", PCI_FUNC(pci_get_devfn(dev)));
104 else
105 sprintf(name, "enetc#%u", eth_num_devices++);
106 device_set_name(dev, name);
107
108 return 0;
109}
110
Alex Marginean38882ae2019-07-03 12:11:42 +0300111/* MDIO wrappers, we're using these to drive internal MDIO to get to serdes */
112static int enetc_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
113{
114 struct enetc_mdio_priv priv;
115
116 priv.regs_base = bus->priv;
117 return enetc_mdio_read_priv(&priv, addr, devad, reg);
118}
119
120static int enetc_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
121 u16 val)
122{
123 struct enetc_mdio_priv priv;
124
125 priv.regs_base = bus->priv;
126 return enetc_mdio_write_priv(&priv, addr, devad, reg, val);
127}
128
129/* only interfaces that can pin out through serdes have internal MDIO */
130static bool enetc_has_imdio(struct udevice *dev)
131{
132 struct enetc_priv *priv = dev_get_priv(dev);
133
134 return !!(priv->imdio.priv);
135}
136
137/* set up serdes for SGMII */
138static int enetc_init_sgmii(struct udevice *dev)
139{
140 struct enetc_priv *priv = dev_get_priv(dev);
Alex Marginean41a7ac52019-07-15 11:48:47 +0300141 bool is2500 = false;
142 u16 reg;
Alex Marginean38882ae2019-07-03 12:11:42 +0300143
144 if (!enetc_has_imdio(dev))
145 return 0;
146
Alex Marginean41a7ac52019-07-15 11:48:47 +0300147 if (priv->if_type == PHY_INTERFACE_MODE_SGMII_2500)
148 is2500 = true;
149
150 /*
151 * Set to SGMII mode, for 1Gbps enable AN, for 2.5Gbps set fixed speed.
152 * Although fixed speed is 1Gbps, we could be running at 2.5Gbps based
153 * on PLL configuration. Setting 1G for 2.5G here is counter intuitive
154 * but intentional.
155 */
156 reg = ENETC_PCS_IF_MODE_SGMII;
157 reg |= is2500 ? ENETC_PCS_IF_MODE_SPEED_1G : ENETC_PCS_IF_MODE_SGMII_AN;
Alex Marginean38882ae2019-07-03 12:11:42 +0300158 enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
Alex Marginean41a7ac52019-07-15 11:48:47 +0300159 ENETC_PCS_IF_MODE, reg);
Alex Marginean38882ae2019-07-03 12:11:42 +0300160
161 /* Dev ability - SGMII */
162 enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
163 ENETC_PCS_DEV_ABILITY, ENETC_PCS_DEV_ABILITY_SGMII);
164
165 /* Adjust link timer for SGMII */
166 enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
167 ENETC_PCS_LINK_TIMER1, ENETC_PCS_LINK_TIMER1_VAL);
168 enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
169 ENETC_PCS_LINK_TIMER2, ENETC_PCS_LINK_TIMER2_VAL);
170
Alex Marginean41a7ac52019-07-15 11:48:47 +0300171 reg = ENETC_PCS_CR_DEF_VAL;
172 reg |= is2500 ? ENETC_PCS_CR_RST : ENETC_PCS_CR_RESET_AN;
Alex Marginean38882ae2019-07-03 12:11:42 +0300173 /* restart PCS AN */
174 enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE,
Alex Marginean41a7ac52019-07-15 11:48:47 +0300175 ENETC_PCS_CR, reg);
Alex Marginean38882ae2019-07-03 12:11:42 +0300176
177 return 0;
178}
179
180/* set up MAC for RGMII */
181static int enetc_init_rgmii(struct udevice *dev)
182{
183 struct enetc_priv *priv = dev_get_priv(dev);
184 u32 if_mode;
185
186 /* enable RGMII AN */
187 if_mode = enetc_read_port(priv, ENETC_PM_IF_MODE);
188 if_mode |= ENETC_PM_IF_MODE_AN_ENA;
189 enetc_write_port(priv, ENETC_PM_IF_MODE, if_mode);
190
191 return 0;
192}
193
Alex Margineanafad2d02020-01-10 23:32:20 +0200194/* set up MAC configuration for the given interface type */
195static void enetc_setup_mac_iface(struct udevice *dev)
Alex Marginean38882ae2019-07-03 12:11:42 +0300196{
197 struct enetc_priv *priv = dev_get_priv(dev);
198 u32 if_mode;
199
Alex Margineanafad2d02020-01-10 23:32:20 +0200200 switch (priv->if_type) {
201 case PHY_INTERFACE_MODE_RGMII:
202 case PHY_INTERFACE_MODE_RGMII_ID:
203 case PHY_INTERFACE_MODE_RGMII_RXID:
204 case PHY_INTERFACE_MODE_RGMII_TXID:
205 enetc_init_rgmii(dev);
206 break;
207 case PHY_INTERFACE_MODE_XGMII:
208 case PHY_INTERFACE_MODE_USXGMII:
209 case PHY_INTERFACE_MODE_XFI:
210 /* set ifmode to (US)XGMII */
211 if_mode = enetc_read_port(priv, ENETC_PM_IF_MODE);
212 if_mode &= ~ENETC_PM_IF_IFMODE_MASK;
213 enetc_write_port(priv, ENETC_PM_IF_MODE, if_mode);
214 break;
215 };
216}
217
218/* set up serdes for SXGMII */
219static int enetc_init_sxgmii(struct udevice *dev)
220{
221 struct enetc_priv *priv = dev_get_priv(dev);
Alex Marginean38882ae2019-07-03 12:11:42 +0300222
223 if (!enetc_has_imdio(dev))
224 return 0;
225
226 /* Dev ability - SXGMII */
227 enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, ENETC_PCS_DEVAD_REPL,
228 ENETC_PCS_DEV_ABILITY, ENETC_PCS_DEV_ABILITY_SXGMII);
229
230 /* Restart PCS AN */
231 enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, ENETC_PCS_DEVAD_REPL,
232 ENETC_PCS_CR,
Alex Marginean41a7ac52019-07-15 11:48:47 +0300233 ENETC_PCS_CR_RST | ENETC_PCS_CR_RESET_AN);
Alex Marginean38882ae2019-07-03 12:11:42 +0300234
235 return 0;
236}
237
238/* Apply protocol specific configuration to MAC, serdes as needed */
239static void enetc_start_pcs(struct udevice *dev)
240{
241 struct enetc_priv *priv = dev_get_priv(dev);
242 const char *if_str;
243
244 priv->if_type = PHY_INTERFACE_MODE_NONE;
245
Alex Margineand4be7682019-11-25 17:57:27 +0200246 /* register internal MDIO for debug purposes */
Alex Marginean38882ae2019-07-03 12:11:42 +0300247 if (enetc_read_port(priv, ENETC_PCAPR0) & ENETC_PCAPRO_MDIO) {
Alex Marginean38882ae2019-07-03 12:11:42 +0300248 priv->imdio.read = enetc_mdio_read;
249 priv->imdio.write = enetc_mdio_write;
250 priv->imdio.priv = priv->port_regs + ENETC_PM_IMDIO_BASE;
251 strncpy(priv->imdio.name, dev->name, MDIO_NAME_LEN);
Alex Margineand4be7682019-11-25 17:57:27 +0200252 if (!miiphy_get_dev_by_name(priv->imdio.name))
253 mdio_register(&priv->imdio);
Alex Marginean38882ae2019-07-03 12:11:42 +0300254 }
255
Simon Glassa7ece582020-12-19 10:40:14 -0700256 if (!ofnode_valid(dev_ofnode(dev))) {
Alex Marginean38882ae2019-07-03 12:11:42 +0300257 enetc_dbg(dev, "no enetc ofnode found, skipping PCS set-up\n");
258 return;
259 }
260
Simon Glassa7ece582020-12-19 10:40:14 -0700261 if_str = ofnode_read_string(dev_ofnode(dev), "phy-mode");
Alex Marginean38882ae2019-07-03 12:11:42 +0300262 if (if_str)
263 priv->if_type = phy_get_interface_by_name(if_str);
264 else
265 enetc_dbg(dev,
266 "phy-mode property not found, defaulting to SGMII\n");
267 if (priv->if_type < 0)
268 priv->if_type = PHY_INTERFACE_MODE_NONE;
269
270 switch (priv->if_type) {
271 case PHY_INTERFACE_MODE_SGMII:
Alex Marginean41a7ac52019-07-15 11:48:47 +0300272 case PHY_INTERFACE_MODE_SGMII_2500:
Alex Marginean38882ae2019-07-03 12:11:42 +0300273 enetc_init_sgmii(dev);
274 break;
Alex Marginean38882ae2019-07-03 12:11:42 +0300275 case PHY_INTERFACE_MODE_XGMII:
Alex Margineaned0460c2019-11-14 18:28:38 +0200276 case PHY_INTERFACE_MODE_USXGMII:
277 case PHY_INTERFACE_MODE_XFI:
Alex Marginean38882ae2019-07-03 12:11:42 +0300278 enetc_init_sxgmii(dev);
279 break;
280 };
281}
282
Alex Marginean02155392019-07-03 12:11:41 +0300283/* Configure the actual/external ethernet PHY, if one is found */
Alex Marginean602e00f2019-11-25 17:15:13 +0200284static void enetc_config_phy(struct udevice *dev)
Alex Marginean02155392019-07-03 12:11:41 +0300285{
286 struct enetc_priv *priv = dev_get_priv(dev);
Alex Marginean02155392019-07-03 12:11:41 +0300287 int supported;
288
Alex Marginean602e00f2019-11-25 17:15:13 +0200289 priv->phy = dm_eth_phy_connect(dev);
Alex Marginean02155392019-07-03 12:11:41 +0300290
Alex Marginean602e00f2019-11-25 17:15:13 +0200291 if (!priv->phy)
Alex Marginean02155392019-07-03 12:11:41 +0300292 return;
Alex Marginean02155392019-07-03 12:11:41 +0300293
Alex Margineanb93375c2019-11-14 18:58:45 +0200294 supported = PHY_GBIT_FEATURES | SUPPORTED_2500baseX_Full;
295 priv->phy->supported &= supported;
296 priv->phy->advertising &= supported;
Alex Marginean602e00f2019-11-25 17:15:13 +0200297
298 phy_config(priv->phy);
Alex Marginean02155392019-07-03 12:11:41 +0300299}
300
Alex Marginean7a910c12019-07-03 12:11:40 +0300301/*
302 * Probe ENETC driver:
303 * - initialize port and station interface BARs
304 */
305static int enetc_probe(struct udevice *dev)
306{
307 struct enetc_priv *priv = dev_get_priv(dev);
308
Simon Glassa7ece582020-12-19 10:40:14 -0700309 if (ofnode_valid(dev_ofnode(dev)) && !ofnode_is_available(dev_ofnode(dev))) {
Alex Marginean7a910c12019-07-03 12:11:40 +0300310 enetc_dbg(dev, "interface disabled\n");
311 return -ENODEV;
312 }
313
314 priv->enetc_txbd = memalign(ENETC_BD_ALIGN,
315 sizeof(struct enetc_tx_bd) * ENETC_BD_CNT);
316 priv->enetc_rxbd = memalign(ENETC_BD_ALIGN,
317 sizeof(union enetc_rx_bd) * ENETC_BD_CNT);
318
319 if (!priv->enetc_txbd || !priv->enetc_rxbd) {
320 /* free should be able to handle NULL, just free all pointers */
321 free(priv->enetc_txbd);
322 free(priv->enetc_rxbd);
323
324 return -ENOMEM;
325 }
326
327 /* initialize register */
328 priv->regs_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0);
329 if (!priv->regs_base) {
330 enetc_dbg(dev, "failed to map BAR0\n");
331 return -EINVAL;
332 }
333 priv->port_regs = priv->regs_base + ENETC_PORT_REGS_OFF;
334
335 dm_pci_clrset_config16(dev, PCI_COMMAND, 0, PCI_COMMAND_MEMORY);
336
Alex Margineanc905c212019-11-14 18:58:46 +0200337 enetc_start_pcs(dev);
338 enetc_config_phy(dev);
339
Alex Marginean7a910c12019-07-03 12:11:40 +0300340 return 0;
341}
342
343/*
344 * Remove the driver from an interface:
345 * - free up allocated memory
346 */
347static int enetc_remove(struct udevice *dev)
348{
349 struct enetc_priv *priv = dev_get_priv(dev);
350
351 free(priv->enetc_txbd);
352 free(priv->enetc_rxbd);
353
354 return 0;
355}
356
Michael Walle1d3e24f2019-12-20 14:16:48 +0100357/*
358 * LS1028A is the only part with IERB at this time and there are plans to
359 * change its structure, keep this LS1028A specific for now.
360 */
361#define LS1028A_IERB_BASE 0x1f0800000ULL
362#define LS1028A_IERB_PSIPMAR0(pf, vf) (LS1028A_IERB_BASE + 0x8000 \
363 + (pf) * 0x100 + (vf) * 8)
364#define LS1028A_IERB_PSIPMAR1(pf, vf) (LS1028A_IERB_PSIPMAR0(pf, vf) + 4)
365
366static int enetc_ls1028a_write_hwaddr(struct udevice *dev)
367{
Simon Glassb75b15b2020-12-03 16:55:23 -0700368 struct pci_child_plat *ppdata = dev_get_parent_plat(dev);
Michael Walle1d3e24f2019-12-20 14:16:48 +0100369 const int devfn_to_pf[] = {0, 1, 2, -1, -1, -1, 3};
Simon Glassfa20e932020-12-03 16:55:20 -0700370 struct eth_pdata *plat = dev_get_plat(dev);
Michael Walle1d3e24f2019-12-20 14:16:48 +0100371 int devfn = PCI_FUNC(ppdata->devfn);
372 u8 *addr = plat->enetaddr;
373 u32 lower, upper;
374 int pf;
375
376 if (devfn >= ARRAY_SIZE(devfn_to_pf))
377 return 0;
378
379 pf = devfn_to_pf[devfn];
380 if (pf < 0)
381 return 0;
382
383 lower = *(const u16 *)(addr + 4);
384 upper = *(const u32 *)addr;
385
386 out_le32(LS1028A_IERB_PSIPMAR0(pf, 0), upper);
387 out_le32(LS1028A_IERB_PSIPMAR1(pf, 0), lower);
388
389 return 0;
390}
391
Michael Walle8c7188e2019-12-20 14:16:47 +0100392static int enetc_write_hwaddr(struct udevice *dev)
Alex Marginean7a910c12019-07-03 12:11:40 +0300393{
Simon Glassfa20e932020-12-03 16:55:20 -0700394 struct eth_pdata *plat = dev_get_plat(dev);
Michael Walle8c7188e2019-12-20 14:16:47 +0100395 struct enetc_priv *priv = dev_get_priv(dev);
396 u8 *addr = plat->enetaddr;
397
Michael Walle1d3e24f2019-12-20 14:16:48 +0100398 if (IS_ENABLED(CONFIG_ARCH_LS1028A))
399 return enetc_ls1028a_write_hwaddr(dev);
400
Alex Marginean7a910c12019-07-03 12:11:40 +0300401 u16 lower = *(const u16 *)(addr + 4);
402 u32 upper = *(const u32 *)addr;
403
404 enetc_write_port(priv, ENETC_PSIPMAR0, upper);
405 enetc_write_port(priv, ENETC_PSIPMAR1, lower);
Michael Walle8c7188e2019-12-20 14:16:47 +0100406
407 return 0;
Alex Marginean7a910c12019-07-03 12:11:40 +0300408}
409
410/* Configure port parameters (# of rings, frame size, enable port) */
411static void enetc_enable_si_port(struct enetc_priv *priv)
412{
413 u32 val;
414
415 /* set Rx/Tx BDR count */
416 val = ENETC_PSICFGR_SET_TXBDR(ENETC_TX_BDR_CNT);
417 val |= ENETC_PSICFGR_SET_RXBDR(ENETC_RX_BDR_CNT);
418 enetc_write_port(priv, ENETC_PSICFGR(0), val);
419 /* set Rx max frame size */
420 enetc_write_port(priv, ENETC_PM_MAXFRM, ENETC_RX_MAXFRM_SIZE);
421 /* enable MAC port */
422 enetc_write_port(priv, ENETC_PM_CC, ENETC_PM_CC_RX_TX_EN);
423 /* enable port */
424 enetc_write_port(priv, ENETC_PMR, ENETC_PMR_SI0_EN);
425 /* set SI cache policy */
426 enetc_write(priv, ENETC_SICAR0,
427 ENETC_SICAR_RD_CFG | ENETC_SICAR_WR_CFG);
428 /* enable SI */
429 enetc_write(priv, ENETC_SIMR, ENETC_SIMR_EN);
430}
431
432/* returns DMA address for a given buffer index */
433static inline u64 enetc_rxb_address(struct udevice *dev, int i)
434{
435 return cpu_to_le64(dm_pci_virt_to_mem(dev, net_rx_packets[i]));
436}
437
438/*
439 * Setup a single Tx BD Ring (ID = 0):
440 * - set Tx buffer descriptor address
441 * - set the BD count
442 * - initialize the producer and consumer index
443 */
444static void enetc_setup_tx_bdr(struct udevice *dev)
445{
446 struct enetc_priv *priv = dev_get_priv(dev);
447 struct bd_ring *tx_bdr = &priv->tx_bdr;
448 u64 tx_bd_add = (u64)priv->enetc_txbd;
449
450 /* used later to advance to the next Tx BD */
451 tx_bdr->bd_count = ENETC_BD_CNT;
452 tx_bdr->next_prod_idx = 0;
453 tx_bdr->next_cons_idx = 0;
454 tx_bdr->cons_idx = priv->regs_base +
455 ENETC_BDR(TX, ENETC_TX_BDR_ID, ENETC_TBCIR);
456 tx_bdr->prod_idx = priv->regs_base +
457 ENETC_BDR(TX, ENETC_TX_BDR_ID, ENETC_TBPIR);
458
459 /* set Tx BD address */
460 enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBBAR0,
461 lower_32_bits(tx_bd_add));
462 enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBBAR1,
463 upper_32_bits(tx_bd_add));
464 /* set Tx 8 BD count */
465 enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBLENR,
466 tx_bdr->bd_count);
467
468 /* reset both producer/consumer indexes */
469 enetc_write_reg(tx_bdr->cons_idx, tx_bdr->next_cons_idx);
470 enetc_write_reg(tx_bdr->prod_idx, tx_bdr->next_prod_idx);
471
472 /* enable TX ring */
473 enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBMR, ENETC_TBMR_EN);
474}
475
476/*
477 * Setup a single Rx BD Ring (ID = 0):
478 * - set Rx buffer descriptors address (one descriptor per buffer)
479 * - set buffer size as max frame size
480 * - enable Rx ring
481 * - reset consumer and producer indexes
482 * - set buffer for each descriptor
483 */
484static void enetc_setup_rx_bdr(struct udevice *dev)
485{
486 struct enetc_priv *priv = dev_get_priv(dev);
487 struct bd_ring *rx_bdr = &priv->rx_bdr;
488 u64 rx_bd_add = (u64)priv->enetc_rxbd;
489 int i;
490
491 /* used later to advance to the next BD produced by ENETC HW */
492 rx_bdr->bd_count = ENETC_BD_CNT;
493 rx_bdr->next_prod_idx = 0;
494 rx_bdr->next_cons_idx = 0;
495 rx_bdr->cons_idx = priv->regs_base +
496 ENETC_BDR(RX, ENETC_RX_BDR_ID, ENETC_RBCIR);
497 rx_bdr->prod_idx = priv->regs_base +
498 ENETC_BDR(RX, ENETC_RX_BDR_ID, ENETC_RBPIR);
499
500 /* set Rx BD address */
501 enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBAR0,
502 lower_32_bits(rx_bd_add));
503 enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBAR1,
504 upper_32_bits(rx_bd_add));
505 /* set Rx BD count (multiple of 8) */
506 enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBLENR,
507 rx_bdr->bd_count);
508 /* set Rx buffer size */
509 enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBSR, PKTSIZE_ALIGN);
510
511 /* fill Rx BD */
512 memset(priv->enetc_rxbd, 0,
513 rx_bdr->bd_count * sizeof(union enetc_rx_bd));
514 for (i = 0; i < rx_bdr->bd_count; i++) {
515 priv->enetc_rxbd[i].w.addr = enetc_rxb_address(dev, i);
516 /* each RX buffer must be aligned to 64B */
517 WARN_ON(priv->enetc_rxbd[i].w.addr & (ARCH_DMA_MINALIGN - 1));
518 }
519
520 /* reset producer (ENETC owned) and consumer (SW owned) index */
521 enetc_write_reg(rx_bdr->cons_idx, rx_bdr->next_cons_idx);
522 enetc_write_reg(rx_bdr->prod_idx, rx_bdr->next_prod_idx);
523
524 /* enable Rx ring */
525 enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBMR, ENETC_RBMR_EN);
526}
527
528/*
529 * Start ENETC interface:
530 * - perform FLR
531 * - enable access to port and SI registers
532 * - set mac address
533 * - setup TX/RX buffer descriptors
534 * - enable Tx/Rx rings
535 */
536static int enetc_start(struct udevice *dev)
537{
Alex Marginean7a910c12019-07-03 12:11:40 +0300538 struct enetc_priv *priv = dev_get_priv(dev);
539
540 /* reset and enable the PCI device */
541 dm_pci_flr(dev);
542 dm_pci_clrset_config16(dev, PCI_COMMAND, 0,
543 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
544
Alex Marginean7a910c12019-07-03 12:11:40 +0300545 enetc_enable_si_port(priv);
546
547 /* setup Tx/Rx buffer descriptors */
548 enetc_setup_tx_bdr(dev);
549 enetc_setup_rx_bdr(dev);
550
Alex Margineanafad2d02020-01-10 23:32:20 +0200551 enetc_setup_mac_iface(dev);
Alex Margineanc905c212019-11-14 18:58:46 +0200552
Alex Marginean602e00f2019-11-25 17:15:13 +0200553 if (priv->phy)
554 phy_startup(priv->phy);
Alex Marginean02155392019-07-03 12:11:41 +0300555
Alex Marginean7a910c12019-07-03 12:11:40 +0300556 return 0;
557}
558
559/*
560 * Stop the network interface:
561 * - just quiesce it, we can wipe all configuration as _start starts from
562 * scratch each time
563 */
564static void enetc_stop(struct udevice *dev)
565{
566 /* FLR is sufficient to quiesce the device */
567 dm_pci_flr(dev);
Alex Margineand4be7682019-11-25 17:57:27 +0200568 /* leave the BARs accessible after we stop, this is needed to use
569 * internal MDIO in command line.
570 */
571 dm_pci_clrset_config16(dev, PCI_COMMAND, 0, PCI_COMMAND_MEMORY);
Alex Marginean7a910c12019-07-03 12:11:40 +0300572}
573
574/*
575 * ENETC transmit packet:
576 * - check if Tx BD ring is full
577 * - set buffer/packet address (dma address)
578 * - set final fragment flag
579 * - try while producer index equals consumer index or timeout
580 */
581static int enetc_send(struct udevice *dev, void *packet, int length)
582{
583 struct enetc_priv *priv = dev_get_priv(dev);
584 struct bd_ring *txr = &priv->tx_bdr;
585 void *nv_packet = (void *)packet;
586 int tries = ENETC_POLL_TRIES;
587 u32 pi, ci;
588
589 pi = txr->next_prod_idx;
590 ci = enetc_read_reg(txr->cons_idx) & ENETC_BDR_IDX_MASK;
591 /* Tx ring is full when */
592 if (((pi + 1) % txr->bd_count) == ci) {
593 enetc_dbg(dev, "Tx BDR full\n");
594 return -ETIMEDOUT;
595 }
596 enetc_dbg(dev, "TxBD[%d]send: pkt_len=%d, buff @0x%x%08x\n", pi, length,
597 upper_32_bits((u64)nv_packet), lower_32_bits((u64)nv_packet));
598
599 /* prepare Tx BD */
600 memset(&priv->enetc_txbd[pi], 0x0, sizeof(struct enetc_tx_bd));
601 priv->enetc_txbd[pi].addr =
602 cpu_to_le64(dm_pci_virt_to_mem(dev, nv_packet));
603 priv->enetc_txbd[pi].buf_len = cpu_to_le16(length);
604 priv->enetc_txbd[pi].frm_len = cpu_to_le16(length);
605 priv->enetc_txbd[pi].flags = cpu_to_le16(ENETC_TXBD_FLAGS_F);
606 dmb();
607 /* send frame: increment producer index */
608 pi = (pi + 1) % txr->bd_count;
609 txr->next_prod_idx = pi;
610 enetc_write_reg(txr->prod_idx, pi);
611 while ((--tries >= 0) &&
612 (pi != (enetc_read_reg(txr->cons_idx) & ENETC_BDR_IDX_MASK)))
613 udelay(10);
614
615 return tries > 0 ? 0 : -ETIMEDOUT;
616}
617
618/*
619 * Receive frame:
620 * - wait for the next BD to get ready bit set
621 * - clean up the descriptor
622 * - move on and indicate to HW that the cleaned BD is available for Rx
623 */
624static int enetc_recv(struct udevice *dev, int flags, uchar **packetp)
625{
626 struct enetc_priv *priv = dev_get_priv(dev);
627 struct bd_ring *rxr = &priv->rx_bdr;
628 int tries = ENETC_POLL_TRIES;
629 int pi = rxr->next_prod_idx;
630 int ci = rxr->next_cons_idx;
631 u32 status;
632 int len;
633 u8 rdy;
634
635 do {
636 dmb();
637 status = le32_to_cpu(priv->enetc_rxbd[pi].r.lstatus);
638 /* check if current BD is ready to be consumed */
639 rdy = ENETC_RXBD_STATUS_R(status);
640 } while (--tries >= 0 && !rdy);
641
642 if (!rdy)
643 return -EAGAIN;
644
645 dmb();
646 len = le16_to_cpu(priv->enetc_rxbd[pi].r.buf_len);
647 *packetp = (uchar *)enetc_rxb_address(dev, pi);
648 enetc_dbg(dev, "RxBD[%d]: len=%d err=%d pkt=0x%x%08x\n", pi, len,
649 ENETC_RXBD_STATUS_ERRORS(status),
650 upper_32_bits((u64)*packetp), lower_32_bits((u64)*packetp));
651
652 /* BD clean up and advance to next in ring */
653 memset(&priv->enetc_rxbd[pi], 0, sizeof(union enetc_rx_bd));
654 priv->enetc_rxbd[pi].w.addr = enetc_rxb_address(dev, pi);
655 rxr->next_prod_idx = (pi + 1) % rxr->bd_count;
656 ci = (ci + 1) % rxr->bd_count;
657 rxr->next_cons_idx = ci;
658 dmb();
659 /* free up the slot in the ring for HW */
660 enetc_write_reg(rxr->cons_idx, ci);
661
662 return len;
663}
664
665static const struct eth_ops enetc_ops = {
666 .start = enetc_start,
667 .send = enetc_send,
668 .recv = enetc_recv,
669 .stop = enetc_stop,
Michael Walle8c7188e2019-12-20 14:16:47 +0100670 .write_hwaddr = enetc_write_hwaddr,
Alex Marginean7a910c12019-07-03 12:11:40 +0300671};
672
673U_BOOT_DRIVER(eth_enetc) = {
Alex Marginean805b8592019-12-10 16:55:39 +0200674 .name = ENETC_DRIVER_NAME,
Alex Marginean7a910c12019-07-03 12:11:40 +0300675 .id = UCLASS_ETH,
676 .bind = enetc_bind,
677 .probe = enetc_probe,
678 .remove = enetc_remove,
679 .ops = &enetc_ops,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700680 .priv_auto = sizeof(struct enetc_priv),
Simon Glass71fa5b42020-12-03 16:55:18 -0700681 .plat_auto = sizeof(struct eth_pdata),
Alex Marginean7a910c12019-07-03 12:11:40 +0300682};
683
684static struct pci_device_id enetc_ids[] = {
685 { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_ENETC_ETH) },
686 {}
687};
688
689U_BOOT_PCI_DEVICE(eth_enetc, enetc_ids);