Blame - arch/arm/cpu/armv7/ls102xa/Kconfig - filogic/uboot

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York Sun	149eb33	2016-09-26 08:09:27 -0700	[diff] [blame]	1	config ARCH_LS1021A
York Sun	fcd0e74	2016-10-04 14:31:47 -0700	[diff] [blame]	2	bool
York Sun	149eb33	2016-09-26 08:09:27 -0700	[diff] [blame]	3	select SYS_FSL_ERRATUM_A010315
York Sun	6b62ef0	2016-10-04 18:01:34 -0700	[diff] [blame]	4	select SYS_FSL_SRDS_1
				5	select SYS_HAS_SERDES
York Sun	f64fc5c	2016-10-04 18:04:37 -0700	[diff] [blame]	6	select SYS_FSL_DDR_BE
				7	select SYS_FSL_DDR_VER_50
York Sun	92c36e2	2016-12-28 08:43:30 -0800	[diff] [blame]	8	select SYS_FSL_HAS_SEC
				9	select SYS_FSL_SEC_COMPAT_5
York Sun	fa419942	2016-12-28 08:43:31 -0800	[diff] [blame]	10	select SYS_FSL_SEC_LE
York Sun	4de7e93	2016-09-26 08:09:29 -0700	[diff] [blame]	11
York Sun	4dd8c61	2016-10-04 14:31:48 -0700	[diff] [blame]	12	menu "LS102xA architecture"
				13	depends on ARCH_LS1021A
				14
York Sun	4de7e93	2016-09-26 08:09:29 -0700	[diff] [blame]	15	config LS1_DEEP_SLEEP
York Sun	fcd0e74	2016-10-04 14:31:47 -0700	[diff] [blame]	16	bool "Deep sleep"
				17	depends on ARCH_LS1021A
York Sun	4dd8c61	2016-10-04 14:31:48 -0700	[diff] [blame]	18
York Sun	f188d22	2016-10-04 14:45:01 -0700	[diff] [blame]	19	config MAX_CPUS
				20	int "Maximum number of CPUs permitted for LS102xA"
				21	depends on ARCH_LS1021A
				22	default 2
				23	help
				24	Set this number to the maximum number of possible CPUs in the SoC.
				25	SoCs may have multiple clusters with each cluster may have multiple
				26	ports. If some ports are reserved but higher ports are used for
				27	cores, count the reserved ports. This will allocate enough memory
				28	in spin table to properly handle all cores.
				29
York Sun	f64fc5c	2016-10-04 18:04:37 -0700	[diff] [blame]	30	config NUM_DDR_CONTROLLERS
				31	int "Maximum DDR controllers"
				32	default 1
				33
York Sun	dfa93a9	2016-12-02 09:31:43 -0800	[diff] [blame]	34	config SECURE_BOOT
				35	bool "Secure Boot"
				36	help
				37	Enable Freescale Secure Boot feature. Normally selected
				38	by defconfig. If unsure, do not change.
				39
York Sun	4dd8c61	2016-10-04 14:31:48 -0700	[diff] [blame]	40	config SYS_FSL_ERRATUM_A010315
				41	bool "Workaround for PCIe erratum A010315"
				42
York Sun	6b62ef0	2016-10-04 18:01:34 -0700	[diff] [blame]	43	config SYS_FSL_SRDS_1
				44	bool
				45
				46	config SYS_FSL_SRDS_2
				47	bool
				48
				49	config SYS_HAS_SERDES
				50	bool
York Sun	f64fc5c	2016-10-04 18:04:37 -0700	[diff] [blame]	51
				52	config SYS_FSL_DDR
				53	bool "Freescale DDR driver"
				54	help
				55	Select Freescale General DDR driver, shared between most Freescale
				56	PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
				57	based Layerscape SoCs (such as ls2080a).
				58
				59	config SYS_FSL_DDR_BE
				60	bool
				61	default y
				62	help
				63	Access DDR registers in big-endian.
				64
				65	config SYS_FSL_DDR_VER
				66	int
				67	default 50 if SYS_FSL_DDR_VER_50
				68
				69	config SYS_FSL_DDR_VER_50
				70	bool
				71
				72	config SYS_FSL_DDRC_ARM_GEN3
				73	bool
				74
				75	config SYS_FSL_DDRC_GEN4
				76	bool
				77
				78	config SYS_FSL_DDR3
				79	bool "Freescale DDR3 controller"
				80	depends on !SYS_FSL_DDR4
				81	select SYS_FSL_DDR
				82	select SYS_FSL_DDRC_ARM_GEN3
				83	help
				84	Enable Freescale DDR3 controller on ARM-based SoCs.
				85
				86	config SYS_FSL_DDR4
				87	bool "Freescale DDR4 controller"
				88	select SYS_FSL_DDR
				89	select SYS_FSL_DDRC_GEN4
				90	help
				91	Enable Freescale DDR4 controller.
York Sun	6b62ef0	2016-10-04 18:01:34 -0700	[diff] [blame]	92
York Sun	e7310a3	2016-10-04 14:45:54 -0700	[diff] [blame]	93	config SYS_FSL_IFC_BANK_COUNT
				94	int "Maximum banks of Integrated flash controller"
				95	depends on ARCH_LS1021A
				96	default 8
				97
York Sun	4dd8c61	2016-10-04 14:31:48 -0700	[diff] [blame]	98	endmenu