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Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -04001/*
Enric Balletbò i Serra19f9df82012-03-05 11:32:16 +00002 * Common configuration settings for IGEP technology based boards
3 *
4 * (C) Copyright 2012
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -04005 * ISEE 2007 SL, <www.iseebcn.com>
6 *
Wolfgang Denkbd8ec7e2013-10-07 13:07:26 +02007 * SPDX-License-Identifier: GPL-2.0+
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -04008 */
9
Enric Balletbò i Serra19f9df82012-03-05 11:32:16 +000010#ifndef __IGEP00X0_H
11#define __IGEP00X0_H
12
Enric Balletbò i Serraed116482013-12-06 21:30:24 +010013#define CONFIG_NR_DRAM_BANKS 2
Ladislav Michl43a60622016-07-12 20:28:32 +020014#define CONFIG_NAND
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -040015
Enric Balletbò i Serraed116482013-12-06 21:30:24 +010016#include <configs/ti_omap3_common.h>
Enric Balletbo i Serra74fea922013-02-07 00:40:05 +000017#include <asm/mach-types.h>
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -040018
Tom Rinicfff4aa2016-08-26 13:30:43 -040019/*
20 * We are only ever GP parts and will utilize all of the "downloaded image"
21 * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB).
22 */
Enric Balletbo i Serra8aa10d42016-05-03 08:59:24 +020023#undef CONFIG_SPL_TEXT_BASE
Enric Balletbo i Serra8aa10d42016-05-03 08:59:24 +020024#define CONFIG_SPL_TEXT_BASE 0x40200000
25
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -040026#define CONFIG_MISC_INIT_R
27
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -040028#define CONFIG_REVISION_TAG 1
29
Enric Balletbo i Serra3bb41cc2015-02-24 19:27:15 +010030/* Status LED available for IGEP0020 and IGEP0030 but not IGEP0032 */
Tom Rinibd746e12017-01-10 17:22:06 -050031#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \
32 (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
Enric Balletbo i Serraa66c8872015-01-28 15:01:32 +010033#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
34#define RED_LED_GPIO 27
Enric Balletbo i Serra3bb41cc2015-02-24 19:27:15 +010035#elif (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
Enric Balletbo i Serraa66c8872015-01-28 15:01:32 +010036#define RED_LED_GPIO 16
Enric Balletbo i Serra02043a72013-02-07 00:40:06 +000037#endif
Enric Balletbo i Serra3bb41cc2015-02-24 19:27:15 +010038#endif
Javier Martinez Canillasd549ace2012-12-27 03:36:01 +000039
Enric Balletbo i Serra12fcb8c2014-01-25 22:52:22 +010040/* GPIO banks */
41#define CONFIG_OMAP3_GPIO_3 /* GPIO64 .. 95 is in GPIO bank 3 */
42#define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */
43#define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */
44
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -040045/* USB */
Ladislav Michl06c1cd02016-01-04 23:08:01 +010046#define CONFIG_USB_MUSB_UDC 1
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -040047#define CONFIG_USB_OMAP3 1
48#define CONFIG_TWL4030_USB 1
49
50/* USB device configuration */
51#define CONFIG_USB_DEVICE 1
52#define CONFIG_USB_TTY 1
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -040053
54/* Change these to suit your needs */
55#define CONFIG_USBD_VENDORID 0x0451
56#define CONFIG_USBD_PRODUCTID 0x5678
57#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
58#define CONFIG_USBD_PRODUCT_NAME "IGEP"
59
Ladislav Michl43a60622016-07-12 20:28:32 +020060#define CONFIG_CMD_MTDPARTS
61#define CONFIG_CMD_ONENAND
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -040062
Enric Balletbò i Serraa5d75f72015-09-07 08:28:09 +020063#ifndef CONFIG_SPL_BUILD
64
Enric Balletbò i Serraa5d75f72015-09-07 08:28:09 +020065/* Environment */
66#define ENV_DEVICE_SETTINGS \
67 "stdin=serial\0" \
68 "stdout=serial\0" \
69 "stderr=serial\0"
70
71#define MEM_LAYOUT_SETTINGS \
72 DEFAULT_LINUX_BOOT_ENV \
73 "scriptaddr=0x87E00000\0" \
74 "pxefile_addr_r=0x87F00000\0"
75
76#define BOOT_TARGET_DEVICES(func) \
77 func(MMC, mmc, 0)
78
79#include <config_distro_bootcmd.h>
80
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -040081#define CONFIG_EXTRA_ENV_SETTINGS \
Enric Balletbò i Serraa5d75f72015-09-07 08:28:09 +020082 ENV_DEVICE_SETTINGS \
83 MEM_LAYOUT_SETTINGS \
84 BOOTENV
Enric Balletbo i Serra4adf8012011-04-19 09:16:36 -040085
Enric Balletbò i Serraa5d75f72015-09-07 08:28:09 +020086#endif
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -040087
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -040088/*
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -040089 * SMSC911x Ethernet
90 */
91#if defined(CONFIG_CMD_NET)
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -040092#define CONFIG_SMC911X
93#define CONFIG_SMC911X_32_BIT
Ladislav Michl06c1cd02016-01-04 23:08:01 +010094#define CONFIG_SMC911X_BASE 0x2C000000
Enric Balletbo i Serra2ce268c2010-10-14 16:54:59 -040095#endif /* (CONFIG_CMD_NET) */
96
Ladislav Michl43a60622016-07-12 20:28:32 +020097#define CONFIG_RBTREE
98#define CONFIG_MTD_PARTITIONS
Ladislav Michlc44e29f2016-07-12 20:28:33 +020099#define CONFIG_SYS_MTDPARTS_RUNTIME
Javier Martinez Canillas361fc832012-07-28 01:19:34 +0000100
Ladislav Michl43a60622016-07-12 20:28:32 +0200101/* OneNAND config */
Ladislav Michl43a60622016-07-12 20:28:32 +0200102#define CONFIG_USE_ONENAND_BOARD_INIT
103#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
104#define CONFIG_SYS_ONENAND_BLOCK_SIZE (128*1024)
Javier Martinez Canillas361fc832012-07-28 01:19:34 +0000105
Ladislav Michl43a60622016-07-12 20:28:32 +0200106/* NAND config */
Ladislav Michl43a60622016-07-12 20:28:32 +0200107#define CONFIG_SPL_OMAP3_ID_NAND
Stefano Babic0cd41182015-07-26 15:18:15 +0200108#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
Javier Martinez Canillas361fc832012-07-28 01:19:34 +0000109#define CONFIG_SYS_NAND_5_ADDR_CYCLE
110#define CONFIG_SYS_NAND_PAGE_COUNT 64
111#define CONFIG_SYS_NAND_PAGE_SIZE 2048
112#define CONFIG_SYS_NAND_OOBSIZE 64
113#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
Ladislav Michl8ed5b0b2015-10-12 18:09:14 +0200114#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
115#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
116 10, 11, 12, 13, 14, 15, 16, 17, \
117 18, 19, 20, 21, 22, 23, 24, 25, \
118 26, 27, 28, 29, 30, 31, 32, 33, \
119 34, 35, 36, 37, 38, 39, 40, 41, \
120 42, 43, 44, 45, 46, 47, 48, 49, \
121 50, 51, 52, 53, 54, 55, 56, 57, }
Javier Martinez Canillas361fc832012-07-28 01:19:34 +0000122#define CONFIG_SYS_NAND_ECCSIZE 512
Ladislav Michl8ed5b0b2015-10-12 18:09:14 +0200123#define CONFIG_SYS_NAND_ECCBYTES 14
124#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
125#define CONFIG_NAND_OMAP_GPMC
126#define CONFIG_BCH
127
Ladislav Michl43a60622016-07-12 20:28:32 +0200128/* UBI configuration */
129#define CONFIG_SPL_UBI 1
130#define CONFIG_SPL_UBI_MAX_VOL_LEBS 256
131#define CONFIG_SPL_UBI_MAX_PEB_SIZE (256*1024)
132#define CONFIG_SPL_UBI_MAX_PEBS 4096
133#define CONFIG_SPL_UBI_VOL_IDS 8
134#define CONFIG_SPL_UBI_LOAD_MONITOR_ID 0
135#define CONFIG_SPL_UBI_LOAD_KERNEL_ID 3
136#define CONFIG_SPL_UBI_LOAD_ARGS_ID 4
137#define CONFIG_SPL_UBI_PEB_OFFSET 4
138#define CONFIG_SPL_UBI_VID_OFFSET 512
139#define CONFIG_SPL_UBI_LEB_START 2048
140#define CONFIG_SPL_UBI_INFO_ADDR 0x88080000
141
142/* environment organization */
143#define CONFIG_ENV_IS_IN_UBI 1
144#define CONFIG_ENV_UBI_PART "UBI"
145#define CONFIG_ENV_UBI_VOLUME "config"
146#define CONFIG_ENV_UBI_VOLUME_REDUND "config_r"
147#define CONFIG_UBI_SILENCE_MSG 1
148#define CONFIG_UBIFS_SILENCE_MSG 1
149#define CONFIG_ENV_SIZE (32*1024)
150
Enric Balletbò i Serra19f9df82012-03-05 11:32:16 +0000151#endif /* __IGEP00X0_H */