Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 1 | /* |
Wolfgang Denk | b853995 | 2009-05-16 10:47:43 +0200 | [diff] [blame] | 2 | * (C) Copyright 2007-2009 DENX Software Engineering |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 3 | * |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 4 | * SPDX-License-Identifier: GPL-2.0+ |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <common.h> |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 8 | #include <asm/bitops.h> |
| 9 | #include <command.h> |
Wolfgang Denk | b853995 | 2009-05-16 10:47:43 +0200 | [diff] [blame] | 10 | #include <asm/io.h> |
John Rigby | 0c9b301 | 2008-08-28 13:17:07 -0600 | [diff] [blame] | 11 | #include <asm/processor.h> |
Wolfgang Denk | 1d7cc1e | 2009-06-14 20:58:47 +0200 | [diff] [blame] | 12 | #include <asm/mpc512x.h> |
Wolfgang Denk | 049430f | 2008-01-13 00:55:47 +0100 | [diff] [blame] | 13 | #include <fdt_support.h> |
Martha Marx | fd449ab | 2008-05-29 14:23:25 -0400 | [diff] [blame] | 14 | #ifdef CONFIG_MISC_INIT_R |
| 15 | #include <i2c.h> |
| 16 | #endif |
Martha M Stan | ff8c0df | 2009-09-21 14:08:00 -0400 | [diff] [blame] | 17 | #include <net.h> |
Wolfgang Denk | 12cec0a | 2008-07-11 01:16:00 +0200 | [diff] [blame] | 18 | |
Stefan Roese | 406e95a | 2009-06-09 16:57:47 +0200 | [diff] [blame] | 19 | #include <linux/mtd/mtd.h> |
| 20 | #include <linux/mtd/nand.h> |
| 21 | |
Ralph Kondziella | d074bfe | 2009-01-26 12:34:36 -0700 | [diff] [blame] | 22 | DECLARE_GLOBAL_DATA_PTR; |
| 23 | |
Stefan Roese | 406e95a | 2009-06-09 16:57:47 +0200 | [diff] [blame] | 24 | void __mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip); |
| 25 | |
| 26 | /* Active chip number set in board_nand_select_device() (mpc5121_nfc.c) */ |
| 27 | extern int mpc5121_nfc_chip; |
| 28 | |
| 29 | /* Control chips select signal on MPC5121ADS board */ |
| 30 | void mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip) |
| 31 | { |
| 32 | unsigned char *csreg = (u8 *)CONFIG_SYS_CPLD_BASE + 0x09; |
| 33 | u8 v; |
| 34 | |
| 35 | v = in_8(csreg); |
| 36 | v |= 0x0F; |
| 37 | |
| 38 | if (chip >= 0) { |
| 39 | __mpc5121_nfc_select_chip(mtd, 0); |
| 40 | v &= ~(1 << mpc5121_nfc_chip); |
| 41 | } else { |
| 42 | __mpc5121_nfc_select_chip(mtd, -1); |
| 43 | } |
| 44 | |
| 45 | out_8(csreg, v); |
| 46 | } |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 47 | |
Wolfgang Denk | 1d7cc1e | 2009-06-14 20:58:47 +0200 | [diff] [blame] | 48 | int board_early_init_f(void) |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 49 | { |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 50 | /* |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 51 | * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control |
| 52 | * |
| 53 | * Without this the flash identification routine fails, as it needs to issue |
| 54 | * write commands in order to establish the device ID. |
| 55 | */ |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 56 | |
mark.vels@team-embedded.nl | ec28133 | 2010-10-05 17:46:19 +0200 | [diff] [blame] | 57 | #ifdef CONFIG_MPC5121ADS_REV2 |
Wolfgang Denk | b853995 | 2009-05-16 10:47:43 +0200 | [diff] [blame] | 58 | out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1); |
Martha Marx | fd449ab | 2008-05-29 14:23:25 -0400 | [diff] [blame] | 59 | #else |
Wolfgang Denk | b853995 | 2009-05-16 10:47:43 +0200 | [diff] [blame] | 60 | if (in_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) & 0x04) { |
| 61 | out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1); |
Martha Marx | fd449ab | 2008-05-29 14:23:25 -0400 | [diff] [blame] | 62 | } else { |
| 63 | /* running from Backup flash */ |
Wolfgang Denk | b853995 | 2009-05-16 10:47:43 +0200 | [diff] [blame] | 64 | out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0x32); |
Martha Marx | fd449ab | 2008-05-29 14:23:25 -0400 | [diff] [blame] | 65 | } |
| 66 | #endif |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 67 | return 0; |
| 68 | } |
| 69 | |
Martha M Stan | ff8c0df | 2009-09-21 14:08:00 -0400 | [diff] [blame] | 70 | int is_micron(void){ |
| 71 | |
| 72 | ushort brd_rev = *(vu_short *)(CONFIG_SYS_CPLD_BASE + 0x00); |
| 73 | uchar macaddr[6]; |
| 74 | u32 brddate, macchk, ismicron; |
| 75 | |
| 76 | /* |
| 77 | * MAC address has serial number with date of manufacture |
| 78 | * Boards made before Nov-08 #1180 use Micron memory; |
| 79 | * 001e59 is the STx vendor # |
| 80 | * Default is Elpida since it works for both but is slightly slower |
| 81 | */ |
| 82 | ismicron = 0; |
| 83 | if (brd_rev >= 0x0400 && eth_getenv_enetaddr("ethaddr", macaddr)) { |
| 84 | brddate = (macaddr[3] << 16) + (macaddr[4] << 8) + macaddr[5]; |
| 85 | macchk = (macaddr[0] << 16) + (macaddr[1] << 8) + macaddr[2]; |
| 86 | debug("brddate = %d\n\t", brddate); |
| 87 | |
| 88 | if (macchk == 0x001e59 && brddate <= 8111180) |
| 89 | ismicron = 1; |
| 90 | } else if (brd_rev < 0x400) { |
| 91 | ismicron = 1; |
| 92 | } |
| 93 | debug("Using %s Memory settings\n\t", |
| 94 | ismicron ? "Micron" : "Elpida"); |
| 95 | return(ismicron); |
| 96 | } |
| 97 | |
Wolfgang Denk | 1d7cc1e | 2009-06-14 20:58:47 +0200 | [diff] [blame] | 98 | phys_size_t initdram(int board_type) |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 99 | { |
| 100 | u32 msize = 0; |
Martha M Stan | ff8c0df | 2009-09-21 14:08:00 -0400 | [diff] [blame] | 101 | /* |
| 102 | * Elpida MDDRC and initialization settings are an alternative |
| 103 | * to the Default Micron ones for all but the earliest Rev 4 boards |
| 104 | */ |
Wolfgang Denk | ce33a01 | 2009-10-04 22:56:08 +0200 | [diff] [blame] | 105 | ddr512x_config_t elpida_mddrc_config = { |
| 106 | .ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA, |
| 107 | .ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0, |
| 108 | .ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA, |
| 109 | .ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA, |
Martha M Stan | ff8c0df | 2009-09-21 14:08:00 -0400 | [diff] [blame] | 110 | }; |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 111 | |
Martha M Stan | ff8c0df | 2009-09-21 14:08:00 -0400 | [diff] [blame] | 112 | u32 elpida_init_sequence[] = { |
| 113 | CONFIG_SYS_DDRCMD_NOP, |
| 114 | CONFIG_SYS_DDRCMD_NOP, |
| 115 | CONFIG_SYS_DDRCMD_NOP, |
| 116 | CONFIG_SYS_DDRCMD_NOP, |
| 117 | CONFIG_SYS_DDRCMD_NOP, |
| 118 | CONFIG_SYS_DDRCMD_NOP, |
| 119 | CONFIG_SYS_DDRCMD_NOP, |
| 120 | CONFIG_SYS_DDRCMD_NOP, |
| 121 | CONFIG_SYS_DDRCMD_NOP, |
| 122 | CONFIG_SYS_DDRCMD_NOP, |
| 123 | CONFIG_SYS_DDRCMD_PCHG_ALL, |
| 124 | CONFIG_SYS_DDRCMD_NOP, |
| 125 | CONFIG_SYS_DDRCMD_RFSH, |
| 126 | CONFIG_SYS_DDRCMD_NOP, |
| 127 | CONFIG_SYS_DDRCMD_RFSH, |
| 128 | CONFIG_SYS_DDRCMD_NOP, |
| 129 | CONFIG_SYS_DDRCMD_EM2, |
| 130 | CONFIG_SYS_DDRCMD_EM3, |
| 131 | CONFIG_SYS_DDRCMD_EN_DLL, |
| 132 | CONFIG_SYS_ELPIDA_RES_DLL, |
| 133 | CONFIG_SYS_DDRCMD_PCHG_ALL, |
| 134 | CONFIG_SYS_DDRCMD_RFSH, |
| 135 | CONFIG_SYS_DDRCMD_RFSH, |
| 136 | CONFIG_SYS_DDRCMD_RFSH, |
| 137 | CONFIG_SYS_ELPIDA_INIT_DEV_OP, |
| 138 | CONFIG_SYS_DDRCMD_NOP, |
| 139 | CONFIG_SYS_DDRCMD_NOP, |
| 140 | CONFIG_SYS_DDRCMD_NOP, |
| 141 | CONFIG_SYS_DDRCMD_NOP, |
| 142 | CONFIG_SYS_DDRCMD_NOP, |
| 143 | CONFIG_SYS_DDRCMD_NOP, |
| 144 | CONFIG_SYS_DDRCMD_NOP, |
| 145 | CONFIG_SYS_DDRCMD_NOP, |
| 146 | CONFIG_SYS_DDRCMD_NOP, |
| 147 | CONFIG_SYS_DDRCMD_NOP, |
| 148 | CONFIG_SYS_DDRCMD_OCD_DEFAULT, |
| 149 | CONFIG_SYS_ELPIDA_OCD_EXIT, |
| 150 | CONFIG_SYS_DDRCMD_NOP, |
| 151 | CONFIG_SYS_DDRCMD_NOP, |
| 152 | CONFIG_SYS_DDRCMD_NOP, |
| 153 | CONFIG_SYS_DDRCMD_NOP, |
| 154 | CONFIG_SYS_DDRCMD_NOP, |
| 155 | CONFIG_SYS_DDRCMD_NOP, |
| 156 | CONFIG_SYS_DDRCMD_NOP, |
| 157 | CONFIG_SYS_DDRCMD_NOP, |
| 158 | CONFIG_SYS_DDRCMD_NOP, |
| 159 | CONFIG_SYS_DDRCMD_NOP |
| 160 | }; |
| 161 | |
| 162 | if (is_micron()) { |
| 163 | msize = fixed_sdram(NULL, NULL, 0); |
| 164 | } else { |
Wolfgang Denk | ce33a01 | 2009-10-04 22:56:08 +0200 | [diff] [blame] | 165 | msize = fixed_sdram(&elpida_mddrc_config, |
Martha M Stan | ff8c0df | 2009-09-21 14:08:00 -0400 | [diff] [blame] | 166 | elpida_init_sequence, |
| 167 | sizeof(elpida_init_sequence)/sizeof(u32)); |
| 168 | } |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 169 | |
| 170 | return msize; |
| 171 | } |
| 172 | |
York Sun | fd7cbfd | 2008-05-05 10:20:01 -0500 | [diff] [blame] | 173 | int misc_init_r(void) |
| 174 | { |
| 175 | u8 tmp_val; |
| 176 | |
| 177 | /* Using this for DIU init before the driver in linux takes over |
| 178 | * Enable the TFP410 Encoder (I2C address 0x38) |
| 179 | */ |
| 180 | |
| 181 | i2c_set_bus_num(2); |
| 182 | tmp_val = 0xBF; |
| 183 | i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); |
| 184 | /* Verify if enabled */ |
| 185 | tmp_val = 0; |
| 186 | i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); |
Marek Vasut | 4a5a6d7 | 2011-10-21 14:17:03 +0000 | [diff] [blame] | 187 | debug("DVI Encoder Read: 0x%02x\n", tmp_val); |
York Sun | fd7cbfd | 2008-05-05 10:20:01 -0500 | [diff] [blame] | 188 | |
| 189 | tmp_val = 0x10; |
| 190 | i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); |
| 191 | /* Verify if enabled */ |
| 192 | tmp_val = 0; |
| 193 | i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); |
Marek Vasut | 4a5a6d7 | 2011-10-21 14:17:03 +0000 | [diff] [blame] | 194 | debug("DVI Encoder Read: 0x%02x\n", tmp_val); |
York Sun | fd7cbfd | 2008-05-05 10:20:01 -0500 | [diff] [blame] | 195 | |
York Sun | fd7cbfd | 2008-05-05 10:20:01 -0500 | [diff] [blame] | 196 | return 0; |
| 197 | } |
Wolfgang Denk | bbcbb32 | 2009-05-16 10:47:41 +0200 | [diff] [blame] | 198 | |
Kenneth Johansson | 8d676e4 | 2008-07-15 12:13:38 +0200 | [diff] [blame] | 199 | static iopin_t ioregs_init[] = { |
| 200 | /* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */ |
| 201 | { |
Wolfgang Denk | b853995 | 2009-05-16 10:47:43 +0200 | [diff] [blame] | 202 | offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0, |
Kenneth Johansson | 8d676e4 | 2008-07-15 12:13:38 +0200 | [diff] [blame] | 203 | IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | |
| 204 | IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) |
| 205 | }, |
| 206 | /* Set highest Slew on 9 PATA pins */ |
| 207 | { |
Wolfgang Denk | b853995 | 2009-05-16 10:47:43 +0200 | [diff] [blame] | 208 | offsetof(struct ioctrl512x, io_control_pata_ce1), 9, 1, |
Kenneth Johansson | 8d676e4 | 2008-07-15 12:13:38 +0200 | [diff] [blame] | 209 | IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | |
| 210 | IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) |
| 211 | }, |
| 212 | /* FUNC1=FEC_COL Sets Next 15 to FEC pads */ |
| 213 | { |
Wolfgang Denk | b853995 | 2009-05-16 10:47:43 +0200 | [diff] [blame] | 214 | offsetof(struct ioctrl512x, io_control_psc0_0), 15, 0, |
Kenneth Johansson | 8d676e4 | 2008-07-15 12:13:38 +0200 | [diff] [blame] | 215 | IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | |
| 216 | IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) |
| 217 | }, |
| 218 | /* FUNC1=SPDIF_TXCLK */ |
| 219 | { |
Wolfgang Denk | b853995 | 2009-05-16 10:47:43 +0200 | [diff] [blame] | 220 | offsetof(struct ioctrl512x, io_control_lpc_cs1), 1, 0, |
Kenneth Johansson | 8d676e4 | 2008-07-15 12:13:38 +0200 | [diff] [blame] | 221 | IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | |
| 222 | IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3) |
| 223 | }, |
| 224 | /* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */ |
| 225 | { |
Wolfgang Denk | b853995 | 2009-05-16 10:47:43 +0200 | [diff] [blame] | 226 | offsetof(struct ioctrl512x, io_control_i2c1_scl), 2, 0, |
Kenneth Johansson | 8d676e4 | 2008-07-15 12:13:38 +0200 | [diff] [blame] | 227 | IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | |
| 228 | IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3) |
| 229 | }, |
| 230 | /* FUNC2=DIU CLK */ |
| 231 | { |
Wolfgang Denk | b853995 | 2009-05-16 10:47:43 +0200 | [diff] [blame] | 232 | offsetof(struct ioctrl512x, io_control_psc6_0), 1, 0, |
Kenneth Johansson | 8d676e4 | 2008-07-15 12:13:38 +0200 | [diff] [blame] | 233 | IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | |
| 234 | IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3) |
| 235 | }, |
| 236 | /* FUNC2=DIU_HSYNC */ |
| 237 | { |
Wolfgang Denk | b853995 | 2009-05-16 10:47:43 +0200 | [diff] [blame] | 238 | offsetof(struct ioctrl512x, io_control_psc6_1), 1, 0, |
Kenneth Johansson | 8d676e4 | 2008-07-15 12:13:38 +0200 | [diff] [blame] | 239 | IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | |
| 240 | IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) |
| 241 | }, |
| 242 | /* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */ |
| 243 | { |
Wolfgang Denk | b853995 | 2009-05-16 10:47:43 +0200 | [diff] [blame] | 244 | offsetof(struct ioctrl512x, io_control_psc6_4), 26, 0, |
Kenneth Johansson | 8d676e4 | 2008-07-15 12:13:38 +0200 | [diff] [blame] | 245 | IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | |
| 246 | IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) |
| 247 | } |
| 248 | }; |
York Sun | fd7cbfd | 2008-05-05 10:20:01 -0500 | [diff] [blame] | 249 | |
John Rigby | ea1dfef | 2009-01-23 10:33:15 -0700 | [diff] [blame] | 250 | static iopin_t rev2_silicon_pci_ioregs_init[] = { |
| 251 | /* FUNC0=PCI Sets next 54 to PCI pads */ |
| 252 | { |
Wolfgang Denk | b853995 | 2009-05-16 10:47:43 +0200 | [diff] [blame] | 253 | offsetof(struct ioctrl512x, io_control_pci_ad31), 54, 0, |
John Rigby | ea1dfef | 2009-01-23 10:33:15 -0700 | [diff] [blame] | 254 | IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0) |
| 255 | } |
| 256 | }; |
| 257 | |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 258 | int checkboard (void) |
| 259 | { |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 260 | ushort brd_rev = *(vu_short *) (CONFIG_SYS_CPLD_BASE + 0x00); |
| 261 | uchar cpld_rev = *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x02); |
John Rigby | ea1dfef | 2009-01-23 10:33:15 -0700 | [diff] [blame] | 262 | volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; |
Wolfgang Denk | b853995 | 2009-05-16 10:47:43 +0200 | [diff] [blame] | 263 | u32 spridr = in_be32(&im->sysconf.spridr); |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 264 | |
mark.vels@team-embedded.nl | ec28133 | 2010-10-05 17:46:19 +0200 | [diff] [blame] | 265 | printf ("Board: MPC5121ADS rev. 0x%04x (CPLD rev. 0x%02x)\n", |
Wolfgang Denk | 530181f | 2007-08-02 21:27:46 +0200 | [diff] [blame] | 266 | brd_rev, cpld_rev); |
Wolfgang Denk | bbcbb32 | 2009-05-16 10:47:41 +0200 | [diff] [blame] | 267 | |
Martha Marx | 44727cb | 2008-05-29 15:37:21 -0400 | [diff] [blame] | 268 | /* initialize function mux & slew rate IO inter alia on IO Pins */ |
Wolfgang Denk | bbcbb32 | 2009-05-16 10:47:41 +0200 | [diff] [blame] | 269 | iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init)); |
Kenneth Johansson | 8d676e4 | 2008-07-15 12:13:38 +0200 | [diff] [blame] | 270 | |
Wolfgang Denk | b853995 | 2009-05-16 10:47:43 +0200 | [diff] [blame] | 271 | if (SVR_MJREV (spridr) >= 2) |
John Rigby | ea1dfef | 2009-01-23 10:33:15 -0700 | [diff] [blame] | 272 | iopin_initialize(rev2_silicon_pci_ioregs_init, 1); |
John Rigby | 92d24ac | 2007-08-24 18:18:43 -0600 | [diff] [blame] | 273 | |
Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame] | 274 | return 0; |
| 275 | } |
Grzegorz Bernacki | af554d8 | 2008-01-08 17:16:15 +0100 | [diff] [blame] | 276 | |
Robert P. J. Day | 3c75700 | 2016-05-19 15:23:12 -0400 | [diff] [blame] | 277 | #ifdef CONFIG_OF_BOARD_SETUP |
Simon Glass | 2aec3cc | 2014-10-23 18:58:47 -0600 | [diff] [blame] | 278 | int ft_board_setup(void *blob, bd_t *bd) |
Grzegorz Bernacki | af554d8 | 2008-01-08 17:16:15 +0100 | [diff] [blame] | 279 | { |
| 280 | ft_cpu_setup(blob, bd); |
Simon Glass | 2aec3cc | 2014-10-23 18:58:47 -0600 | [diff] [blame] | 281 | |
| 282 | return 0; |
Grzegorz Bernacki | af554d8 | 2008-01-08 17:16:15 +0100 | [diff] [blame] | 283 | } |
Robert P. J. Day | 3c75700 | 2016-05-19 15:23:12 -0400 | [diff] [blame] | 284 | #endif /* CONFIG_OF_BOARD_SETUP */ |