Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 2 | /* |
Vivek Mahajan | 288f7fb | 2009-05-25 17:23:16 +0530 | [diff] [blame] | 3 | * Copyright (C) 2004-2009 Freescale Semiconductor, Inc. |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <common.h> |
Simon Glass | 40d9b24 | 2020-05-10 11:40:07 -0600 | [diff] [blame] | 7 | #include <asm-offsets.h> |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 8 | #include <mpc83xx.h> |
Tom Rini | 4ddbade | 2022-05-25 12:16:03 -0400 | [diff] [blame] | 9 | #include <system-constants.h> |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 10 | #include <ioports.h> |
Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 11 | #include <asm/global_data.h> |
Vivek Mahajan | 288f7fb | 2009-05-25 17:23:16 +0530 | [diff] [blame] | 12 | #include <asm/io.h> |
Simon Glass | 156283f | 2017-03-28 10:27:27 -0600 | [diff] [blame] | 13 | #include <asm/processor.h> |
Heiko Schocher | 3b76773 | 2020-04-15 10:35:40 +0200 | [diff] [blame] | 14 | #include <fsl_qe.h> |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 15 | #ifdef CONFIG_USB_EHCI_FSL |
Mateusz Kulikowski | 3add69e | 2016-03-31 23:12:23 +0200 | [diff] [blame] | 16 | #include <usb/ehci-ci.h> |
Vivek Mahajan | 288f7fb | 2009-05-25 17:23:16 +0530 | [diff] [blame] | 17 | #endif |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 18 | #include <linux/delay.h> |
Heiko Schocher | 3b07a13 | 2020-02-03 10:23:53 +0100 | [diff] [blame] | 19 | #ifdef CONFIG_QE |
| 20 | #include <fsl_qe.h> |
| 21 | #endif |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 22 | |
Mario Six | b47839c | 2019-01-21 09:17:58 +0100 | [diff] [blame] | 23 | #include "lblaw/lblaw.h" |
Mario Six | 1faf95d | 2019-01-21 09:18:03 +0100 | [diff] [blame] | 24 | #include "elbc/elbc.h" |
Mario Six | 636c108 | 2019-01-21 09:18:11 +0100 | [diff] [blame] | 25 | #include "sysio/sysio.h" |
Mario Six | aa50254 | 2019-01-21 09:18:12 +0100 | [diff] [blame] | 26 | #include "arbiter/arbiter.h" |
Mario Six | f62074e | 2019-01-21 09:18:13 +0100 | [diff] [blame] | 27 | #include "initreg/initreg.h" |
Mario Six | b47839c | 2019-01-21 09:17:58 +0100 | [diff] [blame] | 28 | |
Wolfgang Denk | 6405a15 | 2006-03-31 18:32:53 +0200 | [diff] [blame] | 29 | DECLARE_GLOBAL_DATA_PTR; |
| 30 | |
Dave Liu | e732e9c | 2006-11-03 12:11:15 -0600 | [diff] [blame] | 31 | #ifdef CONFIG_QE |
| 32 | extern qe_iop_conf_t qe_iop_conf_tab[]; |
| 33 | extern void qe_config_iopin(u8 port, u8 pin, int dir, |
| 34 | int open_drain, int assign); |
Dave Liu | e732e9c | 2006-11-03 12:11:15 -0600 | [diff] [blame] | 35 | |
Heiko Schocher | 3b07a13 | 2020-02-03 10:23:53 +0100 | [diff] [blame] | 36 | #if !defined(CONFIG_PINCTRL) |
Dave Liu | e732e9c | 2006-11-03 12:11:15 -0600 | [diff] [blame] | 37 | static void config_qe_ioports(void) |
| 38 | { |
| 39 | u8 port, pin; |
| 40 | int dir, open_drain, assign; |
| 41 | int i; |
| 42 | |
| 43 | for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { |
| 44 | port = qe_iop_conf_tab[i].port; |
| 45 | pin = qe_iop_conf_tab[i].pin; |
| 46 | dir = qe_iop_conf_tab[i].dir; |
| 47 | open_drain = qe_iop_conf_tab[i].open_drain; |
| 48 | assign = qe_iop_conf_tab[i].assign; |
| 49 | qe_config_iopin(port, pin, dir, open_drain, assign); |
| 50 | } |
| 51 | } |
| 52 | #endif |
Heiko Schocher | 3b07a13 | 2020-02-03 10:23:53 +0100 | [diff] [blame] | 53 | #endif |
Dave Liu | e732e9c | 2006-11-03 12:11:15 -0600 | [diff] [blame] | 54 | |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 55 | /* |
| 56 | * Breathe some life into the CPU... |
| 57 | * |
| 58 | * Set up the memory map, |
| 59 | * initialize a bunch of registers, |
| 60 | * initialize the UPM's |
| 61 | */ |
| 62 | void cpu_init_f (volatile immap_t * im) |
| 63 | { |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 64 | __be32 sccr_mask = |
| 65 | #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */ |
Kim Phillips | 8d5fa6a | 2010-05-19 17:06:46 -0500 | [diff] [blame] | 66 | SCCR_ENCCM | |
Kim Phillips | 19a91de | 2008-01-16 12:06:16 -0600 | [diff] [blame] | 67 | #endif |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 68 | #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */ |
Kim Phillips | 8d5fa6a | 2010-05-19 17:06:46 -0500 | [diff] [blame] | 69 | SCCR_PCICM | |
Kim Phillips | 19a91de | 2008-01-16 12:06:16 -0600 | [diff] [blame] | 70 | #endif |
Ilya Yanok | a4f3ed3 | 2010-09-17 23:41:47 +0200 | [diff] [blame] | 71 | #ifdef CONFIG_SYS_SCCR_PCIEXP1CM /* PCIE1 clock mode */ |
| 72 | SCCR_PCIEXP1CM | |
| 73 | #endif |
| 74 | #ifdef CONFIG_SYS_SCCR_PCIEXP2CM /* PCIE2 clock mode */ |
| 75 | SCCR_PCIEXP2CM | |
| 76 | #endif |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 77 | #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */ |
Kim Phillips | 8d5fa6a | 2010-05-19 17:06:46 -0500 | [diff] [blame] | 78 | SCCR_TSECCM | |
Timur Tabi | 054838e | 2006-10-31 18:44:42 -0600 | [diff] [blame] | 79 | #endif |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 80 | #ifdef CFG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */ |
Kim Phillips | 8d5fa6a | 2010-05-19 17:06:46 -0500 | [diff] [blame] | 81 | SCCR_TSEC1CM | |
Timur Tabi | 054838e | 2006-10-31 18:44:42 -0600 | [diff] [blame] | 82 | #endif |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 83 | #ifdef CFG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */ |
Kim Phillips | 8d5fa6a | 2010-05-19 17:06:46 -0500 | [diff] [blame] | 84 | SCCR_TSEC2CM | |
Kumar Gala | 15c3f69 | 2007-02-27 23:51:42 -0600 | [diff] [blame] | 85 | #endif |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 86 | #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */ |
Kim Phillips | 8d5fa6a | 2010-05-19 17:06:46 -0500 | [diff] [blame] | 87 | SCCR_TSEC1ON | |
Timur Tabi | 0b2deff | 2007-07-03 13:04:34 -0500 | [diff] [blame] | 88 | #endif |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 89 | #ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */ |
Kim Phillips | 8d5fa6a | 2010-05-19 17:06:46 -0500 | [diff] [blame] | 90 | SCCR_TSEC2ON | |
Timur Tabi | 0b2deff | 2007-07-03 13:04:34 -0500 | [diff] [blame] | 91 | #endif |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 92 | #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */ |
Kim Phillips | 8d5fa6a | 2010-05-19 17:06:46 -0500 | [diff] [blame] | 93 | SCCR_USBMPHCM | |
Kumar Gala | 15c3f69 | 2007-02-27 23:51:42 -0600 | [diff] [blame] | 94 | #endif |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 95 | #ifdef CFG_SYS_SCCR_USBDRCM /* USB DR clock mode */ |
Kim Phillips | 8d5fa6a | 2010-05-19 17:06:46 -0500 | [diff] [blame] | 96 | SCCR_USBDRCM | |
Kumar Gala | 15c3f69 | 2007-02-27 23:51:42 -0600 | [diff] [blame] | 97 | #endif |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 98 | #ifdef CFG_SYS_SCCR_SATACM /* SATA controller clock mode */ |
Kim Phillips | 8d5fa6a | 2010-05-19 17:06:46 -0500 | [diff] [blame] | 99 | SCCR_SATACM | |
Timur Tabi | 054838e | 2006-10-31 18:44:42 -0600 | [diff] [blame] | 100 | #endif |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 101 | 0; |
| 102 | __be32 sccr_val = |
| 103 | #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */ |
| 104 | (CONFIG_SYS_SCCR_ENCCM << SCCR_ENCCM_SHIFT) | |
| 105 | #endif |
| 106 | #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */ |
| 107 | (CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT) | |
| 108 | #endif |
Ilya Yanok | a4f3ed3 | 2010-09-17 23:41:47 +0200 | [diff] [blame] | 109 | #ifdef CONFIG_SYS_SCCR_PCIEXP1CM /* PCIE1 clock mode */ |
| 110 | (CONFIG_SYS_SCCR_PCIEXP1CM << SCCR_PCIEXP1CM_SHIFT) | |
| 111 | #endif |
| 112 | #ifdef CONFIG_SYS_SCCR_PCIEXP2CM /* PCIE2 clock mode */ |
| 113 | (CONFIG_SYS_SCCR_PCIEXP2CM << SCCR_PCIEXP2CM_SHIFT) | |
| 114 | #endif |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 115 | #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */ |
| 116 | (CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT) | |
| 117 | #endif |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 118 | #ifdef CFG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */ |
| 119 | (CFG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) | |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 120 | #endif |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 121 | #ifdef CFG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */ |
| 122 | (CFG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) | |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 123 | #endif |
| 124 | #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */ |
| 125 | (CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) | |
| 126 | #endif |
| 127 | #ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */ |
| 128 | (CONFIG_SYS_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) | |
| 129 | #endif |
| 130 | #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */ |
| 131 | (CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) | |
| 132 | #endif |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 133 | #ifdef CFG_SYS_SCCR_USBDRCM /* USB DR clock mode */ |
| 134 | (CFG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) | |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 135 | #endif |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 136 | #ifdef CFG_SYS_SCCR_SATACM /* SATA controller clock mode */ |
| 137 | (CFG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) | |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 138 | #endif |
| 139 | 0; |
| 140 | |
| 141 | /* Pointer is writable since we allocated a register for it */ |
Tom Rini | 4ddbade | 2022-05-25 12:16:03 -0400 | [diff] [blame] | 142 | gd = (gd_t *)SYS_INIT_SP_ADDR; |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 143 | |
mario.six@gdsys.cc | 85df7b4 | 2017-01-17 08:33:48 +0100 | [diff] [blame] | 144 | /* global data region was cleared in start.S */ |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 145 | |
| 146 | /* system performance tweaking */ |
| 147 | clrsetbits_be32(&im->arbiter.acr, acr_mask, acr_val); |
| 148 | |
| 149 | clrsetbits_be32(&im->sysconf.spcr, spcr_mask, spcr_val); |
| 150 | |
| 151 | clrsetbits_be32(&im->clk.sccr, sccr_mask, sccr_val); |
Timur Tabi | 054838e | 2006-10-31 18:44:42 -0600 | [diff] [blame] | 152 | |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 153 | /* RSR - Reset Status Register - clear all status (4.6.1.3) */ |
Simon Glass | 4d6eaa3 | 2012-12-13 20:48:56 +0000 | [diff] [blame] | 154 | gd->arch.reset_status = __raw_readl(&im->reset.rsr); |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 155 | __raw_writel(~(RSR_RES), &im->reset.rsr); |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 156 | |
Nick Spence | 56fd3c2 | 2008-08-28 14:09:19 -0700 | [diff] [blame] | 157 | /* AER - Arbiter Event Register - store status */ |
Simon Glass | 387a1f2 | 2012-12-13 20:48:57 +0000 | [diff] [blame] | 158 | gd->arch.arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr); |
| 159 | gd->arch.arbiter_event_address = __raw_readl(&im->arbiter.aeadr); |
Nick Spence | 56fd3c2 | 2008-08-28 14:09:19 -0700 | [diff] [blame] | 160 | |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 161 | /* |
| 162 | * RMR - Reset Mode Register |
| 163 | * contains checkstop reset enable (4.6.1.4) |
| 164 | */ |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 165 | __raw_writel(RMR_CSRE & (1<<RMR_CSRE_SHIFT), &im->reset.rmr); |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 166 | |
Peter Korsgaard | 2a483ee | 2009-12-08 22:20:34 +0100 | [diff] [blame] | 167 | /* LCRR - Clock Ratio Register (10.3.1.16) |
| 168 | * write, read, and isync per MPC8379ERM rev.1 CLKDEV field description |
| 169 | */ |
Becky Bruce | 0d4cee1 | 2010-06-17 11:37:20 -0500 | [diff] [blame] | 170 | clrsetbits_be32(&im->im_lbc.lcrr, lcrr_mask, lcrr_val); |
| 171 | __raw_readl(&im->im_lbc.lcrr); |
Peter Korsgaard | 2a483ee | 2009-12-08 22:20:34 +0100 | [diff] [blame] | 172 | isync(); |
| 173 | |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 174 | /* Enable Time Base & Decrementer ( so we will have udelay() )*/ |
| 175 | setbits_be32(&im->sysconf.spcr, SPCR_TBEN); |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 176 | |
| 177 | /* System General Purpose Register */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 178 | #ifdef CFG_SYS_SICRH |
Mario Six | 0344f5e | 2019-01-21 09:17:27 +0100 | [diff] [blame] | 179 | #if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC8313) |
Andre Schwarz | cea6648 | 2008-06-23 11:40:56 +0200 | [diff] [blame] | 180 | /* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 181 | __raw_writel((im->sysconf.sicrh & 0x0000000C) | CFG_SYS_SICRH, |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 182 | &im->sysconf.sicrh); |
Andre Schwarz | cea6648 | 2008-06-23 11:40:56 +0200 | [diff] [blame] | 183 | #else |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 184 | __raw_writel(CFG_SYS_SICRH, &im->sysconf.sicrh); |
Kumar Gala | e522143 | 2006-01-11 11:12:57 -0600 | [diff] [blame] | 185 | #endif |
Andre Schwarz | cea6648 | 2008-06-23 11:40:56 +0200 | [diff] [blame] | 186 | #endif |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 187 | #ifdef CFG_SYS_SICRL |
| 188 | __raw_writel(CFG_SYS_SICRL, &im->sysconf.sicrl); |
Kumar Gala | e522143 | 2006-01-11 11:12:57 -0600 | [diff] [blame] | 189 | #endif |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 190 | #ifdef CFG_SYS_GPR1 |
| 191 | __raw_writel(CFG_SYS_GPR1, &im->sysconf.gpr1); |
Gerlando Falauto | fe201cb | 2012-10-10 22:13:08 +0000 | [diff] [blame] | 192 | #endif |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 193 | #ifdef CFG_SYS_DDRCDR /* DDR control driver register */ |
| 194 | __raw_writel(CFG_SYS_DDRCDR, &im->sysconf.ddrcdr); |
Dave Liu | e740c46 | 2006-12-07 21:13:15 +0800 | [diff] [blame] | 195 | #endif |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 196 | #ifdef CFG_SYS_OBIR /* Output buffer impedance register */ |
| 197 | __raw_writel(CFG_SYS_OBIR, &im->sysconf.obir); |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 198 | #endif |
Dave Liu | e740c46 | 2006-12-07 21:13:15 +0800 | [diff] [blame] | 199 | |
Heiko Schocher | 3b07a13 | 2020-02-03 10:23:53 +0100 | [diff] [blame] | 200 | #if !defined(CONFIG_PINCTRL) |
Dave Liu | e732e9c | 2006-11-03 12:11:15 -0600 | [diff] [blame] | 201 | #ifdef CONFIG_QE |
| 202 | /* Config QE ioports */ |
| 203 | config_qe_ioports(); |
| 204 | #endif |
Heiko Schocher | 3b07a13 | 2020-02-03 10:23:53 +0100 | [diff] [blame] | 205 | #endif |
| 206 | |
Becky Bruce | 0d4cee1 | 2010-06-17 11:37:20 -0500 | [diff] [blame] | 207 | /* Set up preliminary BR/OR regs */ |
| 208 | init_early_memctl_regs(); |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 209 | |
Becky Bruce | 0d4cee1 | 2010-06-17 11:37:20 -0500 | [diff] [blame] | 210 | /* Local Access window setup */ |
Tom Rini | 364d002 | 2023-01-10 11:19:45 -0500 | [diff] [blame] | 211 | #if defined(CFG_SYS_LBLAWBAR0_PRELIM) && defined(CFG_SYS_LBLAWAR0_PRELIM) |
| 212 | im->sysconf.lblaw[0].bar = CFG_SYS_LBLAWBAR0_PRELIM; |
| 213 | im->sysconf.lblaw[0].ar = CFG_SYS_LBLAWAR0_PRELIM; |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 214 | #else |
Tom Rini | 364d002 | 2023-01-10 11:19:45 -0500 | [diff] [blame] | 215 | #error CFG_SYS_LBLAWBAR0_PRELIM & CFG_SYS_LBLAWAR0_PRELIM must be defined |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 216 | #endif |
| 217 | |
Tom Rini | 364d002 | 2023-01-10 11:19:45 -0500 | [diff] [blame] | 218 | #if defined(CFG_SYS_LBLAWBAR1_PRELIM) && defined(CFG_SYS_LBLAWAR1_PRELIM) |
| 219 | im->sysconf.lblaw[1].bar = CFG_SYS_LBLAWBAR1_PRELIM; |
| 220 | im->sysconf.lblaw[1].ar = CFG_SYS_LBLAWAR1_PRELIM; |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 221 | #endif |
Tom Rini | 364d002 | 2023-01-10 11:19:45 -0500 | [diff] [blame] | 222 | #if defined(CFG_SYS_LBLAWBAR2_PRELIM) && defined(CFG_SYS_LBLAWAR2_PRELIM) |
| 223 | im->sysconf.lblaw[2].bar = CFG_SYS_LBLAWBAR2_PRELIM; |
| 224 | im->sysconf.lblaw[2].ar = CFG_SYS_LBLAWAR2_PRELIM; |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 225 | #endif |
Tom Rini | 364d002 | 2023-01-10 11:19:45 -0500 | [diff] [blame] | 226 | #if defined(CFG_SYS_LBLAWBAR3_PRELIM) && defined(CFG_SYS_LBLAWAR3_PRELIM) |
| 227 | im->sysconf.lblaw[3].bar = CFG_SYS_LBLAWBAR3_PRELIM; |
| 228 | im->sysconf.lblaw[3].ar = CFG_SYS_LBLAWAR3_PRELIM; |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 229 | #endif |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 230 | } |
| 231 | |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 232 | int cpu_init_r (void) |
| 233 | { |
Dave Liu | e732e9c | 2006-11-03 12:11:15 -0600 | [diff] [blame] | 234 | #ifdef CONFIG_QE |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 235 | uint qe_base = CONFIG_SYS_IMMR + 0x00100000; /* QE immr base */ |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 236 | |
Dave Liu | e732e9c | 2006-11-03 12:11:15 -0600 | [diff] [blame] | 237 | qe_init(qe_base); |
| 238 | qe_reset(); |
| 239 | #endif |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 240 | return 0; |
| 241 | } |
Dave Liu | ebd35f8 | 2007-06-25 10:41:56 +0800 | [diff] [blame] | 242 | |
Nick Spence | 56fd3c2 | 2008-08-28 14:09:19 -0700 | [diff] [blame] | 243 | /* |
| 244 | * Print out the bus arbiter event |
| 245 | */ |
| 246 | #if defined(CONFIG_DISPLAY_AER_FULL) |
| 247 | static int print_83xx_arb_event(int force) |
| 248 | { |
| 249 | static char* event[] = { |
| 250 | "Address Time Out", |
| 251 | "Data Time Out", |
| 252 | "Address Only Transfer Type", |
| 253 | "External Control Word Transfer Type", |
| 254 | "Reserved Transfer Type", |
| 255 | "Transfer Error", |
| 256 | "reserved", |
| 257 | "reserved" |
| 258 | }; |
| 259 | static char* master[] = { |
| 260 | "e300 Core Data Transaction", |
| 261 | "reserved", |
| 262 | "e300 Core Instruction Fetch", |
| 263 | "reserved", |
| 264 | "TSEC1", |
| 265 | "TSEC2", |
| 266 | "USB MPH", |
| 267 | "USB DR", |
| 268 | "Encryption Core", |
| 269 | "I2C Boot Sequencer", |
| 270 | "JTAG", |
| 271 | "reserved", |
| 272 | "eSDHC", |
| 273 | "PCI1", |
| 274 | "PCI2", |
| 275 | "DMA", |
| 276 | "QUICC Engine 00", |
| 277 | "QUICC Engine 01", |
| 278 | "QUICC Engine 10", |
| 279 | "QUICC Engine 11", |
| 280 | "reserved", |
| 281 | "reserved", |
| 282 | "reserved", |
| 283 | "reserved", |
| 284 | "SATA1", |
| 285 | "SATA2", |
| 286 | "SATA3", |
| 287 | "SATA4", |
| 288 | "reserved", |
| 289 | "PCI Express 1", |
| 290 | "PCI Express 2", |
| 291 | "TDM-DMAC" |
| 292 | }; |
| 293 | static char *transfer[] = { |
| 294 | "Address-only, Clean Block", |
| 295 | "Address-only, lwarx reservation set", |
| 296 | "Single-beat or Burst write", |
| 297 | "reserved", |
| 298 | "Address-only, Flush Block", |
| 299 | "reserved", |
| 300 | "Burst write", |
| 301 | "reserved", |
| 302 | "Address-only, sync", |
| 303 | "Address-only, tlbsync", |
| 304 | "Single-beat or Burst read", |
| 305 | "Single-beat or Burst read", |
| 306 | "Address-only, Kill Block", |
| 307 | "Address-only, icbi", |
| 308 | "Burst read", |
| 309 | "reserved", |
| 310 | "Address-only, eieio", |
| 311 | "reserved", |
| 312 | "Single-beat write", |
| 313 | "reserved", |
| 314 | "ecowx - Illegal single-beat write", |
| 315 | "reserved", |
| 316 | "reserved", |
| 317 | "reserved", |
| 318 | "Address-only, TLB Invalidate", |
| 319 | "reserved", |
| 320 | "Single-beat or Burst read", |
| 321 | "reserved", |
| 322 | "eciwx - Illegal single-beat read", |
| 323 | "reserved", |
| 324 | "Burst read", |
| 325 | "reserved" |
| 326 | }; |
| 327 | |
Simon Glass | 387a1f2 | 2012-12-13 20:48:57 +0000 | [diff] [blame] | 328 | int etype = (gd->arch.arbiter_event_attributes & AEATR_EVENT) |
Wolfgang Denk | ec7fbf5 | 2013-10-04 17:43:24 +0200 | [diff] [blame] | 329 | >> AEATR_EVENT_SHIFT; |
Simon Glass | 387a1f2 | 2012-12-13 20:48:57 +0000 | [diff] [blame] | 330 | int mstr_id = (gd->arch.arbiter_event_attributes & AEATR_MSTR_ID) |
Wolfgang Denk | ec7fbf5 | 2013-10-04 17:43:24 +0200 | [diff] [blame] | 331 | >> AEATR_MSTR_ID_SHIFT; |
Simon Glass | 387a1f2 | 2012-12-13 20:48:57 +0000 | [diff] [blame] | 332 | int tbst = (gd->arch.arbiter_event_attributes & AEATR_TBST) |
Wolfgang Denk | ec7fbf5 | 2013-10-04 17:43:24 +0200 | [diff] [blame] | 333 | >> AEATR_TBST_SHIFT; |
Simon Glass | 387a1f2 | 2012-12-13 20:48:57 +0000 | [diff] [blame] | 334 | int tsize = (gd->arch.arbiter_event_attributes & AEATR_TSIZE) |
Wolfgang Denk | ec7fbf5 | 2013-10-04 17:43:24 +0200 | [diff] [blame] | 335 | >> AEATR_TSIZE_SHIFT; |
Simon Glass | 387a1f2 | 2012-12-13 20:48:57 +0000 | [diff] [blame] | 336 | int ttype = (gd->arch.arbiter_event_attributes & AEATR_TTYPE) |
Wolfgang Denk | ec7fbf5 | 2013-10-04 17:43:24 +0200 | [diff] [blame] | 337 | >> AEATR_TTYPE_SHIFT; |
Nick Spence | 56fd3c2 | 2008-08-28 14:09:19 -0700 | [diff] [blame] | 338 | |
Simon Glass | 387a1f2 | 2012-12-13 20:48:57 +0000 | [diff] [blame] | 339 | if (!force && !gd->arch.arbiter_event_address) |
Nick Spence | 56fd3c2 | 2008-08-28 14:09:19 -0700 | [diff] [blame] | 340 | return 0; |
| 341 | |
| 342 | puts("Arbiter Event Status:\n"); |
Simon Glass | 387a1f2 | 2012-12-13 20:48:57 +0000 | [diff] [blame] | 343 | printf(" Event Address: 0x%08lX\n", |
| 344 | gd->arch.arbiter_event_address); |
Nick Spence | 56fd3c2 | 2008-08-28 14:09:19 -0700 | [diff] [blame] | 345 | printf(" Event Type: 0x%1x = %s\n", etype, event[etype]); |
| 346 | printf(" Master ID: 0x%02x = %s\n", mstr_id, master[mstr_id]); |
| 347 | printf(" Transfer Size: 0x%1x = %d bytes\n", (tbst<<3) | tsize, |
| 348 | tbst ? (tsize ? tsize : 8) : 16 + 8 * tsize); |
| 349 | printf(" Transfer Type: 0x%02x = %s\n", ttype, transfer[ttype]); |
| 350 | |
Simon Glass | 387a1f2 | 2012-12-13 20:48:57 +0000 | [diff] [blame] | 351 | return gd->arch.arbiter_event_address; |
Nick Spence | 56fd3c2 | 2008-08-28 14:09:19 -0700 | [diff] [blame] | 352 | } |
| 353 | |
| 354 | #elif defined(CONFIG_DISPLAY_AER_BRIEF) |
| 355 | |
| 356 | static int print_83xx_arb_event(int force) |
| 357 | { |
Simon Glass | 387a1f2 | 2012-12-13 20:48:57 +0000 | [diff] [blame] | 358 | if (!force && !gd->arch.arbiter_event_address) |
Nick Spence | 56fd3c2 | 2008-08-28 14:09:19 -0700 | [diff] [blame] | 359 | return 0; |
| 360 | |
| 361 | printf("Arbiter Event Status: AEATR=0x%08lX, AEADR=0x%08lX\n", |
Simon Glass | 387a1f2 | 2012-12-13 20:48:57 +0000 | [diff] [blame] | 362 | gd->arch.arbiter_event_attributes, |
| 363 | gd->arch.arbiter_event_address); |
Nick Spence | 56fd3c2 | 2008-08-28 14:09:19 -0700 | [diff] [blame] | 364 | |
Simon Glass | 387a1f2 | 2012-12-13 20:48:57 +0000 | [diff] [blame] | 365 | return gd->arch.arbiter_event_address; |
Nick Spence | 56fd3c2 | 2008-08-28 14:09:19 -0700 | [diff] [blame] | 366 | } |
| 367 | #endif /* CONFIG_DISPLAY_AER_xxxx */ |
| 368 | |
Mario Six | 28fbefa | 2018-08-06 10:23:45 +0200 | [diff] [blame] | 369 | #ifndef CONFIG_CPU_MPC83XX |
Dave Liu | ebd35f8 | 2007-06-25 10:41:56 +0800 | [diff] [blame] | 370 | /* |
| 371 | * Figure out the cause of the reset |
| 372 | */ |
| 373 | int prt_83xx_rsr(void) |
| 374 | { |
| 375 | static struct { |
| 376 | ulong mask; |
| 377 | char *desc; |
| 378 | } bits[] = { |
| 379 | { |
| 380 | RSR_SWSR, "Software Soft"}, { |
| 381 | RSR_SWHR, "Software Hard"}, { |
| 382 | RSR_JSRS, "JTAG Soft"}, { |
| 383 | RSR_CSHR, "Check Stop"}, { |
| 384 | RSR_SWRS, "Software Watchdog"}, { |
| 385 | RSR_BMRS, "Bus Monitor"}, { |
| 386 | RSR_SRS, "External/Internal Soft"}, { |
| 387 | RSR_HRS, "External/Internal Hard"} |
| 388 | }; |
Robert P. J. Day | 0c91159 | 2016-05-23 06:49:21 -0400 | [diff] [blame] | 389 | static int n = ARRAY_SIZE(bits); |
Simon Glass | 4d6eaa3 | 2012-12-13 20:48:56 +0000 | [diff] [blame] | 390 | ulong rsr = gd->arch.reset_status; |
Dave Liu | ebd35f8 | 2007-06-25 10:41:56 +0800 | [diff] [blame] | 391 | int i; |
| 392 | char *sep; |
| 393 | |
| 394 | puts("Reset Status:"); |
| 395 | |
| 396 | sep = " "; |
| 397 | for (i = 0; i < n; i++) |
| 398 | if (rsr & bits[i].mask) { |
| 399 | printf("%s%s", sep, bits[i].desc); |
| 400 | sep = ", "; |
| 401 | } |
Nick Spence | 56fd3c2 | 2008-08-28 14:09:19 -0700 | [diff] [blame] | 402 | puts("\n"); |
| 403 | |
| 404 | #if defined(CONFIG_DISPLAY_AER_FULL) || defined(CONFIG_DISPLAY_AER_BRIEF) |
| 405 | print_83xx_arb_event(rsr & RSR_BMRS); |
| 406 | #endif |
| 407 | puts("\n"); |
| 408 | |
Dave Liu | ebd35f8 | 2007-06-25 10:41:56 +0800 | [diff] [blame] | 409 | return 0; |
| 410 | } |
Mario Six | 28fbefa | 2018-08-06 10:23:45 +0200 | [diff] [blame] | 411 | #endif |