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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Eran Liberty9095d4a2005-07-28 10:08:46 -05002/*
Vivek Mahajan288f7fb2009-05-25 17:23:16 +05303 * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
Eran Liberty9095d4a2005-07-28 10:08:46 -05004 */
5
6#include <common.h>
7#include <mpc83xx.h>
8#include <ioports.h>
Vivek Mahajan288f7fb2009-05-25 17:23:16 +05309#include <asm/io.h>
Simon Glass156283f2017-03-28 10:27:27 -060010#include <asm/processor.h>
Kim Phillips328040a2009-09-25 18:19:44 -050011#ifdef CONFIG_USB_EHCI_FSL
Mateusz Kulikowski3add69e2016-03-31 23:12:23 +020012#include <usb/ehci-ci.h>
Vivek Mahajan288f7fb2009-05-25 17:23:16 +053013#endif
Eran Liberty9095d4a2005-07-28 10:08:46 -050014
Wolfgang Denk6405a152006-03-31 18:32:53 +020015DECLARE_GLOBAL_DATA_PTR;
16
Dave Liue732e9c2006-11-03 12:11:15 -060017#ifdef CONFIG_QE
18extern qe_iop_conf_t qe_iop_conf_tab[];
19extern void qe_config_iopin(u8 port, u8 pin, int dir,
20 int open_drain, int assign);
21extern void qe_init(uint qe_base);
22extern void qe_reset(void);
23
24static void config_qe_ioports(void)
25{
26 u8 port, pin;
27 int dir, open_drain, assign;
28 int i;
29
30 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
31 port = qe_iop_conf_tab[i].port;
32 pin = qe_iop_conf_tab[i].pin;
33 dir = qe_iop_conf_tab[i].dir;
34 open_drain = qe_iop_conf_tab[i].open_drain;
35 assign = qe_iop_conf_tab[i].assign;
36 qe_config_iopin(port, pin, dir, open_drain, assign);
37 }
38}
39#endif
40
Eran Liberty9095d4a2005-07-28 10:08:46 -050041/*
42 * Breathe some life into the CPU...
43 *
44 * Set up the memory map,
45 * initialize a bunch of registers,
46 * initialize the UPM's
47 */
48void cpu_init_f (volatile immap_t * im)
49{
Kim Phillips328040a2009-09-25 18:19:44 -050050 __be32 acr_mask =
51#ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
Kim Phillips8d5fa6a2010-05-19 17:06:46 -050052 ACR_PIPE_DEP |
Timur Tabi054838e2006-10-31 18:44:42 -060053#endif
Kim Phillips328040a2009-09-25 18:19:44 -050054#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
Kim Phillips8d5fa6a2010-05-19 17:06:46 -050055 ACR_RPTCNT |
Kim Phillips19a91de2008-01-16 12:06:16 -060056#endif
Heiko Schocher5318b082010-01-07 08:56:00 +010057#ifdef CONFIG_SYS_ACR_APARK /* Arbiter address parking mode */
Kim Phillips8d5fa6a2010-05-19 17:06:46 -050058 ACR_APARK |
Heiko Schocher5318b082010-01-07 08:56:00 +010059#endif
60#ifdef CONFIG_SYS_ACR_PARKM /* Arbiter parking master */
Kim Phillips8d5fa6a2010-05-19 17:06:46 -050061 ACR_PARKM |
Heiko Schocher5318b082010-01-07 08:56:00 +010062#endif
Kim Phillips328040a2009-09-25 18:19:44 -050063 0;
64 __be32 acr_val =
65#ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
66 (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) |
67#endif
68#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
69 (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT) |
70#endif
Heiko Schocher5318b082010-01-07 08:56:00 +010071#ifdef CONFIG_SYS_ACR_APARK /* Arbiter address parking mode */
72 (CONFIG_SYS_ACR_APARK << ACR_APARK_SHIFT) |
73#endif
74#ifdef CONFIG_SYS_ACR_PARKM /* Arbiter parking master */
75 (CONFIG_SYS_ACR_PARKM << ACR_PARKM_SHIFT) |
76#endif
Kim Phillips328040a2009-09-25 18:19:44 -050077 0;
78 __be32 spcr_mask =
79#ifdef CONFIG_SYS_SPCR_OPT /* Optimize transactions between CSB and other dev */
Kim Phillips8d5fa6a2010-05-19 17:06:46 -050080 SPCR_OPT |
Kim Phillips328040a2009-09-25 18:19:44 -050081#endif
82#ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
Kim Phillips8d5fa6a2010-05-19 17:06:46 -050083 SPCR_TSECEP |
Kim Phillips328040a2009-09-25 18:19:44 -050084#endif
85#ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
Kim Phillips8d5fa6a2010-05-19 17:06:46 -050086 SPCR_TSEC1EP |
Kim Phillips328040a2009-09-25 18:19:44 -050087#endif
88#ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
Kim Phillips8d5fa6a2010-05-19 17:06:46 -050089 SPCR_TSEC2EP |
Kim Phillips328040a2009-09-25 18:19:44 -050090#endif
91 0;
92 __be32 spcr_val =
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020093#ifdef CONFIG_SYS_SPCR_OPT
Kim Phillips328040a2009-09-25 18:19:44 -050094 (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT) |
Michael Barkowski06e2e192008-03-20 13:15:34 -040095#endif
Kim Phillips328040a2009-09-25 18:19:44 -050096#ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
97 (CONFIG_SYS_SPCR_TSECEP << SPCR_TSECEP_SHIFT) |
Kim Phillips19a91de2008-01-16 12:06:16 -060098#endif
Kim Phillips328040a2009-09-25 18:19:44 -050099#ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
100 (CONFIG_SYS_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT) |
Timur Tabi054838e2006-10-31 18:44:42 -0600101#endif
Kim Phillips328040a2009-09-25 18:19:44 -0500102#ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
103 (CONFIG_SYS_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT) |
Kim Phillips19a91de2008-01-16 12:06:16 -0600104#endif
Kim Phillips328040a2009-09-25 18:19:44 -0500105 0;
106 __be32 sccr_mask =
107#ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
Kim Phillips8d5fa6a2010-05-19 17:06:46 -0500108 SCCR_ENCCM |
Kim Phillips19a91de2008-01-16 12:06:16 -0600109#endif
Kim Phillips328040a2009-09-25 18:19:44 -0500110#ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
Kim Phillips8d5fa6a2010-05-19 17:06:46 -0500111 SCCR_PCICM |
Kim Phillips19a91de2008-01-16 12:06:16 -0600112#endif
Ilya Yanoka4f3ed32010-09-17 23:41:47 +0200113#ifdef CONFIG_SYS_SCCR_PCIEXP1CM /* PCIE1 clock mode */
114 SCCR_PCIEXP1CM |
115#endif
116#ifdef CONFIG_SYS_SCCR_PCIEXP2CM /* PCIE2 clock mode */
117 SCCR_PCIEXP2CM |
118#endif
Kim Phillips328040a2009-09-25 18:19:44 -0500119#ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
Kim Phillips8d5fa6a2010-05-19 17:06:46 -0500120 SCCR_TSECCM |
Timur Tabi054838e2006-10-31 18:44:42 -0600121#endif
Kim Phillips328040a2009-09-25 18:19:44 -0500122#ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
Kim Phillips8d5fa6a2010-05-19 17:06:46 -0500123 SCCR_TSEC1CM |
Timur Tabi054838e2006-10-31 18:44:42 -0600124#endif
Kim Phillips328040a2009-09-25 18:19:44 -0500125#ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
Kim Phillips8d5fa6a2010-05-19 17:06:46 -0500126 SCCR_TSEC2CM |
Kumar Gala15c3f692007-02-27 23:51:42 -0600127#endif
Kim Phillips328040a2009-09-25 18:19:44 -0500128#ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
Kim Phillips8d5fa6a2010-05-19 17:06:46 -0500129 SCCR_TSEC1ON |
Timur Tabi0b2deff2007-07-03 13:04:34 -0500130#endif
Kim Phillips328040a2009-09-25 18:19:44 -0500131#ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
Kim Phillips8d5fa6a2010-05-19 17:06:46 -0500132 SCCR_TSEC2ON |
Timur Tabi0b2deff2007-07-03 13:04:34 -0500133#endif
Kim Phillips328040a2009-09-25 18:19:44 -0500134#ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
Kim Phillips8d5fa6a2010-05-19 17:06:46 -0500135 SCCR_USBMPHCM |
Kumar Gala15c3f692007-02-27 23:51:42 -0600136#endif
Kim Phillips328040a2009-09-25 18:19:44 -0500137#ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
Kim Phillips8d5fa6a2010-05-19 17:06:46 -0500138 SCCR_USBDRCM |
Kumar Gala15c3f692007-02-27 23:51:42 -0600139#endif
Kim Phillips328040a2009-09-25 18:19:44 -0500140#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
Kim Phillips8d5fa6a2010-05-19 17:06:46 -0500141 SCCR_SATACM |
Timur Tabi054838e2006-10-31 18:44:42 -0600142#endif
Kim Phillips328040a2009-09-25 18:19:44 -0500143 0;
144 __be32 sccr_val =
145#ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
146 (CONFIG_SYS_SCCR_ENCCM << SCCR_ENCCM_SHIFT) |
147#endif
148#ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
149 (CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT) |
150#endif
Ilya Yanoka4f3ed32010-09-17 23:41:47 +0200151#ifdef CONFIG_SYS_SCCR_PCIEXP1CM /* PCIE1 clock mode */
152 (CONFIG_SYS_SCCR_PCIEXP1CM << SCCR_PCIEXP1CM_SHIFT) |
153#endif
154#ifdef CONFIG_SYS_SCCR_PCIEXP2CM /* PCIE2 clock mode */
155 (CONFIG_SYS_SCCR_PCIEXP2CM << SCCR_PCIEXP2CM_SHIFT) |
156#endif
Kim Phillips328040a2009-09-25 18:19:44 -0500157#ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
158 (CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT) |
159#endif
160#ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
161 (CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) |
162#endif
163#ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
164 (CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) |
165#endif
166#ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
167 (CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) |
168#endif
169#ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
170 (CONFIG_SYS_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) |
171#endif
172#ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
173 (CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) |
174#endif
175#ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
176 (CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) |
177#endif
178#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
179 (CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) |
180#endif
181 0;
Peter Korsgaard2a483ee2009-12-08 22:20:34 +0100182 __be32 lcrr_mask =
183#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
184 LCRR_DBYP |
185#endif
186#ifdef CONFIG_SYS_LCRR_EADC /* external address delay */
187 LCRR_EADC |
188#endif
189#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
190 LCRR_CLKDIV |
191#endif
192 0;
193 __be32 lcrr_val =
194#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
195 CONFIG_SYS_LCRR_DBYP |
196#endif
197#ifdef CONFIG_SYS_LCRR_EADC
198 CONFIG_SYS_LCRR_EADC |
199#endif
200#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
201 CONFIG_SYS_LCRR_CLKDIV |
202#endif
203 0;
Kim Phillips328040a2009-09-25 18:19:44 -0500204
205 /* Pointer is writable since we allocated a register for it */
206 gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
207
mario.six@gdsys.cc85df7b42017-01-17 08:33:48 +0100208 /* global data region was cleared in start.S */
Kim Phillips328040a2009-09-25 18:19:44 -0500209
210 /* system performance tweaking */
211 clrsetbits_be32(&im->arbiter.acr, acr_mask, acr_val);
212
213 clrsetbits_be32(&im->sysconf.spcr, spcr_mask, spcr_val);
214
215 clrsetbits_be32(&im->clk.sccr, sccr_mask, sccr_val);
Timur Tabi054838e2006-10-31 18:44:42 -0600216
Eran Liberty9095d4a2005-07-28 10:08:46 -0500217 /* RSR - Reset Status Register - clear all status (4.6.1.3) */
Simon Glass4d6eaa32012-12-13 20:48:56 +0000218 gd->arch.reset_status = __raw_readl(&im->reset.rsr);
Kim Phillips328040a2009-09-25 18:19:44 -0500219 __raw_writel(~(RSR_RES), &im->reset.rsr);
Eran Liberty9095d4a2005-07-28 10:08:46 -0500220
Nick Spence56fd3c22008-08-28 14:09:19 -0700221 /* AER - Arbiter Event Register - store status */
Simon Glass387a1f22012-12-13 20:48:57 +0000222 gd->arch.arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr);
223 gd->arch.arbiter_event_address = __raw_readl(&im->arbiter.aeadr);
Nick Spence56fd3c22008-08-28 14:09:19 -0700224
Eran Liberty9095d4a2005-07-28 10:08:46 -0500225 /*
226 * RMR - Reset Mode Register
227 * contains checkstop reset enable (4.6.1.4)
228 */
Kim Phillips328040a2009-09-25 18:19:44 -0500229 __raw_writel(RMR_CSRE & (1<<RMR_CSRE_SHIFT), &im->reset.rmr);
Eran Liberty9095d4a2005-07-28 10:08:46 -0500230
Peter Korsgaard2a483ee2009-12-08 22:20:34 +0100231 /* LCRR - Clock Ratio Register (10.3.1.16)
232 * write, read, and isync per MPC8379ERM rev.1 CLKDEV field description
233 */
Becky Bruce0d4cee12010-06-17 11:37:20 -0500234 clrsetbits_be32(&im->im_lbc.lcrr, lcrr_mask, lcrr_val);
235 __raw_readl(&im->im_lbc.lcrr);
Peter Korsgaard2a483ee2009-12-08 22:20:34 +0100236 isync();
237
Kim Phillips328040a2009-09-25 18:19:44 -0500238 /* Enable Time Base & Decrementer ( so we will have udelay() )*/
239 setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
Eran Liberty9095d4a2005-07-28 10:08:46 -0500240
241 /* System General Purpose Register */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200242#ifdef CONFIG_SYS_SICRH
Peter Tyser72f2d392009-05-22 17:23:25 -0500243#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC8313)
Andre Schwarzcea66482008-06-23 11:40:56 +0200244 /* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
Kim Phillips328040a2009-09-25 18:19:44 -0500245 __raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH,
246 &im->sysconf.sicrh);
Andre Schwarzcea66482008-06-23 11:40:56 +0200247#else
Kim Phillips328040a2009-09-25 18:19:44 -0500248 __raw_writel(CONFIG_SYS_SICRH, &im->sysconf.sicrh);
Kumar Galae5221432006-01-11 11:12:57 -0600249#endif
Andre Schwarzcea66482008-06-23 11:40:56 +0200250#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200251#ifdef CONFIG_SYS_SICRL
Kim Phillips328040a2009-09-25 18:19:44 -0500252 __raw_writel(CONFIG_SYS_SICRL, &im->sysconf.sicrl);
Kumar Galae5221432006-01-11 11:12:57 -0600253#endif
Gerlando Falautofe201cb2012-10-10 22:13:08 +0000254#ifdef CONFIG_SYS_GPR1
255 __raw_writel(CONFIG_SYS_GPR1, &im->sysconf.gpr1);
256#endif
Kim Phillips328040a2009-09-25 18:19:44 -0500257#ifdef CONFIG_SYS_DDRCDR /* DDR control driver register */
258 __raw_writel(CONFIG_SYS_DDRCDR, &im->sysconf.ddrcdr);
Dave Liue740c462006-12-07 21:13:15 +0800259#endif
Kim Phillips328040a2009-09-25 18:19:44 -0500260#ifdef CONFIG_SYS_OBIR /* Output buffer impedance register */
261 __raw_writel(CONFIG_SYS_OBIR, &im->sysconf.obir);
Dave Liub19ecd32007-09-18 12:37:57 +0800262#endif
Dave Liue740c462006-12-07 21:13:15 +0800263
Dave Liue732e9c2006-11-03 12:11:15 -0600264#ifdef CONFIG_QE
265 /* Config QE ioports */
266 config_qe_ioports();
267#endif
Becky Bruce0d4cee12010-06-17 11:37:20 -0500268 /* Set up preliminary BR/OR regs */
269 init_early_memctl_regs();
Eran Liberty9095d4a2005-07-28 10:08:46 -0500270
Becky Bruce0d4cee12010-06-17 11:37:20 -0500271 /* Local Access window setup */
272#if defined(CONFIG_SYS_LBLAWBAR0_PRELIM) && defined(CONFIG_SYS_LBLAWAR0_PRELIM)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200273 im->sysconf.lblaw[0].bar = CONFIG_SYS_LBLAWBAR0_PRELIM;
274 im->sysconf.lblaw[0].ar = CONFIG_SYS_LBLAWAR0_PRELIM;
Eran Liberty9095d4a2005-07-28 10:08:46 -0500275#else
Becky Bruce0d4cee12010-06-17 11:37:20 -0500276#error CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined
Eran Liberty9095d4a2005-07-28 10:08:46 -0500277#endif
278
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200279#if defined(CONFIG_SYS_LBLAWBAR1_PRELIM) && defined(CONFIG_SYS_LBLAWAR1_PRELIM)
280 im->sysconf.lblaw[1].bar = CONFIG_SYS_LBLAWBAR1_PRELIM;
281 im->sysconf.lblaw[1].ar = CONFIG_SYS_LBLAWAR1_PRELIM;
Eran Liberty9095d4a2005-07-28 10:08:46 -0500282#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200283#if defined(CONFIG_SYS_LBLAWBAR2_PRELIM) && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
284 im->sysconf.lblaw[2].bar = CONFIG_SYS_LBLAWBAR2_PRELIM;
285 im->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2_PRELIM;
Eran Liberty9095d4a2005-07-28 10:08:46 -0500286#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200287#if defined(CONFIG_SYS_LBLAWBAR3_PRELIM) && defined(CONFIG_SYS_LBLAWAR3_PRELIM)
288 im->sysconf.lblaw[3].bar = CONFIG_SYS_LBLAWBAR3_PRELIM;
289 im->sysconf.lblaw[3].ar = CONFIG_SYS_LBLAWAR3_PRELIM;
Eran Liberty9095d4a2005-07-28 10:08:46 -0500290#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200291#if defined(CONFIG_SYS_LBLAWBAR4_PRELIM) && defined(CONFIG_SYS_LBLAWAR4_PRELIM)
292 im->sysconf.lblaw[4].bar = CONFIG_SYS_LBLAWBAR4_PRELIM;
293 im->sysconf.lblaw[4].ar = CONFIG_SYS_LBLAWAR4_PRELIM;
Eran Liberty9095d4a2005-07-28 10:08:46 -0500294#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200295#if defined(CONFIG_SYS_LBLAWBAR5_PRELIM) && defined(CONFIG_SYS_LBLAWAR5_PRELIM)
296 im->sysconf.lblaw[5].bar = CONFIG_SYS_LBLAWBAR5_PRELIM;
297 im->sysconf.lblaw[5].ar = CONFIG_SYS_LBLAWAR5_PRELIM;
Eran Liberty9095d4a2005-07-28 10:08:46 -0500298#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200299#if defined(CONFIG_SYS_LBLAWBAR6_PRELIM) && defined(CONFIG_SYS_LBLAWAR6_PRELIM)
300 im->sysconf.lblaw[6].bar = CONFIG_SYS_LBLAWBAR6_PRELIM;
301 im->sysconf.lblaw[6].ar = CONFIG_SYS_LBLAWAR6_PRELIM;
Eran Liberty9095d4a2005-07-28 10:08:46 -0500302#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200303#if defined(CONFIG_SYS_LBLAWBAR7_PRELIM) && defined(CONFIG_SYS_LBLAWAR7_PRELIM)
304 im->sysconf.lblaw[7].bar = CONFIG_SYS_LBLAWBAR7_PRELIM;
305 im->sysconf.lblaw[7].ar = CONFIG_SYS_LBLAWAR7_PRELIM;
Eran Liberty9095d4a2005-07-28 10:08:46 -0500306#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200307#ifdef CONFIG_SYS_GPIO1_PRELIM
308 im->gpio[0].dat = CONFIG_SYS_GPIO1_DAT;
309 im->gpio[0].dir = CONFIG_SYS_GPIO1_DIR;
Kumar Galaab7ec4f2006-01-11 11:21:14 -0600310#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200311#ifdef CONFIG_SYS_GPIO2_PRELIM
312 im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT;
313 im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR;
Kumar Galaab7ec4f2006-01-11 11:21:14 -0600314#endif
Kim Phillips17ab5a92011-04-01 16:53:18 -0500315#if defined(CONFIG_USB_EHCI_FSL) && defined(CONFIG_MPC831x)
Vivek Mahajan288f7fb2009-05-25 17:23:16 +0530316 uint32_t temp;
ramneek mehresh16b08062013-09-12 16:35:49 +0530317 struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
Vivek Mahajan288f7fb2009-05-25 17:23:16 +0530318
319 /* Configure interface. */
Vivek Mahajan2d421c12009-06-24 10:08:40 +0530320 setbits_be32(&ehci->control, REFSEL_16MHZ | UTMI_PHY_EN);
Vivek Mahajan288f7fb2009-05-25 17:23:16 +0530321
322 /* Wait for clock to stabilize */
323 do {
Kim Phillips328040a2009-09-25 18:19:44 -0500324 temp = __raw_readl(&ehci->control);
Vivek Mahajan288f7fb2009-05-25 17:23:16 +0530325 udelay(1000);
326 } while (!(temp & PHY_CLK_VALID));
327#endif
Eran Liberty9095d4a2005-07-28 10:08:46 -0500328}
329
Eran Liberty9095d4a2005-07-28 10:08:46 -0500330int cpu_init_r (void)
331{
Dave Liue732e9c2006-11-03 12:11:15 -0600332#ifdef CONFIG_QE
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200333 uint qe_base = CONFIG_SYS_IMMR + 0x00100000; /* QE immr base */
Kim Phillips328040a2009-09-25 18:19:44 -0500334
Dave Liue732e9c2006-11-03 12:11:15 -0600335 qe_init(qe_base);
336 qe_reset();
337#endif
Eran Liberty9095d4a2005-07-28 10:08:46 -0500338 return 0;
339}
Dave Liuebd35f82007-06-25 10:41:56 +0800340
Nick Spence56fd3c22008-08-28 14:09:19 -0700341/*
342 * Print out the bus arbiter event
343 */
344#if defined(CONFIG_DISPLAY_AER_FULL)
345static int print_83xx_arb_event(int force)
346{
347 static char* event[] = {
348 "Address Time Out",
349 "Data Time Out",
350 "Address Only Transfer Type",
351 "External Control Word Transfer Type",
352 "Reserved Transfer Type",
353 "Transfer Error",
354 "reserved",
355 "reserved"
356 };
357 static char* master[] = {
358 "e300 Core Data Transaction",
359 "reserved",
360 "e300 Core Instruction Fetch",
361 "reserved",
362 "TSEC1",
363 "TSEC2",
364 "USB MPH",
365 "USB DR",
366 "Encryption Core",
367 "I2C Boot Sequencer",
368 "JTAG",
369 "reserved",
370 "eSDHC",
371 "PCI1",
372 "PCI2",
373 "DMA",
374 "QUICC Engine 00",
375 "QUICC Engine 01",
376 "QUICC Engine 10",
377 "QUICC Engine 11",
378 "reserved",
379 "reserved",
380 "reserved",
381 "reserved",
382 "SATA1",
383 "SATA2",
384 "SATA3",
385 "SATA4",
386 "reserved",
387 "PCI Express 1",
388 "PCI Express 2",
389 "TDM-DMAC"
390 };
391 static char *transfer[] = {
392 "Address-only, Clean Block",
393 "Address-only, lwarx reservation set",
394 "Single-beat or Burst write",
395 "reserved",
396 "Address-only, Flush Block",
397 "reserved",
398 "Burst write",
399 "reserved",
400 "Address-only, sync",
401 "Address-only, tlbsync",
402 "Single-beat or Burst read",
403 "Single-beat or Burst read",
404 "Address-only, Kill Block",
405 "Address-only, icbi",
406 "Burst read",
407 "reserved",
408 "Address-only, eieio",
409 "reserved",
410 "Single-beat write",
411 "reserved",
412 "ecowx - Illegal single-beat write",
413 "reserved",
414 "reserved",
415 "reserved",
416 "Address-only, TLB Invalidate",
417 "reserved",
418 "Single-beat or Burst read",
419 "reserved",
420 "eciwx - Illegal single-beat read",
421 "reserved",
422 "Burst read",
423 "reserved"
424 };
425
Simon Glass387a1f22012-12-13 20:48:57 +0000426 int etype = (gd->arch.arbiter_event_attributes & AEATR_EVENT)
Wolfgang Denkec7fbf52013-10-04 17:43:24 +0200427 >> AEATR_EVENT_SHIFT;
Simon Glass387a1f22012-12-13 20:48:57 +0000428 int mstr_id = (gd->arch.arbiter_event_attributes & AEATR_MSTR_ID)
Wolfgang Denkec7fbf52013-10-04 17:43:24 +0200429 >> AEATR_MSTR_ID_SHIFT;
Simon Glass387a1f22012-12-13 20:48:57 +0000430 int tbst = (gd->arch.arbiter_event_attributes & AEATR_TBST)
Wolfgang Denkec7fbf52013-10-04 17:43:24 +0200431 >> AEATR_TBST_SHIFT;
Simon Glass387a1f22012-12-13 20:48:57 +0000432 int tsize = (gd->arch.arbiter_event_attributes & AEATR_TSIZE)
Wolfgang Denkec7fbf52013-10-04 17:43:24 +0200433 >> AEATR_TSIZE_SHIFT;
Simon Glass387a1f22012-12-13 20:48:57 +0000434 int ttype = (gd->arch.arbiter_event_attributes & AEATR_TTYPE)
Wolfgang Denkec7fbf52013-10-04 17:43:24 +0200435 >> AEATR_TTYPE_SHIFT;
Nick Spence56fd3c22008-08-28 14:09:19 -0700436
Simon Glass387a1f22012-12-13 20:48:57 +0000437 if (!force && !gd->arch.arbiter_event_address)
Nick Spence56fd3c22008-08-28 14:09:19 -0700438 return 0;
439
440 puts("Arbiter Event Status:\n");
Simon Glass387a1f22012-12-13 20:48:57 +0000441 printf(" Event Address: 0x%08lX\n",
442 gd->arch.arbiter_event_address);
Nick Spence56fd3c22008-08-28 14:09:19 -0700443 printf(" Event Type: 0x%1x = %s\n", etype, event[etype]);
444 printf(" Master ID: 0x%02x = %s\n", mstr_id, master[mstr_id]);
445 printf(" Transfer Size: 0x%1x = %d bytes\n", (tbst<<3) | tsize,
446 tbst ? (tsize ? tsize : 8) : 16 + 8 * tsize);
447 printf(" Transfer Type: 0x%02x = %s\n", ttype, transfer[ttype]);
448
Simon Glass387a1f22012-12-13 20:48:57 +0000449 return gd->arch.arbiter_event_address;
Nick Spence56fd3c22008-08-28 14:09:19 -0700450}
451
452#elif defined(CONFIG_DISPLAY_AER_BRIEF)
453
454static int print_83xx_arb_event(int force)
455{
Simon Glass387a1f22012-12-13 20:48:57 +0000456 if (!force && !gd->arch.arbiter_event_address)
Nick Spence56fd3c22008-08-28 14:09:19 -0700457 return 0;
458
459 printf("Arbiter Event Status: AEATR=0x%08lX, AEADR=0x%08lX\n",
Simon Glass387a1f22012-12-13 20:48:57 +0000460 gd->arch.arbiter_event_attributes,
461 gd->arch.arbiter_event_address);
Nick Spence56fd3c22008-08-28 14:09:19 -0700462
Simon Glass387a1f22012-12-13 20:48:57 +0000463 return gd->arch.arbiter_event_address;
Nick Spence56fd3c22008-08-28 14:09:19 -0700464}
465#endif /* CONFIG_DISPLAY_AER_xxxx */
466
Mario Six28fbefa2018-08-06 10:23:45 +0200467#ifndef CONFIG_CPU_MPC83XX
Dave Liuebd35f82007-06-25 10:41:56 +0800468/*
469 * Figure out the cause of the reset
470 */
471int prt_83xx_rsr(void)
472{
473 static struct {
474 ulong mask;
475 char *desc;
476 } bits[] = {
477 {
478 RSR_SWSR, "Software Soft"}, {
479 RSR_SWHR, "Software Hard"}, {
480 RSR_JSRS, "JTAG Soft"}, {
481 RSR_CSHR, "Check Stop"}, {
482 RSR_SWRS, "Software Watchdog"}, {
483 RSR_BMRS, "Bus Monitor"}, {
484 RSR_SRS, "External/Internal Soft"}, {
485 RSR_HRS, "External/Internal Hard"}
486 };
Robert P. J. Day0c911592016-05-23 06:49:21 -0400487 static int n = ARRAY_SIZE(bits);
Simon Glass4d6eaa32012-12-13 20:48:56 +0000488 ulong rsr = gd->arch.reset_status;
Dave Liuebd35f82007-06-25 10:41:56 +0800489 int i;
490 char *sep;
491
492 puts("Reset Status:");
493
494 sep = " ";
495 for (i = 0; i < n; i++)
496 if (rsr & bits[i].mask) {
497 printf("%s%s", sep, bits[i].desc);
498 sep = ", ";
499 }
Nick Spence56fd3c22008-08-28 14:09:19 -0700500 puts("\n");
501
502#if defined(CONFIG_DISPLAY_AER_FULL) || defined(CONFIG_DISPLAY_AER_BRIEF)
503 print_83xx_arb_event(rsr & RSR_BMRS);
504#endif
505 puts("\n");
506
Dave Liuebd35f82007-06-25 10:41:56 +0800507 return 0;
508}
Mario Six28fbefa2018-08-06 10:23:45 +0200509#endif