Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 2 | /* |
Vivek Mahajan | 288f7fb | 2009-05-25 17:23:16 +0530 | [diff] [blame] | 3 | * Copyright (C) 2004-2009 Freescale Semiconductor, Inc. |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <common.h> |
| 7 | #include <mpc83xx.h> |
| 8 | #include <ioports.h> |
Vivek Mahajan | 288f7fb | 2009-05-25 17:23:16 +0530 | [diff] [blame] | 9 | #include <asm/io.h> |
Simon Glass | 156283f | 2017-03-28 10:27:27 -0600 | [diff] [blame] | 10 | #include <asm/processor.h> |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 11 | #ifdef CONFIG_USB_EHCI_FSL |
Mateusz Kulikowski | 3add69e | 2016-03-31 23:12:23 +0200 | [diff] [blame] | 12 | #include <usb/ehci-ci.h> |
Vivek Mahajan | 288f7fb | 2009-05-25 17:23:16 +0530 | [diff] [blame] | 13 | #endif |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 14 | |
Wolfgang Denk | 6405a15 | 2006-03-31 18:32:53 +0200 | [diff] [blame] | 15 | DECLARE_GLOBAL_DATA_PTR; |
| 16 | |
Dave Liu | e732e9c | 2006-11-03 12:11:15 -0600 | [diff] [blame] | 17 | #ifdef CONFIG_QE |
| 18 | extern qe_iop_conf_t qe_iop_conf_tab[]; |
| 19 | extern void qe_config_iopin(u8 port, u8 pin, int dir, |
| 20 | int open_drain, int assign); |
| 21 | extern void qe_init(uint qe_base); |
| 22 | extern void qe_reset(void); |
| 23 | |
| 24 | static void config_qe_ioports(void) |
| 25 | { |
| 26 | u8 port, pin; |
| 27 | int dir, open_drain, assign; |
| 28 | int i; |
| 29 | |
| 30 | for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { |
| 31 | port = qe_iop_conf_tab[i].port; |
| 32 | pin = qe_iop_conf_tab[i].pin; |
| 33 | dir = qe_iop_conf_tab[i].dir; |
| 34 | open_drain = qe_iop_conf_tab[i].open_drain; |
| 35 | assign = qe_iop_conf_tab[i].assign; |
| 36 | qe_config_iopin(port, pin, dir, open_drain, assign); |
| 37 | } |
| 38 | } |
| 39 | #endif |
| 40 | |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 41 | /* |
| 42 | * Breathe some life into the CPU... |
| 43 | * |
| 44 | * Set up the memory map, |
| 45 | * initialize a bunch of registers, |
| 46 | * initialize the UPM's |
| 47 | */ |
| 48 | void cpu_init_f (volatile immap_t * im) |
| 49 | { |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 50 | __be32 acr_mask = |
| 51 | #ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */ |
Kim Phillips | 8d5fa6a | 2010-05-19 17:06:46 -0500 | [diff] [blame] | 52 | ACR_PIPE_DEP | |
Timur Tabi | 054838e | 2006-10-31 18:44:42 -0600 | [diff] [blame] | 53 | #endif |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 54 | #ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */ |
Kim Phillips | 8d5fa6a | 2010-05-19 17:06:46 -0500 | [diff] [blame] | 55 | ACR_RPTCNT | |
Kim Phillips | 19a91de | 2008-01-16 12:06:16 -0600 | [diff] [blame] | 56 | #endif |
Heiko Schocher | 5318b08 | 2010-01-07 08:56:00 +0100 | [diff] [blame] | 57 | #ifdef CONFIG_SYS_ACR_APARK /* Arbiter address parking mode */ |
Kim Phillips | 8d5fa6a | 2010-05-19 17:06:46 -0500 | [diff] [blame] | 58 | ACR_APARK | |
Heiko Schocher | 5318b08 | 2010-01-07 08:56:00 +0100 | [diff] [blame] | 59 | #endif |
| 60 | #ifdef CONFIG_SYS_ACR_PARKM /* Arbiter parking master */ |
Kim Phillips | 8d5fa6a | 2010-05-19 17:06:46 -0500 | [diff] [blame] | 61 | ACR_PARKM | |
Heiko Schocher | 5318b08 | 2010-01-07 08:56:00 +0100 | [diff] [blame] | 62 | #endif |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 63 | 0; |
| 64 | __be32 acr_val = |
| 65 | #ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */ |
| 66 | (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) | |
| 67 | #endif |
| 68 | #ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */ |
| 69 | (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT) | |
| 70 | #endif |
Heiko Schocher | 5318b08 | 2010-01-07 08:56:00 +0100 | [diff] [blame] | 71 | #ifdef CONFIG_SYS_ACR_APARK /* Arbiter address parking mode */ |
| 72 | (CONFIG_SYS_ACR_APARK << ACR_APARK_SHIFT) | |
| 73 | #endif |
| 74 | #ifdef CONFIG_SYS_ACR_PARKM /* Arbiter parking master */ |
| 75 | (CONFIG_SYS_ACR_PARKM << ACR_PARKM_SHIFT) | |
| 76 | #endif |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 77 | 0; |
| 78 | __be32 spcr_mask = |
| 79 | #ifdef CONFIG_SYS_SPCR_OPT /* Optimize transactions between CSB and other dev */ |
Kim Phillips | 8d5fa6a | 2010-05-19 17:06:46 -0500 | [diff] [blame] | 80 | SPCR_OPT | |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 81 | #endif |
| 82 | #ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */ |
Kim Phillips | 8d5fa6a | 2010-05-19 17:06:46 -0500 | [diff] [blame] | 83 | SPCR_TSECEP | |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 84 | #endif |
| 85 | #ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */ |
Kim Phillips | 8d5fa6a | 2010-05-19 17:06:46 -0500 | [diff] [blame] | 86 | SPCR_TSEC1EP | |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 87 | #endif |
| 88 | #ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */ |
Kim Phillips | 8d5fa6a | 2010-05-19 17:06:46 -0500 | [diff] [blame] | 89 | SPCR_TSEC2EP | |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 90 | #endif |
| 91 | 0; |
| 92 | __be32 spcr_val = |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 93 | #ifdef CONFIG_SYS_SPCR_OPT |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 94 | (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT) | |
Michael Barkowski | 06e2e19 | 2008-03-20 13:15:34 -0400 | [diff] [blame] | 95 | #endif |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 96 | #ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */ |
| 97 | (CONFIG_SYS_SPCR_TSECEP << SPCR_TSECEP_SHIFT) | |
Kim Phillips | 19a91de | 2008-01-16 12:06:16 -0600 | [diff] [blame] | 98 | #endif |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 99 | #ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */ |
| 100 | (CONFIG_SYS_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT) | |
Timur Tabi | 054838e | 2006-10-31 18:44:42 -0600 | [diff] [blame] | 101 | #endif |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 102 | #ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */ |
| 103 | (CONFIG_SYS_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT) | |
Kim Phillips | 19a91de | 2008-01-16 12:06:16 -0600 | [diff] [blame] | 104 | #endif |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 105 | 0; |
| 106 | __be32 sccr_mask = |
| 107 | #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */ |
Kim Phillips | 8d5fa6a | 2010-05-19 17:06:46 -0500 | [diff] [blame] | 108 | SCCR_ENCCM | |
Kim Phillips | 19a91de | 2008-01-16 12:06:16 -0600 | [diff] [blame] | 109 | #endif |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 110 | #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */ |
Kim Phillips | 8d5fa6a | 2010-05-19 17:06:46 -0500 | [diff] [blame] | 111 | SCCR_PCICM | |
Kim Phillips | 19a91de | 2008-01-16 12:06:16 -0600 | [diff] [blame] | 112 | #endif |
Ilya Yanok | a4f3ed3 | 2010-09-17 23:41:47 +0200 | [diff] [blame] | 113 | #ifdef CONFIG_SYS_SCCR_PCIEXP1CM /* PCIE1 clock mode */ |
| 114 | SCCR_PCIEXP1CM | |
| 115 | #endif |
| 116 | #ifdef CONFIG_SYS_SCCR_PCIEXP2CM /* PCIE2 clock mode */ |
| 117 | SCCR_PCIEXP2CM | |
| 118 | #endif |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 119 | #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */ |
Kim Phillips | 8d5fa6a | 2010-05-19 17:06:46 -0500 | [diff] [blame] | 120 | SCCR_TSECCM | |
Timur Tabi | 054838e | 2006-10-31 18:44:42 -0600 | [diff] [blame] | 121 | #endif |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 122 | #ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */ |
Kim Phillips | 8d5fa6a | 2010-05-19 17:06:46 -0500 | [diff] [blame] | 123 | SCCR_TSEC1CM | |
Timur Tabi | 054838e | 2006-10-31 18:44:42 -0600 | [diff] [blame] | 124 | #endif |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 125 | #ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */ |
Kim Phillips | 8d5fa6a | 2010-05-19 17:06:46 -0500 | [diff] [blame] | 126 | SCCR_TSEC2CM | |
Kumar Gala | 15c3f69 | 2007-02-27 23:51:42 -0600 | [diff] [blame] | 127 | #endif |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 128 | #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */ |
Kim Phillips | 8d5fa6a | 2010-05-19 17:06:46 -0500 | [diff] [blame] | 129 | SCCR_TSEC1ON | |
Timur Tabi | 0b2deff | 2007-07-03 13:04:34 -0500 | [diff] [blame] | 130 | #endif |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 131 | #ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */ |
Kim Phillips | 8d5fa6a | 2010-05-19 17:06:46 -0500 | [diff] [blame] | 132 | SCCR_TSEC2ON | |
Timur Tabi | 0b2deff | 2007-07-03 13:04:34 -0500 | [diff] [blame] | 133 | #endif |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 134 | #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */ |
Kim Phillips | 8d5fa6a | 2010-05-19 17:06:46 -0500 | [diff] [blame] | 135 | SCCR_USBMPHCM | |
Kumar Gala | 15c3f69 | 2007-02-27 23:51:42 -0600 | [diff] [blame] | 136 | #endif |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 137 | #ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */ |
Kim Phillips | 8d5fa6a | 2010-05-19 17:06:46 -0500 | [diff] [blame] | 138 | SCCR_USBDRCM | |
Kumar Gala | 15c3f69 | 2007-02-27 23:51:42 -0600 | [diff] [blame] | 139 | #endif |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 140 | #ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */ |
Kim Phillips | 8d5fa6a | 2010-05-19 17:06:46 -0500 | [diff] [blame] | 141 | SCCR_SATACM | |
Timur Tabi | 054838e | 2006-10-31 18:44:42 -0600 | [diff] [blame] | 142 | #endif |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 143 | 0; |
| 144 | __be32 sccr_val = |
| 145 | #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */ |
| 146 | (CONFIG_SYS_SCCR_ENCCM << SCCR_ENCCM_SHIFT) | |
| 147 | #endif |
| 148 | #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */ |
| 149 | (CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT) | |
| 150 | #endif |
Ilya Yanok | a4f3ed3 | 2010-09-17 23:41:47 +0200 | [diff] [blame] | 151 | #ifdef CONFIG_SYS_SCCR_PCIEXP1CM /* PCIE1 clock mode */ |
| 152 | (CONFIG_SYS_SCCR_PCIEXP1CM << SCCR_PCIEXP1CM_SHIFT) | |
| 153 | #endif |
| 154 | #ifdef CONFIG_SYS_SCCR_PCIEXP2CM /* PCIE2 clock mode */ |
| 155 | (CONFIG_SYS_SCCR_PCIEXP2CM << SCCR_PCIEXP2CM_SHIFT) | |
| 156 | #endif |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 157 | #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */ |
| 158 | (CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT) | |
| 159 | #endif |
| 160 | #ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */ |
| 161 | (CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) | |
| 162 | #endif |
| 163 | #ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */ |
| 164 | (CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) | |
| 165 | #endif |
| 166 | #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */ |
| 167 | (CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) | |
| 168 | #endif |
| 169 | #ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */ |
| 170 | (CONFIG_SYS_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) | |
| 171 | #endif |
| 172 | #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */ |
| 173 | (CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) | |
| 174 | #endif |
| 175 | #ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */ |
| 176 | (CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) | |
| 177 | #endif |
| 178 | #ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */ |
| 179 | (CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) | |
| 180 | #endif |
| 181 | 0; |
Peter Korsgaard | 2a483ee | 2009-12-08 22:20:34 +0100 | [diff] [blame] | 182 | __be32 lcrr_mask = |
| 183 | #ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */ |
| 184 | LCRR_DBYP | |
| 185 | #endif |
| 186 | #ifdef CONFIG_SYS_LCRR_EADC /* external address delay */ |
| 187 | LCRR_EADC | |
| 188 | #endif |
| 189 | #ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */ |
| 190 | LCRR_CLKDIV | |
| 191 | #endif |
| 192 | 0; |
| 193 | __be32 lcrr_val = |
| 194 | #ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */ |
| 195 | CONFIG_SYS_LCRR_DBYP | |
| 196 | #endif |
| 197 | #ifdef CONFIG_SYS_LCRR_EADC |
| 198 | CONFIG_SYS_LCRR_EADC | |
| 199 | #endif |
| 200 | #ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */ |
| 201 | CONFIG_SYS_LCRR_CLKDIV | |
| 202 | #endif |
| 203 | 0; |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 204 | |
| 205 | /* Pointer is writable since we allocated a register for it */ |
| 206 | gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); |
| 207 | |
mario.six@gdsys.cc | 85df7b4 | 2017-01-17 08:33:48 +0100 | [diff] [blame] | 208 | /* global data region was cleared in start.S */ |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 209 | |
| 210 | /* system performance tweaking */ |
| 211 | clrsetbits_be32(&im->arbiter.acr, acr_mask, acr_val); |
| 212 | |
| 213 | clrsetbits_be32(&im->sysconf.spcr, spcr_mask, spcr_val); |
| 214 | |
| 215 | clrsetbits_be32(&im->clk.sccr, sccr_mask, sccr_val); |
Timur Tabi | 054838e | 2006-10-31 18:44:42 -0600 | [diff] [blame] | 216 | |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 217 | /* RSR - Reset Status Register - clear all status (4.6.1.3) */ |
Simon Glass | 4d6eaa3 | 2012-12-13 20:48:56 +0000 | [diff] [blame] | 218 | gd->arch.reset_status = __raw_readl(&im->reset.rsr); |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 219 | __raw_writel(~(RSR_RES), &im->reset.rsr); |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 220 | |
Nick Spence | 56fd3c2 | 2008-08-28 14:09:19 -0700 | [diff] [blame] | 221 | /* AER - Arbiter Event Register - store status */ |
Simon Glass | 387a1f2 | 2012-12-13 20:48:57 +0000 | [diff] [blame] | 222 | gd->arch.arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr); |
| 223 | gd->arch.arbiter_event_address = __raw_readl(&im->arbiter.aeadr); |
Nick Spence | 56fd3c2 | 2008-08-28 14:09:19 -0700 | [diff] [blame] | 224 | |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 225 | /* |
| 226 | * RMR - Reset Mode Register |
| 227 | * contains checkstop reset enable (4.6.1.4) |
| 228 | */ |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 229 | __raw_writel(RMR_CSRE & (1<<RMR_CSRE_SHIFT), &im->reset.rmr); |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 230 | |
Peter Korsgaard | 2a483ee | 2009-12-08 22:20:34 +0100 | [diff] [blame] | 231 | /* LCRR - Clock Ratio Register (10.3.1.16) |
| 232 | * write, read, and isync per MPC8379ERM rev.1 CLKDEV field description |
| 233 | */ |
Becky Bruce | 0d4cee1 | 2010-06-17 11:37:20 -0500 | [diff] [blame] | 234 | clrsetbits_be32(&im->im_lbc.lcrr, lcrr_mask, lcrr_val); |
| 235 | __raw_readl(&im->im_lbc.lcrr); |
Peter Korsgaard | 2a483ee | 2009-12-08 22:20:34 +0100 | [diff] [blame] | 236 | isync(); |
| 237 | |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 238 | /* Enable Time Base & Decrementer ( so we will have udelay() )*/ |
| 239 | setbits_be32(&im->sysconf.spcr, SPCR_TBEN); |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 240 | |
| 241 | /* System General Purpose Register */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 242 | #ifdef CONFIG_SYS_SICRH |
Peter Tyser | 72f2d39 | 2009-05-22 17:23:25 -0500 | [diff] [blame] | 243 | #if defined(CONFIG_MPC834x) || defined(CONFIG_MPC8313) |
Andre Schwarz | cea6648 | 2008-06-23 11:40:56 +0200 | [diff] [blame] | 244 | /* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */ |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 245 | __raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH, |
| 246 | &im->sysconf.sicrh); |
Andre Schwarz | cea6648 | 2008-06-23 11:40:56 +0200 | [diff] [blame] | 247 | #else |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 248 | __raw_writel(CONFIG_SYS_SICRH, &im->sysconf.sicrh); |
Kumar Gala | e522143 | 2006-01-11 11:12:57 -0600 | [diff] [blame] | 249 | #endif |
Andre Schwarz | cea6648 | 2008-06-23 11:40:56 +0200 | [diff] [blame] | 250 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 251 | #ifdef CONFIG_SYS_SICRL |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 252 | __raw_writel(CONFIG_SYS_SICRL, &im->sysconf.sicrl); |
Kumar Gala | e522143 | 2006-01-11 11:12:57 -0600 | [diff] [blame] | 253 | #endif |
Gerlando Falauto | fe201cb | 2012-10-10 22:13:08 +0000 | [diff] [blame] | 254 | #ifdef CONFIG_SYS_GPR1 |
| 255 | __raw_writel(CONFIG_SYS_GPR1, &im->sysconf.gpr1); |
| 256 | #endif |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 257 | #ifdef CONFIG_SYS_DDRCDR /* DDR control driver register */ |
| 258 | __raw_writel(CONFIG_SYS_DDRCDR, &im->sysconf.ddrcdr); |
Dave Liu | e740c46 | 2006-12-07 21:13:15 +0800 | [diff] [blame] | 259 | #endif |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 260 | #ifdef CONFIG_SYS_OBIR /* Output buffer impedance register */ |
| 261 | __raw_writel(CONFIG_SYS_OBIR, &im->sysconf.obir); |
Dave Liu | b19ecd3 | 2007-09-18 12:37:57 +0800 | [diff] [blame] | 262 | #endif |
Dave Liu | e740c46 | 2006-12-07 21:13:15 +0800 | [diff] [blame] | 263 | |
Dave Liu | e732e9c | 2006-11-03 12:11:15 -0600 | [diff] [blame] | 264 | #ifdef CONFIG_QE |
| 265 | /* Config QE ioports */ |
| 266 | config_qe_ioports(); |
| 267 | #endif |
Becky Bruce | 0d4cee1 | 2010-06-17 11:37:20 -0500 | [diff] [blame] | 268 | /* Set up preliminary BR/OR regs */ |
| 269 | init_early_memctl_regs(); |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 270 | |
Becky Bruce | 0d4cee1 | 2010-06-17 11:37:20 -0500 | [diff] [blame] | 271 | /* Local Access window setup */ |
| 272 | #if defined(CONFIG_SYS_LBLAWBAR0_PRELIM) && defined(CONFIG_SYS_LBLAWAR0_PRELIM) |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 273 | im->sysconf.lblaw[0].bar = CONFIG_SYS_LBLAWBAR0_PRELIM; |
| 274 | im->sysconf.lblaw[0].ar = CONFIG_SYS_LBLAWAR0_PRELIM; |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 275 | #else |
Becky Bruce | 0d4cee1 | 2010-06-17 11:37:20 -0500 | [diff] [blame] | 276 | #error CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 277 | #endif |
| 278 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 279 | #if defined(CONFIG_SYS_LBLAWBAR1_PRELIM) && defined(CONFIG_SYS_LBLAWAR1_PRELIM) |
| 280 | im->sysconf.lblaw[1].bar = CONFIG_SYS_LBLAWBAR1_PRELIM; |
| 281 | im->sysconf.lblaw[1].ar = CONFIG_SYS_LBLAWAR1_PRELIM; |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 282 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 283 | #if defined(CONFIG_SYS_LBLAWBAR2_PRELIM) && defined(CONFIG_SYS_LBLAWAR2_PRELIM) |
| 284 | im->sysconf.lblaw[2].bar = CONFIG_SYS_LBLAWBAR2_PRELIM; |
| 285 | im->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2_PRELIM; |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 286 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 287 | #if defined(CONFIG_SYS_LBLAWBAR3_PRELIM) && defined(CONFIG_SYS_LBLAWAR3_PRELIM) |
| 288 | im->sysconf.lblaw[3].bar = CONFIG_SYS_LBLAWBAR3_PRELIM; |
| 289 | im->sysconf.lblaw[3].ar = CONFIG_SYS_LBLAWAR3_PRELIM; |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 290 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 291 | #if defined(CONFIG_SYS_LBLAWBAR4_PRELIM) && defined(CONFIG_SYS_LBLAWAR4_PRELIM) |
| 292 | im->sysconf.lblaw[4].bar = CONFIG_SYS_LBLAWBAR4_PRELIM; |
| 293 | im->sysconf.lblaw[4].ar = CONFIG_SYS_LBLAWAR4_PRELIM; |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 294 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 295 | #if defined(CONFIG_SYS_LBLAWBAR5_PRELIM) && defined(CONFIG_SYS_LBLAWAR5_PRELIM) |
| 296 | im->sysconf.lblaw[5].bar = CONFIG_SYS_LBLAWBAR5_PRELIM; |
| 297 | im->sysconf.lblaw[5].ar = CONFIG_SYS_LBLAWAR5_PRELIM; |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 298 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 299 | #if defined(CONFIG_SYS_LBLAWBAR6_PRELIM) && defined(CONFIG_SYS_LBLAWAR6_PRELIM) |
| 300 | im->sysconf.lblaw[6].bar = CONFIG_SYS_LBLAWBAR6_PRELIM; |
| 301 | im->sysconf.lblaw[6].ar = CONFIG_SYS_LBLAWAR6_PRELIM; |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 302 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 303 | #if defined(CONFIG_SYS_LBLAWBAR7_PRELIM) && defined(CONFIG_SYS_LBLAWAR7_PRELIM) |
| 304 | im->sysconf.lblaw[7].bar = CONFIG_SYS_LBLAWBAR7_PRELIM; |
| 305 | im->sysconf.lblaw[7].ar = CONFIG_SYS_LBLAWAR7_PRELIM; |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 306 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 307 | #ifdef CONFIG_SYS_GPIO1_PRELIM |
| 308 | im->gpio[0].dat = CONFIG_SYS_GPIO1_DAT; |
| 309 | im->gpio[0].dir = CONFIG_SYS_GPIO1_DIR; |
Kumar Gala | ab7ec4f | 2006-01-11 11:21:14 -0600 | [diff] [blame] | 310 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 311 | #ifdef CONFIG_SYS_GPIO2_PRELIM |
| 312 | im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT; |
| 313 | im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR; |
Kumar Gala | ab7ec4f | 2006-01-11 11:21:14 -0600 | [diff] [blame] | 314 | #endif |
Kim Phillips | 17ab5a9 | 2011-04-01 16:53:18 -0500 | [diff] [blame] | 315 | #if defined(CONFIG_USB_EHCI_FSL) && defined(CONFIG_MPC831x) |
Vivek Mahajan | 288f7fb | 2009-05-25 17:23:16 +0530 | [diff] [blame] | 316 | uint32_t temp; |
ramneek mehresh | 16b0806 | 2013-09-12 16:35:49 +0530 | [diff] [blame] | 317 | struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR; |
Vivek Mahajan | 288f7fb | 2009-05-25 17:23:16 +0530 | [diff] [blame] | 318 | |
| 319 | /* Configure interface. */ |
Vivek Mahajan | 2d421c1 | 2009-06-24 10:08:40 +0530 | [diff] [blame] | 320 | setbits_be32(&ehci->control, REFSEL_16MHZ | UTMI_PHY_EN); |
Vivek Mahajan | 288f7fb | 2009-05-25 17:23:16 +0530 | [diff] [blame] | 321 | |
| 322 | /* Wait for clock to stabilize */ |
| 323 | do { |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 324 | temp = __raw_readl(&ehci->control); |
Vivek Mahajan | 288f7fb | 2009-05-25 17:23:16 +0530 | [diff] [blame] | 325 | udelay(1000); |
| 326 | } while (!(temp & PHY_CLK_VALID)); |
| 327 | #endif |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 328 | } |
| 329 | |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 330 | int cpu_init_r (void) |
| 331 | { |
Dave Liu | e732e9c | 2006-11-03 12:11:15 -0600 | [diff] [blame] | 332 | #ifdef CONFIG_QE |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 333 | uint qe_base = CONFIG_SYS_IMMR + 0x00100000; /* QE immr base */ |
Kim Phillips | 328040a | 2009-09-25 18:19:44 -0500 | [diff] [blame] | 334 | |
Dave Liu | e732e9c | 2006-11-03 12:11:15 -0600 | [diff] [blame] | 335 | qe_init(qe_base); |
| 336 | qe_reset(); |
| 337 | #endif |
Eran Liberty | 9095d4a | 2005-07-28 10:08:46 -0500 | [diff] [blame] | 338 | return 0; |
| 339 | } |
Dave Liu | ebd35f8 | 2007-06-25 10:41:56 +0800 | [diff] [blame] | 340 | |
Nick Spence | 56fd3c2 | 2008-08-28 14:09:19 -0700 | [diff] [blame] | 341 | /* |
| 342 | * Print out the bus arbiter event |
| 343 | */ |
| 344 | #if defined(CONFIG_DISPLAY_AER_FULL) |
| 345 | static int print_83xx_arb_event(int force) |
| 346 | { |
| 347 | static char* event[] = { |
| 348 | "Address Time Out", |
| 349 | "Data Time Out", |
| 350 | "Address Only Transfer Type", |
| 351 | "External Control Word Transfer Type", |
| 352 | "Reserved Transfer Type", |
| 353 | "Transfer Error", |
| 354 | "reserved", |
| 355 | "reserved" |
| 356 | }; |
| 357 | static char* master[] = { |
| 358 | "e300 Core Data Transaction", |
| 359 | "reserved", |
| 360 | "e300 Core Instruction Fetch", |
| 361 | "reserved", |
| 362 | "TSEC1", |
| 363 | "TSEC2", |
| 364 | "USB MPH", |
| 365 | "USB DR", |
| 366 | "Encryption Core", |
| 367 | "I2C Boot Sequencer", |
| 368 | "JTAG", |
| 369 | "reserved", |
| 370 | "eSDHC", |
| 371 | "PCI1", |
| 372 | "PCI2", |
| 373 | "DMA", |
| 374 | "QUICC Engine 00", |
| 375 | "QUICC Engine 01", |
| 376 | "QUICC Engine 10", |
| 377 | "QUICC Engine 11", |
| 378 | "reserved", |
| 379 | "reserved", |
| 380 | "reserved", |
| 381 | "reserved", |
| 382 | "SATA1", |
| 383 | "SATA2", |
| 384 | "SATA3", |
| 385 | "SATA4", |
| 386 | "reserved", |
| 387 | "PCI Express 1", |
| 388 | "PCI Express 2", |
| 389 | "TDM-DMAC" |
| 390 | }; |
| 391 | static char *transfer[] = { |
| 392 | "Address-only, Clean Block", |
| 393 | "Address-only, lwarx reservation set", |
| 394 | "Single-beat or Burst write", |
| 395 | "reserved", |
| 396 | "Address-only, Flush Block", |
| 397 | "reserved", |
| 398 | "Burst write", |
| 399 | "reserved", |
| 400 | "Address-only, sync", |
| 401 | "Address-only, tlbsync", |
| 402 | "Single-beat or Burst read", |
| 403 | "Single-beat or Burst read", |
| 404 | "Address-only, Kill Block", |
| 405 | "Address-only, icbi", |
| 406 | "Burst read", |
| 407 | "reserved", |
| 408 | "Address-only, eieio", |
| 409 | "reserved", |
| 410 | "Single-beat write", |
| 411 | "reserved", |
| 412 | "ecowx - Illegal single-beat write", |
| 413 | "reserved", |
| 414 | "reserved", |
| 415 | "reserved", |
| 416 | "Address-only, TLB Invalidate", |
| 417 | "reserved", |
| 418 | "Single-beat or Burst read", |
| 419 | "reserved", |
| 420 | "eciwx - Illegal single-beat read", |
| 421 | "reserved", |
| 422 | "Burst read", |
| 423 | "reserved" |
| 424 | }; |
| 425 | |
Simon Glass | 387a1f2 | 2012-12-13 20:48:57 +0000 | [diff] [blame] | 426 | int etype = (gd->arch.arbiter_event_attributes & AEATR_EVENT) |
Wolfgang Denk | ec7fbf5 | 2013-10-04 17:43:24 +0200 | [diff] [blame] | 427 | >> AEATR_EVENT_SHIFT; |
Simon Glass | 387a1f2 | 2012-12-13 20:48:57 +0000 | [diff] [blame] | 428 | int mstr_id = (gd->arch.arbiter_event_attributes & AEATR_MSTR_ID) |
Wolfgang Denk | ec7fbf5 | 2013-10-04 17:43:24 +0200 | [diff] [blame] | 429 | >> AEATR_MSTR_ID_SHIFT; |
Simon Glass | 387a1f2 | 2012-12-13 20:48:57 +0000 | [diff] [blame] | 430 | int tbst = (gd->arch.arbiter_event_attributes & AEATR_TBST) |
Wolfgang Denk | ec7fbf5 | 2013-10-04 17:43:24 +0200 | [diff] [blame] | 431 | >> AEATR_TBST_SHIFT; |
Simon Glass | 387a1f2 | 2012-12-13 20:48:57 +0000 | [diff] [blame] | 432 | int tsize = (gd->arch.arbiter_event_attributes & AEATR_TSIZE) |
Wolfgang Denk | ec7fbf5 | 2013-10-04 17:43:24 +0200 | [diff] [blame] | 433 | >> AEATR_TSIZE_SHIFT; |
Simon Glass | 387a1f2 | 2012-12-13 20:48:57 +0000 | [diff] [blame] | 434 | int ttype = (gd->arch.arbiter_event_attributes & AEATR_TTYPE) |
Wolfgang Denk | ec7fbf5 | 2013-10-04 17:43:24 +0200 | [diff] [blame] | 435 | >> AEATR_TTYPE_SHIFT; |
Nick Spence | 56fd3c2 | 2008-08-28 14:09:19 -0700 | [diff] [blame] | 436 | |
Simon Glass | 387a1f2 | 2012-12-13 20:48:57 +0000 | [diff] [blame] | 437 | if (!force && !gd->arch.arbiter_event_address) |
Nick Spence | 56fd3c2 | 2008-08-28 14:09:19 -0700 | [diff] [blame] | 438 | return 0; |
| 439 | |
| 440 | puts("Arbiter Event Status:\n"); |
Simon Glass | 387a1f2 | 2012-12-13 20:48:57 +0000 | [diff] [blame] | 441 | printf(" Event Address: 0x%08lX\n", |
| 442 | gd->arch.arbiter_event_address); |
Nick Spence | 56fd3c2 | 2008-08-28 14:09:19 -0700 | [diff] [blame] | 443 | printf(" Event Type: 0x%1x = %s\n", etype, event[etype]); |
| 444 | printf(" Master ID: 0x%02x = %s\n", mstr_id, master[mstr_id]); |
| 445 | printf(" Transfer Size: 0x%1x = %d bytes\n", (tbst<<3) | tsize, |
| 446 | tbst ? (tsize ? tsize : 8) : 16 + 8 * tsize); |
| 447 | printf(" Transfer Type: 0x%02x = %s\n", ttype, transfer[ttype]); |
| 448 | |
Simon Glass | 387a1f2 | 2012-12-13 20:48:57 +0000 | [diff] [blame] | 449 | return gd->arch.arbiter_event_address; |
Nick Spence | 56fd3c2 | 2008-08-28 14:09:19 -0700 | [diff] [blame] | 450 | } |
| 451 | |
| 452 | #elif defined(CONFIG_DISPLAY_AER_BRIEF) |
| 453 | |
| 454 | static int print_83xx_arb_event(int force) |
| 455 | { |
Simon Glass | 387a1f2 | 2012-12-13 20:48:57 +0000 | [diff] [blame] | 456 | if (!force && !gd->arch.arbiter_event_address) |
Nick Spence | 56fd3c2 | 2008-08-28 14:09:19 -0700 | [diff] [blame] | 457 | return 0; |
| 458 | |
| 459 | printf("Arbiter Event Status: AEATR=0x%08lX, AEADR=0x%08lX\n", |
Simon Glass | 387a1f2 | 2012-12-13 20:48:57 +0000 | [diff] [blame] | 460 | gd->arch.arbiter_event_attributes, |
| 461 | gd->arch.arbiter_event_address); |
Nick Spence | 56fd3c2 | 2008-08-28 14:09:19 -0700 | [diff] [blame] | 462 | |
Simon Glass | 387a1f2 | 2012-12-13 20:48:57 +0000 | [diff] [blame] | 463 | return gd->arch.arbiter_event_address; |
Nick Spence | 56fd3c2 | 2008-08-28 14:09:19 -0700 | [diff] [blame] | 464 | } |
| 465 | #endif /* CONFIG_DISPLAY_AER_xxxx */ |
| 466 | |
Mario Six | 28fbefa | 2018-08-06 10:23:45 +0200 | [diff] [blame^] | 467 | #ifndef CONFIG_CPU_MPC83XX |
Dave Liu | ebd35f8 | 2007-06-25 10:41:56 +0800 | [diff] [blame] | 468 | /* |
| 469 | * Figure out the cause of the reset |
| 470 | */ |
| 471 | int prt_83xx_rsr(void) |
| 472 | { |
| 473 | static struct { |
| 474 | ulong mask; |
| 475 | char *desc; |
| 476 | } bits[] = { |
| 477 | { |
| 478 | RSR_SWSR, "Software Soft"}, { |
| 479 | RSR_SWHR, "Software Hard"}, { |
| 480 | RSR_JSRS, "JTAG Soft"}, { |
| 481 | RSR_CSHR, "Check Stop"}, { |
| 482 | RSR_SWRS, "Software Watchdog"}, { |
| 483 | RSR_BMRS, "Bus Monitor"}, { |
| 484 | RSR_SRS, "External/Internal Soft"}, { |
| 485 | RSR_HRS, "External/Internal Hard"} |
| 486 | }; |
Robert P. J. Day | 0c91159 | 2016-05-23 06:49:21 -0400 | [diff] [blame] | 487 | static int n = ARRAY_SIZE(bits); |
Simon Glass | 4d6eaa3 | 2012-12-13 20:48:56 +0000 | [diff] [blame] | 488 | ulong rsr = gd->arch.reset_status; |
Dave Liu | ebd35f8 | 2007-06-25 10:41:56 +0800 | [diff] [blame] | 489 | int i; |
| 490 | char *sep; |
| 491 | |
| 492 | puts("Reset Status:"); |
| 493 | |
| 494 | sep = " "; |
| 495 | for (i = 0; i < n; i++) |
| 496 | if (rsr & bits[i].mask) { |
| 497 | printf("%s%s", sep, bits[i].desc); |
| 498 | sep = ", "; |
| 499 | } |
Nick Spence | 56fd3c2 | 2008-08-28 14:09:19 -0700 | [diff] [blame] | 500 | puts("\n"); |
| 501 | |
| 502 | #if defined(CONFIG_DISPLAY_AER_FULL) || defined(CONFIG_DISPLAY_AER_BRIEF) |
| 503 | print_83xx_arb_event(rsr & RSR_BMRS); |
| 504 | #endif |
| 505 | puts("\n"); |
| 506 | |
Dave Liu | ebd35f8 | 2007-06-25 10:41:56 +0800 | [diff] [blame] | 507 | return 0; |
| 508 | } |
Mario Six | 28fbefa | 2018-08-06 10:23:45 +0200 | [diff] [blame^] | 509 | #endif |