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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
wdenkfe8c2802002-11-03 00:38:21 +00002/*
3 * armboot - Startup Code for ARM920 CPU-core
4 *
Albert ARIBAUD60fbc8d2011-08-04 18:45:45 +02005 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
6 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
Detlev Zundelf1b3f2b2009-05-13 10:54:10 +02007 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
wdenkfe8c2802002-11-03 00:38:21 +00008 */
9
Wolfgang Denk0191e472010-10-26 14:34:52 +020010#include <asm-offsets.h>
wdenkfe8c2802002-11-03 00:38:21 +000011#include <config.h>
wdenkfe8c2802002-11-03 00:38:21 +000012
13/*
14 *************************************************************************
15 *
Peter Pearse782cf162007-09-05 16:04:41 +010016 * Startup Code (called from the ARM reset exception vector)
wdenkfe8c2802002-11-03 00:38:21 +000017 *
18 * do important init only if we don't start from memory!
19 * relocate armboot to ram
20 * setup stack
21 * jump to second stage
22 *
23 *************************************************************************
24 */
25
Albert ARIBAUD9852cc62014-04-15 16:13:51 +020026 .globl reset
wdenkfe8c2802002-11-03 00:38:21 +000027
Albert ARIBAUD9852cc62014-04-15 16:13:51 +020028reset:
wdenkfe8c2802002-11-03 00:38:21 +000029 /*
30 * set the cpu to SVC32 mode
31 */
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +090032 mrs r0, cpsr
33 bic r0, r0, #0x1f
34 orr r0, r0, #0xd3
35 msr cpsr, r0
Peter Pearse782cf162007-09-05 16:04:41 +010036
wdenkfe8c2802002-11-03 00:38:21 +000037 /*
38 * we do sys-critical inits only at reboot,
39 * not when booting from ram!
40 */
Tom Rinie1e85442021-08-27 21:18:30 -040041#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
wdenkfe8c2802002-11-03 00:38:21 +000042 bl cpu_init_crit
43#endif
44
Albert ARIBAUDfacdae52013-01-08 10:18:02 +000045 bl _main
Heiko Schocher271a2402010-09-17 13:10:43 +020046
47/*------------------------------------------------------------------------------*/
48
Albert ARIBAUDfacdae52013-01-08 10:18:02 +000049 .globl c_runtime_cpu_setup
50c_runtime_cpu_setup:
51
52 mov pc, lr
53
wdenkfe8c2802002-11-03 00:38:21 +000054/*
55 *************************************************************************
56 *
57 * CPU_init_critical registers
58 *
59 * setup important registers
60 * setup memory timing
61 *
62 *************************************************************************
63 */
64
65
Tom Rinie1e85442021-08-27 21:18:30 -040066#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
wdenkfe8c2802002-11-03 00:38:21 +000067cpu_init_crit:
68 /*
69 * flush v4 I/D caches
70 */
71 mov r0, #0
72 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
73 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
74
75 /*
76 * disable MMU stuff and caches
77 */
78 mrc p15, 0, r0, c1, c0, 0
79 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
80 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
Yuichiro Goto8d4b7e92016-02-25 10:23:34 +090081 orr r0, r0, #0x00000002 @ set bit 1 (A) Align
wdenkfe8c2802002-11-03 00:38:21 +000082 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
83 mcr p15, 0, r0, c1, c0, 0
84
Tom Rinie1e85442021-08-27 21:18:30 -040085#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
wdenkfe8c2802002-11-03 00:38:21 +000086 /*
87 * before relocating, we have to setup RAM timing
88 * because memory timing is board-dependend, you will
wdenk336b2bc2005-04-02 23:52:25 +000089 * find a lowlevel_init.S in your board directory.
wdenkfe8c2802002-11-03 00:38:21 +000090 */
91 mov ip, lr
Peter Pearsede5b02c2007-08-14 10:10:52 +010092
wdenk336b2bc2005-04-02 23:52:25 +000093 bl lowlevel_init
wdenkfe8c2802002-11-03 00:38:21 +000094 mov lr, ip
Simon Glass90844072016-05-05 07:28:06 -060095#endif
wdenkfe8c2802002-11-03 00:38:21 +000096 mov pc, lr
Tom Rinie1e85442021-08-27 21:18:30 -040097#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */