Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 2 | /* |
| 3 | * armboot - Startup Code for ARM920 CPU-core |
| 4 | * |
Albert ARIBAUD | 60fbc8d | 2011-08-04 18:45:45 +0200 | [diff] [blame] | 5 | * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> |
| 6 | * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> |
Detlev Zundel | f1b3f2b | 2009-05-13 10:54:10 +0200 | [diff] [blame] | 7 | * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 8 | */ |
| 9 | |
Wolfgang Denk | 0191e47 | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 10 | #include <asm-offsets.h> |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 11 | #include <config.h> |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 12 | |
| 13 | /* |
| 14 | ************************************************************************* |
| 15 | * |
Peter Pearse | 782cf16 | 2007-09-05 16:04:41 +0100 | [diff] [blame] | 16 | * Startup Code (called from the ARM reset exception vector) |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 17 | * |
| 18 | * do important init only if we don't start from memory! |
| 19 | * relocate armboot to ram |
| 20 | * setup stack |
| 21 | * jump to second stage |
| 22 | * |
| 23 | ************************************************************************* |
| 24 | */ |
| 25 | |
Albert ARIBAUD | 9852cc6 | 2014-04-15 16:13:51 +0200 | [diff] [blame] | 26 | .globl reset |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 27 | |
Albert ARIBAUD | 9852cc6 | 2014-04-15 16:13:51 +0200 | [diff] [blame] | 28 | reset: |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 29 | /* |
| 30 | * set the cpu to SVC32 mode |
| 31 | */ |
kevin.morfitt@fearnside-systems.co.uk | d1cacc7 | 2009-10-10 13:30:22 +0900 | [diff] [blame] | 32 | mrs r0, cpsr |
| 33 | bic r0, r0, #0x1f |
| 34 | orr r0, r0, #0xd3 |
| 35 | msr cpsr, r0 |
Peter Pearse | 782cf16 | 2007-09-05 16:04:41 +0100 | [diff] [blame] | 36 | |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 37 | /* |
| 38 | * we do sys-critical inits only at reboot, |
| 39 | * not when booting from ram! |
| 40 | */ |
Tom Rini | e1e8544 | 2021-08-27 21:18:30 -0400 | [diff] [blame] | 41 | #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 42 | bl cpu_init_crit |
| 43 | #endif |
| 44 | |
Albert ARIBAUD | facdae5 | 2013-01-08 10:18:02 +0000 | [diff] [blame] | 45 | bl _main |
Heiko Schocher | 271a240 | 2010-09-17 13:10:43 +0200 | [diff] [blame] | 46 | |
| 47 | /*------------------------------------------------------------------------------*/ |
| 48 | |
Albert ARIBAUD | facdae5 | 2013-01-08 10:18:02 +0000 | [diff] [blame] | 49 | .globl c_runtime_cpu_setup |
| 50 | c_runtime_cpu_setup: |
| 51 | |
| 52 | mov pc, lr |
| 53 | |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 54 | /* |
| 55 | ************************************************************************* |
| 56 | * |
| 57 | * CPU_init_critical registers |
| 58 | * |
| 59 | * setup important registers |
| 60 | * setup memory timing |
| 61 | * |
| 62 | ************************************************************************* |
| 63 | */ |
| 64 | |
| 65 | |
Tom Rini | e1e8544 | 2021-08-27 21:18:30 -0400 | [diff] [blame] | 66 | #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 67 | cpu_init_crit: |
| 68 | /* |
| 69 | * flush v4 I/D caches |
| 70 | */ |
| 71 | mov r0, #0 |
| 72 | mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ |
| 73 | mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ |
| 74 | |
| 75 | /* |
| 76 | * disable MMU stuff and caches |
| 77 | */ |
| 78 | mrc p15, 0, r0, c1, c0, 0 |
| 79 | bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) |
| 80 | bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) |
Yuichiro Goto | 8d4b7e9 | 2016-02-25 10:23:34 +0900 | [diff] [blame] | 81 | orr r0, r0, #0x00000002 @ set bit 1 (A) Align |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 82 | orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache |
| 83 | mcr p15, 0, r0, c1, c0, 0 |
| 84 | |
Tom Rini | e1e8544 | 2021-08-27 21:18:30 -0400 | [diff] [blame] | 85 | #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY) |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 86 | /* |
| 87 | * before relocating, we have to setup RAM timing |
| 88 | * because memory timing is board-dependend, you will |
wdenk | 336b2bc | 2005-04-02 23:52:25 +0000 | [diff] [blame] | 89 | * find a lowlevel_init.S in your board directory. |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 90 | */ |
| 91 | mov ip, lr |
Peter Pearse | de5b02c | 2007-08-14 10:10:52 +0100 | [diff] [blame] | 92 | |
wdenk | 336b2bc | 2005-04-02 23:52:25 +0000 | [diff] [blame] | 93 | bl lowlevel_init |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 94 | mov lr, ip |
Simon Glass | 9084407 | 2016-05-05 07:28:06 -0600 | [diff] [blame] | 95 | #endif |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 96 | mov pc, lr |
Tom Rini | e1e8544 | 2021-08-27 21:18:30 -0400 | [diff] [blame] | 97 | #endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */ |