wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 1 | /* |
| 2 | * armboot - Startup Code for ARM920 CPU-core |
| 3 | * |
Albert ARIBAUD | 60fbc8d | 2011-08-04 18:45:45 +0200 | [diff] [blame] | 4 | * Copyright (c) 2001 Marius Gröger <mag@sysgo.de> |
| 5 | * Copyright (c) 2002 Alex Züpke <azu@sysgo.de> |
Detlev Zundel | f1b3f2b | 2009-05-13 10:54:10 +0200 | [diff] [blame] | 6 | * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de> |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 7 | * |
| 8 | * See file CREDITS for list of people who contributed to this |
| 9 | * project. |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or |
| 12 | * modify it under the terms of the GNU General Public License as |
| 13 | * published by the Free Software Foundation; either version 2 of |
| 14 | * the License, or (at your option) any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | * GNU General Public License for more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License |
| 22 | * along with this program; if not, write to the Free Software |
| 23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 24 | * MA 02111-1307 USA |
| 25 | */ |
| 26 | |
Wolfgang Denk | 0191e47 | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 27 | #include <asm-offsets.h> |
Wolfgang Denk | 140f044 | 2009-07-27 10:06:39 +0200 | [diff] [blame] | 28 | #include <common.h> |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 29 | #include <config.h> |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 30 | |
| 31 | /* |
| 32 | ************************************************************************* |
| 33 | * |
| 34 | * Jump vector table as in table 3.1 in [1] |
| 35 | * |
| 36 | ************************************************************************* |
| 37 | */ |
| 38 | |
| 39 | |
| 40 | .globl _start |
kevin.morfitt@fearnside-systems.co.uk | d1cacc7 | 2009-10-10 13:30:22 +0900 | [diff] [blame] | 41 | _start: b start_code |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 42 | ldr pc, _undefined_instruction |
| 43 | ldr pc, _software_interrupt |
| 44 | ldr pc, _prefetch_abort |
| 45 | ldr pc, _data_abort |
| 46 | ldr pc, _not_used |
| 47 | ldr pc, _irq |
| 48 | ldr pc, _fiq |
| 49 | |
| 50 | _undefined_instruction: .word undefined_instruction |
| 51 | _software_interrupt: .word software_interrupt |
| 52 | _prefetch_abort: .word prefetch_abort |
| 53 | _data_abort: .word data_abort |
| 54 | _not_used: .word not_used |
| 55 | _irq: .word irq |
| 56 | _fiq: .word fiq |
| 57 | |
| 58 | .balignl 16,0xdeadbeef |
| 59 | |
| 60 | |
| 61 | /* |
| 62 | ************************************************************************* |
| 63 | * |
Peter Pearse | 782cf16 | 2007-09-05 16:04:41 +0100 | [diff] [blame] | 64 | * Startup Code (called from the ARM reset exception vector) |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 65 | * |
| 66 | * do important init only if we don't start from memory! |
| 67 | * relocate armboot to ram |
| 68 | * setup stack |
| 69 | * jump to second stage |
| 70 | * |
| 71 | ************************************************************************* |
| 72 | */ |
| 73 | |
Heiko Schocher | 271a240 | 2010-09-17 13:10:43 +0200 | [diff] [blame] | 74 | .globl _TEXT_BASE |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 75 | _TEXT_BASE: |
Wolfgang Denk | 0708bc6 | 2010-10-07 21:51:12 +0200 | [diff] [blame] | 76 | .word CONFIG_SYS_TEXT_BASE |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 77 | |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 78 | /* |
wdenk | 927034e | 2004-02-08 19:38:38 +0000 | [diff] [blame] | 79 | * These are defined in the board-specific linker script. |
Albert Aribaud | 126897e | 2010-11-25 22:45:02 +0100 | [diff] [blame] | 80 | * Subtracting _start from them lets the linker put their |
| 81 | * relative position in the executable instead of leaving |
| 82 | * them null. |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 83 | */ |
Albert Aribaud | 126897e | 2010-11-25 22:45:02 +0100 | [diff] [blame] | 84 | .globl _bss_start_ofs |
| 85 | _bss_start_ofs: |
| 86 | .word __bss_start - _start |
wdenk | 927034e | 2004-02-08 19:38:38 +0000 | [diff] [blame] | 87 | |
Albert Aribaud | 126897e | 2010-11-25 22:45:02 +0100 | [diff] [blame] | 88 | .globl _bss_end_ofs |
| 89 | _bss_end_ofs: |
Po-Yu Chuang | cedbf4b | 2011-03-01 22:59:59 +0000 | [diff] [blame] | 90 | .word __bss_end__ - _start |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 91 | |
Po-Yu Chuang | 1864b00 | 2011-03-01 23:02:04 +0000 | [diff] [blame] | 92 | .globl _end_ofs |
| 93 | _end_ofs: |
| 94 | .word _end - _start |
| 95 | |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 96 | #ifdef CONFIG_USE_IRQ |
| 97 | /* IRQ stack memory (calculated at run-time) */ |
| 98 | .globl IRQ_STACK_START |
| 99 | IRQ_STACK_START: |
| 100 | .word 0x0badc0de |
| 101 | |
| 102 | /* IRQ stack memory (calculated at run-time) */ |
| 103 | .globl FIQ_STACK_START |
| 104 | FIQ_STACK_START: |
| 105 | .word 0x0badc0de |
| 106 | #endif |
| 107 | |
Heiko Schocher | 271a240 | 2010-09-17 13:10:43 +0200 | [diff] [blame] | 108 | /* IRQ stack memory (calculated at run-time) + 8 bytes */ |
| 109 | .globl IRQ_STACK_START_IN |
| 110 | IRQ_STACK_START_IN: |
| 111 | .word 0x0badc0de |
| 112 | |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 113 | /* |
Peter Pearse | 782cf16 | 2007-09-05 16:04:41 +0100 | [diff] [blame] | 114 | * the actual start code |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 115 | */ |
| 116 | |
Peter Pearse | 782cf16 | 2007-09-05 16:04:41 +0100 | [diff] [blame] | 117 | start_code: |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 118 | /* |
| 119 | * set the cpu to SVC32 mode |
| 120 | */ |
kevin.morfitt@fearnside-systems.co.uk | d1cacc7 | 2009-10-10 13:30:22 +0900 | [diff] [blame] | 121 | mrs r0, cpsr |
| 122 | bic r0, r0, #0x1f |
| 123 | orr r0, r0, #0xd3 |
| 124 | msr cpsr, r0 |
Peter Pearse | 782cf16 | 2007-09-05 16:04:41 +0100 | [diff] [blame] | 125 | |
Jean-Christophe PLAGNIOL-VILLARD | 06f3496 | 2008-11-30 19:36:50 +0100 | [diff] [blame] | 126 | #if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) |
Peter Pearse | de5b02c | 2007-08-14 10:10:52 +0100 | [diff] [blame] | 127 | /* |
Peter Pearse | 782cf16 | 2007-09-05 16:04:41 +0100 | [diff] [blame] | 128 | * relocate exception table |
Peter Pearse | de5b02c | 2007-08-14 10:10:52 +0100 | [diff] [blame] | 129 | */ |
| 130 | ldr r0, =_start |
| 131 | ldr r1, =0x0 |
| 132 | mov r2, #16 |
| 133 | copyex: |
| 134 | subs r2, r2, #1 |
| 135 | ldr r3, [r0], #4 |
| 136 | str r3, [r1], #4 |
| 137 | bne copyex |
| 138 | #endif |
| 139 | |
kevin.morfitt@fearnside-systems.co.uk | e0d8131 | 2009-11-17 18:30:34 +0900 | [diff] [blame] | 140 | #ifdef CONFIG_S3C24X0 |
Peter Pearse | 782cf16 | 2007-09-05 16:04:41 +0100 | [diff] [blame] | 141 | /* turn off the watchdog */ |
| 142 | |
| 143 | # if defined(CONFIG_S3C2400) |
kevin.morfitt@fearnside-systems.co.uk | d1cacc7 | 2009-10-10 13:30:22 +0900 | [diff] [blame] | 144 | # define pWTCON 0x15300000 |
Mike Williams | bf895ad | 2011-07-22 04:01:30 +0000 | [diff] [blame] | 145 | # define INTMSK 0x14400008 /* Interrupt-Controller base addresses */ |
Peter Pearse | 782cf16 | 2007-09-05 16:04:41 +0100 | [diff] [blame] | 146 | # define CLKDIVN 0x14800014 /* clock divisor register */ |
| 147 | #else |
kevin.morfitt@fearnside-systems.co.uk | d1cacc7 | 2009-10-10 13:30:22 +0900 | [diff] [blame] | 148 | # define pWTCON 0x53000000 |
Mike Williams | bf895ad | 2011-07-22 04:01:30 +0000 | [diff] [blame] | 149 | # define INTMSK 0x4A000008 /* Interrupt-Controller base addresses */ |
Peter Pearse | 782cf16 | 2007-09-05 16:04:41 +0100 | [diff] [blame] | 150 | # define INTSUBMSK 0x4A00001C |
| 151 | # define CLKDIVN 0x4C000014 /* clock divisor register */ |
| 152 | # endif |
| 153 | |
kevin.morfitt@fearnside-systems.co.uk | d1cacc7 | 2009-10-10 13:30:22 +0900 | [diff] [blame] | 154 | ldr r0, =pWTCON |
| 155 | mov r1, #0x0 |
| 156 | str r1, [r0] |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 157 | |
| 158 | /* |
| 159 | * mask all IRQs by setting all bits in the INTMR - default |
| 160 | */ |
| 161 | mov r1, #0xffffffff |
| 162 | ldr r0, =INTMSK |
| 163 | str r1, [r0] |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 164 | # if defined(CONFIG_S3C2410) |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 165 | ldr r1, =0x3ff |
| 166 | ldr r0, =INTSUBMSK |
| 167 | str r1, [r0] |
wdenk | 7ac1610 | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 168 | # endif |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 169 | |
| 170 | /* FCLK:HCLK:PCLK = 1:2:4 */ |
| 171 | /* default FCLK is 120 MHz ! */ |
| 172 | ldr r0, =CLKDIVN |
| 173 | mov r1, #3 |
| 174 | str r1, [r0] |
kevin.morfitt@fearnside-systems.co.uk | e0d8131 | 2009-11-17 18:30:34 +0900 | [diff] [blame] | 175 | #endif /* CONFIG_S3C24X0 */ |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 176 | |
| 177 | /* |
| 178 | * we do sys-critical inits only at reboot, |
| 179 | * not when booting from ram! |
| 180 | */ |
wdenk | 3d3d99f | 2005-04-04 12:44:11 +0000 | [diff] [blame] | 181 | #ifndef CONFIG_SKIP_LOWLEVEL_INIT |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 182 | bl cpu_init_crit |
| 183 | #endif |
| 184 | |
Albert ARIBAUD | facdae5 | 2013-01-08 10:18:02 +0000 | [diff] [blame^] | 185 | bl _main |
Heiko Schocher | 271a240 | 2010-09-17 13:10:43 +0200 | [diff] [blame] | 186 | |
| 187 | /*------------------------------------------------------------------------------*/ |
| 188 | |
| 189 | /* |
| 190 | * void relocate_code (addr_sp, gd, addr_moni) |
| 191 | * |
| 192 | * This "function" does not return, instead it continues in RAM |
| 193 | * after relocating the monitor code. |
| 194 | * |
| 195 | */ |
| 196 | .globl relocate_code |
| 197 | relocate_code: |
| 198 | mov r4, r0 /* save addr_sp */ |
| 199 | mov r5, r1 /* save addr of gd */ |
| 200 | mov r6, r2 /* save addr of destination */ |
Heiko Schocher | 271a240 | 2010-09-17 13:10:43 +0200 | [diff] [blame] | 201 | |
Heiko Schocher | 271a240 | 2010-09-17 13:10:43 +0200 | [diff] [blame] | 202 | adr r0, _start |
Andreas Bießmann | 007b38f | 2010-12-01 00:58:34 +0100 | [diff] [blame] | 203 | cmp r0, r6 |
Zhong Hongbo | 8c2ef80 | 2012-09-01 20:49:52 +0000 | [diff] [blame] | 204 | moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ |
Albert ARIBAUD | facdae5 | 2013-01-08 10:18:02 +0000 | [diff] [blame^] | 205 | beq relocate_done /* skip relocation */ |
Andreas Bießmann | 8cfbda9 | 2010-12-01 00:58:33 +0100 | [diff] [blame] | 206 | mov r1, r6 /* r1 <- scratch for copy_loop */ |
Albert Aribaud | 126897e | 2010-11-25 22:45:02 +0100 | [diff] [blame] | 207 | ldr r3, _bss_start_ofs |
| 208 | add r2, r0, r3 /* r2 <- source end address */ |
Heiko Schocher | 271a240 | 2010-09-17 13:10:43 +0200 | [diff] [blame] | 209 | |
Heiko Schocher | 271a240 | 2010-09-17 13:10:43 +0200 | [diff] [blame] | 210 | copy_loop: |
| 211 | ldmia r0!, {r9-r10} /* copy from source address [r0] */ |
Andreas Bießmann | 8cfbda9 | 2010-12-01 00:58:33 +0100 | [diff] [blame] | 212 | stmia r1!, {r9-r10} /* copy to target address [r1] */ |
Albert Aribaud | 0668d16 | 2010-10-05 16:06:39 +0200 | [diff] [blame] | 213 | cmp r0, r2 /* until source end address [r2] */ |
| 214 | blo copy_loop |
Heiko Schocher | 271a240 | 2010-09-17 13:10:43 +0200 | [diff] [blame] | 215 | |
Aneesh V | 552a319 | 2011-07-13 05:11:07 +0000 | [diff] [blame] | 216 | #ifndef CONFIG_SPL_BUILD |
Albert Aribaud | 126897e | 2010-11-25 22:45:02 +0100 | [diff] [blame] | 217 | /* |
| 218 | * fix .rel.dyn relocations |
| 219 | */ |
| 220 | ldr r0, _TEXT_BASE /* r0 <- Text base */ |
Andreas Bießmann | 8cfbda9 | 2010-12-01 00:58:33 +0100 | [diff] [blame] | 221 | sub r9, r6, r0 /* r9 <- relocation offset */ |
Albert Aribaud | 126897e | 2010-11-25 22:45:02 +0100 | [diff] [blame] | 222 | ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ |
| 223 | add r10, r10, r0 /* r10 <- sym table in FLASH */ |
| 224 | ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ |
| 225 | add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ |
| 226 | ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ |
| 227 | add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ |
Heiko Schocher | 271a240 | 2010-09-17 13:10:43 +0200 | [diff] [blame] | 228 | fixloop: |
Albert Aribaud | 126897e | 2010-11-25 22:45:02 +0100 | [diff] [blame] | 229 | ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ |
| 230 | add r0, r0, r9 /* r0 <- location to fix up in RAM */ |
| 231 | ldr r1, [r2, #4] |
Andreas Bießmann | 318cea1 | 2010-12-01 00:58:35 +0100 | [diff] [blame] | 232 | and r7, r1, #0xff |
| 233 | cmp r7, #23 /* relative fixup? */ |
Albert Aribaud | 126897e | 2010-11-25 22:45:02 +0100 | [diff] [blame] | 234 | beq fixrel |
Andreas Bießmann | 318cea1 | 2010-12-01 00:58:35 +0100 | [diff] [blame] | 235 | cmp r7, #2 /* absolute fixup? */ |
Albert Aribaud | 126897e | 2010-11-25 22:45:02 +0100 | [diff] [blame] | 236 | beq fixabs |
| 237 | /* ignore unknown type of fixup */ |
| 238 | b fixnext |
| 239 | fixabs: |
| 240 | /* absolute fix: set location to (offset) symbol value */ |
| 241 | mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ |
| 242 | add r1, r10, r1 /* r1 <- address of symbol in table */ |
| 243 | ldr r1, [r1, #4] /* r1 <- symbol value */ |
Wolfgang Denk | 899cdd1 | 2010-12-09 11:26:24 +0100 | [diff] [blame] | 244 | add r1, r1, r9 /* r1 <- relocated sym addr */ |
Albert Aribaud | 126897e | 2010-11-25 22:45:02 +0100 | [diff] [blame] | 245 | b fixnext |
| 246 | fixrel: |
| 247 | /* relative fix: increase location by offset */ |
| 248 | ldr r1, [r0] |
| 249 | add r1, r1, r9 |
| 250 | fixnext: |
| 251 | str r1, [r0] |
| 252 | add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ |
Heiko Schocher | 271a240 | 2010-09-17 13:10:43 +0200 | [diff] [blame] | 253 | cmp r2, r3 |
Wolfgang Denk | 98dd07c | 2010-10-23 23:22:38 +0200 | [diff] [blame] | 254 | blo fixloop |
Heiko Schocher | 271a240 | 2010-09-17 13:10:43 +0200 | [diff] [blame] | 255 | #endif |
Heiko Schocher | 271a240 | 2010-09-17 13:10:43 +0200 | [diff] [blame] | 256 | |
Albert ARIBAUD | facdae5 | 2013-01-08 10:18:02 +0000 | [diff] [blame^] | 257 | relocate_done: |
Heiko Schocher | 271a240 | 2010-09-17 13:10:43 +0200 | [diff] [blame] | 258 | |
Heiko Schocher | 271a240 | 2010-09-17 13:10:43 +0200 | [diff] [blame] | 259 | mov pc, lr |
| 260 | |
Albert Aribaud | 126897e | 2010-11-25 22:45:02 +0100 | [diff] [blame] | 261 | _rel_dyn_start_ofs: |
| 262 | .word __rel_dyn_start - _start |
| 263 | _rel_dyn_end_ofs: |
| 264 | .word __rel_dyn_end - _start |
| 265 | _dynsym_start_ofs: |
| 266 | .word __dynsym_start - _start |
| 267 | |
Albert ARIBAUD | facdae5 | 2013-01-08 10:18:02 +0000 | [diff] [blame^] | 268 | .globl c_runtime_cpu_setup |
| 269 | c_runtime_cpu_setup: |
| 270 | |
| 271 | mov pc, lr |
| 272 | |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 273 | /* |
| 274 | ************************************************************************* |
| 275 | * |
| 276 | * CPU_init_critical registers |
| 277 | * |
| 278 | * setup important registers |
| 279 | * setup memory timing |
| 280 | * |
| 281 | ************************************************************************* |
| 282 | */ |
| 283 | |
| 284 | |
Wolfgang Denk | f2e11a7 | 2006-04-03 15:46:10 +0200 | [diff] [blame] | 285 | #ifndef CONFIG_SKIP_LOWLEVEL_INIT |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 286 | cpu_init_crit: |
| 287 | /* |
| 288 | * flush v4 I/D caches |
| 289 | */ |
| 290 | mov r0, #0 |
| 291 | mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ |
| 292 | mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ |
| 293 | |
| 294 | /* |
| 295 | * disable MMU stuff and caches |
| 296 | */ |
| 297 | mrc p15, 0, r0, c1, c0, 0 |
| 298 | bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) |
| 299 | bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) |
| 300 | orr r0, r0, #0x00000002 @ set bit 2 (A) Align |
| 301 | orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache |
| 302 | mcr p15, 0, r0, c1, c0, 0 |
| 303 | |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 304 | /* |
| 305 | * before relocating, we have to setup RAM timing |
| 306 | * because memory timing is board-dependend, you will |
wdenk | 336b2bc | 2005-04-02 23:52:25 +0000 | [diff] [blame] | 307 | * find a lowlevel_init.S in your board directory. |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 308 | */ |
| 309 | mov ip, lr |
Peter Pearse | de5b02c | 2007-08-14 10:10:52 +0100 | [diff] [blame] | 310 | |
wdenk | 336b2bc | 2005-04-02 23:52:25 +0000 | [diff] [blame] | 311 | bl lowlevel_init |
Ulf Samuelsson | 07f9b4e | 2009-03-27 23:26:43 +0100 | [diff] [blame] | 312 | |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 313 | mov lr, ip |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 314 | mov pc, lr |
Wolfgang Denk | f2e11a7 | 2006-04-03 15:46:10 +0200 | [diff] [blame] | 315 | #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 316 | |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 317 | /* |
| 318 | ************************************************************************* |
| 319 | * |
| 320 | * Interrupt handling |
| 321 | * |
| 322 | ************************************************************************* |
| 323 | */ |
| 324 | |
| 325 | @ |
| 326 | @ IRQ stack frame. |
| 327 | @ |
| 328 | #define S_FRAME_SIZE 72 |
| 329 | |
| 330 | #define S_OLD_R0 68 |
| 331 | #define S_PSR 64 |
| 332 | #define S_PC 60 |
| 333 | #define S_LR 56 |
| 334 | #define S_SP 52 |
| 335 | |
| 336 | #define S_IP 48 |
| 337 | #define S_FP 44 |
| 338 | #define S_R10 40 |
| 339 | #define S_R9 36 |
| 340 | #define S_R8 32 |
| 341 | #define S_R7 28 |
| 342 | #define S_R6 24 |
| 343 | #define S_R5 20 |
| 344 | #define S_R4 16 |
| 345 | #define S_R3 12 |
| 346 | #define S_R2 8 |
| 347 | #define S_R1 4 |
| 348 | #define S_R0 0 |
| 349 | |
kevin.morfitt@fearnside-systems.co.uk | d1cacc7 | 2009-10-10 13:30:22 +0900 | [diff] [blame] | 350 | #define MODE_SVC 0x13 |
| 351 | #define I_BIT 0x80 |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 352 | |
| 353 | /* |
| 354 | * use bad_save_user_regs for abort/prefetch/undef/swi ... |
| 355 | * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling |
| 356 | */ |
| 357 | |
| 358 | .macro bad_save_user_regs |
| 359 | sub sp, sp, #S_FRAME_SIZE |
| 360 | stmia sp, {r0 - r12} @ Calling r0-r12 |
Heiko Schocher | 271a240 | 2010-09-17 13:10:43 +0200 | [diff] [blame] | 361 | ldr r2, IRQ_STACK_START_IN |
wdenk | f4688a2 | 2003-05-28 08:06:31 +0000 | [diff] [blame] | 362 | ldmia r2, {r2 - r3} @ get pc, cpsr |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 363 | add r0, sp, #S_FRAME_SIZE @ restore sp_SVC |
| 364 | |
| 365 | add r5, sp, #S_SP |
| 366 | mov r1, lr |
wdenk | f4688a2 | 2003-05-28 08:06:31 +0000 | [diff] [blame] | 367 | stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 368 | mov r0, sp |
| 369 | .endm |
| 370 | |
| 371 | .macro irq_save_user_regs |
| 372 | sub sp, sp, #S_FRAME_SIZE |
| 373 | stmia sp, {r0 - r12} @ Calling r0-r12 |
kevin.morfitt@fearnside-systems.co.uk | d1cacc7 | 2009-10-10 13:30:22 +0900 | [diff] [blame] | 374 | add r7, sp, #S_PC |
| 375 | stmdb r7, {sp, lr}^ @ Calling SP, LR |
| 376 | str lr, [r7, #0] @ Save calling PC |
| 377 | mrs r6, spsr |
| 378 | str r6, [r7, #4] @ Save CPSR |
| 379 | str r0, [r7, #8] @ Save OLD_R0 |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 380 | mov r0, sp |
| 381 | .endm |
| 382 | |
| 383 | .macro irq_restore_user_regs |
| 384 | ldmia sp, {r0 - lr}^ @ Calling r0 - lr |
| 385 | mov r0, r0 |
| 386 | ldr lr, [sp, #S_PC] @ Get PC |
| 387 | add sp, sp, #S_FRAME_SIZE |
kevin.morfitt@fearnside-systems.co.uk | d1cacc7 | 2009-10-10 13:30:22 +0900 | [diff] [blame] | 388 | /* return & move spsr_svc into cpsr */ |
| 389 | subs pc, lr, #4 |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 390 | .endm |
| 391 | |
| 392 | .macro get_bad_stack |
Heiko Schocher | 271a240 | 2010-09-17 13:10:43 +0200 | [diff] [blame] | 393 | ldr r13, IRQ_STACK_START_IN @ setup our mode stack |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 394 | |
| 395 | str lr, [r13] @ save caller lr / spsr |
| 396 | mrs lr, spsr |
kevin.morfitt@fearnside-systems.co.uk | d1cacc7 | 2009-10-10 13:30:22 +0900 | [diff] [blame] | 397 | str lr, [r13, #4] |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 398 | |
| 399 | mov r13, #MODE_SVC @ prepare SVC-Mode |
| 400 | @ msr spsr_c, r13 |
| 401 | msr spsr, r13 |
| 402 | mov lr, pc |
| 403 | movs pc, lr |
| 404 | .endm |
| 405 | |
| 406 | .macro get_irq_stack @ setup IRQ stack |
| 407 | ldr sp, IRQ_STACK_START |
| 408 | .endm |
| 409 | |
| 410 | .macro get_fiq_stack @ setup FIQ stack |
| 411 | ldr sp, FIQ_STACK_START |
| 412 | .endm |
| 413 | |
| 414 | /* |
| 415 | * exception handlers |
| 416 | */ |
| 417 | .align 5 |
| 418 | undefined_instruction: |
| 419 | get_bad_stack |
| 420 | bad_save_user_regs |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 421 | bl do_undefined_instruction |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 422 | |
| 423 | .align 5 |
| 424 | software_interrupt: |
| 425 | get_bad_stack |
| 426 | bad_save_user_regs |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 427 | bl do_software_interrupt |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 428 | |
| 429 | .align 5 |
| 430 | prefetch_abort: |
| 431 | get_bad_stack |
| 432 | bad_save_user_regs |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 433 | bl do_prefetch_abort |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 434 | |
| 435 | .align 5 |
| 436 | data_abort: |
| 437 | get_bad_stack |
| 438 | bad_save_user_regs |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 439 | bl do_data_abort |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 440 | |
| 441 | .align 5 |
| 442 | not_used: |
| 443 | get_bad_stack |
| 444 | bad_save_user_regs |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 445 | bl do_not_used |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 446 | |
| 447 | #ifdef CONFIG_USE_IRQ |
| 448 | |
| 449 | .align 5 |
| 450 | irq: |
| 451 | get_irq_stack |
| 452 | irq_save_user_regs |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 453 | bl do_irq |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 454 | irq_restore_user_regs |
| 455 | |
| 456 | .align 5 |
| 457 | fiq: |
| 458 | get_fiq_stack |
| 459 | /* someone ought to write a more effiction fiq_save_user_regs */ |
| 460 | irq_save_user_regs |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 461 | bl do_fiq |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 462 | irq_restore_user_regs |
| 463 | |
| 464 | #else |
| 465 | |
| 466 | .align 5 |
| 467 | irq: |
| 468 | get_bad_stack |
| 469 | bad_save_user_regs |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 470 | bl do_irq |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 471 | |
| 472 | .align 5 |
| 473 | fiq: |
| 474 | get_bad_stack |
| 475 | bad_save_user_regs |
Wolfgang Denk | a1be476 | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 476 | bl do_fiq |
wdenk | fe8c280 | 2002-11-03 00:38:21 +0000 | [diff] [blame] | 477 | |
| 478 | #endif |