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wdenkfe8c2802002-11-03 00:38:21 +00001/*
2 * armboot - Startup Code for ARM920 CPU-core
3 *
Albert ARIBAUD60fbc8d2011-08-04 18:45:45 +02004 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
5 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
Detlev Zundelf1b3f2b2009-05-13 10:54:10 +02006 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
wdenkfe8c2802002-11-03 00:38:21 +00007 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
Wolfgang Denk0191e472010-10-26 14:34:52 +020027#include <asm-offsets.h>
Wolfgang Denk140f0442009-07-27 10:06:39 +020028#include <common.h>
wdenkfe8c2802002-11-03 00:38:21 +000029#include <config.h>
wdenkfe8c2802002-11-03 00:38:21 +000030
31/*
32 *************************************************************************
33 *
34 * Jump vector table as in table 3.1 in [1]
35 *
36 *************************************************************************
37 */
38
39
40.globl _start
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +090041_start: b start_code
wdenkfe8c2802002-11-03 00:38:21 +000042 ldr pc, _undefined_instruction
43 ldr pc, _software_interrupt
44 ldr pc, _prefetch_abort
45 ldr pc, _data_abort
46 ldr pc, _not_used
47 ldr pc, _irq
48 ldr pc, _fiq
49
50_undefined_instruction: .word undefined_instruction
51_software_interrupt: .word software_interrupt
52_prefetch_abort: .word prefetch_abort
53_data_abort: .word data_abort
54_not_used: .word not_used
55_irq: .word irq
56_fiq: .word fiq
57
58 .balignl 16,0xdeadbeef
59
60
61/*
62 *************************************************************************
63 *
Peter Pearse782cf162007-09-05 16:04:41 +010064 * Startup Code (called from the ARM reset exception vector)
wdenkfe8c2802002-11-03 00:38:21 +000065 *
66 * do important init only if we don't start from memory!
67 * relocate armboot to ram
68 * setup stack
69 * jump to second stage
70 *
71 *************************************************************************
72 */
73
Heiko Schocher271a2402010-09-17 13:10:43 +020074.globl _TEXT_BASE
wdenkfe8c2802002-11-03 00:38:21 +000075_TEXT_BASE:
Wolfgang Denk0708bc62010-10-07 21:51:12 +020076 .word CONFIG_SYS_TEXT_BASE
wdenkfe8c2802002-11-03 00:38:21 +000077
wdenkfe8c2802002-11-03 00:38:21 +000078/*
wdenk927034e2004-02-08 19:38:38 +000079 * These are defined in the board-specific linker script.
Albert Aribaud126897e2010-11-25 22:45:02 +010080 * Subtracting _start from them lets the linker put their
81 * relative position in the executable instead of leaving
82 * them null.
wdenkfe8c2802002-11-03 00:38:21 +000083 */
Albert Aribaud126897e2010-11-25 22:45:02 +010084.globl _bss_start_ofs
85_bss_start_ofs:
86 .word __bss_start - _start
wdenk927034e2004-02-08 19:38:38 +000087
Albert Aribaud126897e2010-11-25 22:45:02 +010088.globl _bss_end_ofs
89_bss_end_ofs:
Po-Yu Chuangcedbf4b2011-03-01 22:59:59 +000090 .word __bss_end__ - _start
wdenkfe8c2802002-11-03 00:38:21 +000091
Po-Yu Chuang1864b002011-03-01 23:02:04 +000092.globl _end_ofs
93_end_ofs:
94 .word _end - _start
95
wdenkfe8c2802002-11-03 00:38:21 +000096#ifdef CONFIG_USE_IRQ
97/* IRQ stack memory (calculated at run-time) */
98.globl IRQ_STACK_START
99IRQ_STACK_START:
100 .word 0x0badc0de
101
102/* IRQ stack memory (calculated at run-time) */
103.globl FIQ_STACK_START
104FIQ_STACK_START:
105 .word 0x0badc0de
106#endif
107
Heiko Schocher271a2402010-09-17 13:10:43 +0200108/* IRQ stack memory (calculated at run-time) + 8 bytes */
109.globl IRQ_STACK_START_IN
110IRQ_STACK_START_IN:
111 .word 0x0badc0de
112
wdenkfe8c2802002-11-03 00:38:21 +0000113/*
Peter Pearse782cf162007-09-05 16:04:41 +0100114 * the actual start code
wdenkfe8c2802002-11-03 00:38:21 +0000115 */
116
Peter Pearse782cf162007-09-05 16:04:41 +0100117start_code:
wdenkfe8c2802002-11-03 00:38:21 +0000118 /*
119 * set the cpu to SVC32 mode
120 */
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900121 mrs r0, cpsr
122 bic r0, r0, #0x1f
123 orr r0, r0, #0xd3
124 msr cpsr, r0
Peter Pearse782cf162007-09-05 16:04:41 +0100125
Jean-Christophe PLAGNIOL-VILLARD06f34962008-11-30 19:36:50 +0100126#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
Peter Pearsede5b02c2007-08-14 10:10:52 +0100127 /*
Peter Pearse782cf162007-09-05 16:04:41 +0100128 * relocate exception table
Peter Pearsede5b02c2007-08-14 10:10:52 +0100129 */
130 ldr r0, =_start
131 ldr r1, =0x0
132 mov r2, #16
133copyex:
134 subs r2, r2, #1
135 ldr r3, [r0], #4
136 str r3, [r1], #4
137 bne copyex
138#endif
139
kevin.morfitt@fearnside-systems.co.uke0d81312009-11-17 18:30:34 +0900140#ifdef CONFIG_S3C24X0
Peter Pearse782cf162007-09-05 16:04:41 +0100141 /* turn off the watchdog */
142
143# if defined(CONFIG_S3C2400)
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900144# define pWTCON 0x15300000
Mike Williamsbf895ad2011-07-22 04:01:30 +0000145# define INTMSK 0x14400008 /* Interrupt-Controller base addresses */
Peter Pearse782cf162007-09-05 16:04:41 +0100146# define CLKDIVN 0x14800014 /* clock divisor register */
147#else
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900148# define pWTCON 0x53000000
Mike Williamsbf895ad2011-07-22 04:01:30 +0000149# define INTMSK 0x4A000008 /* Interrupt-Controller base addresses */
Peter Pearse782cf162007-09-05 16:04:41 +0100150# define INTSUBMSK 0x4A00001C
151# define CLKDIVN 0x4C000014 /* clock divisor register */
152# endif
153
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900154 ldr r0, =pWTCON
155 mov r1, #0x0
156 str r1, [r0]
wdenkfe8c2802002-11-03 00:38:21 +0000157
158 /*
159 * mask all IRQs by setting all bits in the INTMR - default
160 */
161 mov r1, #0xffffffff
162 ldr r0, =INTMSK
163 str r1, [r0]
wdenk7ac16102004-08-01 22:48:16 +0000164# if defined(CONFIG_S3C2410)
wdenkfe8c2802002-11-03 00:38:21 +0000165 ldr r1, =0x3ff
166 ldr r0, =INTSUBMSK
167 str r1, [r0]
wdenk7ac16102004-08-01 22:48:16 +0000168# endif
wdenkfe8c2802002-11-03 00:38:21 +0000169
170 /* FCLK:HCLK:PCLK = 1:2:4 */
171 /* default FCLK is 120 MHz ! */
172 ldr r0, =CLKDIVN
173 mov r1, #3
174 str r1, [r0]
kevin.morfitt@fearnside-systems.co.uke0d81312009-11-17 18:30:34 +0900175#endif /* CONFIG_S3C24X0 */
wdenkfe8c2802002-11-03 00:38:21 +0000176
177 /*
178 * we do sys-critical inits only at reboot,
179 * not when booting from ram!
180 */
wdenk3d3d99f2005-04-04 12:44:11 +0000181#ifndef CONFIG_SKIP_LOWLEVEL_INIT
wdenkfe8c2802002-11-03 00:38:21 +0000182 bl cpu_init_crit
183#endif
184
Albert ARIBAUDfacdae52013-01-08 10:18:02 +0000185 bl _main
Heiko Schocher271a2402010-09-17 13:10:43 +0200186
187/*------------------------------------------------------------------------------*/
188
189/*
190 * void relocate_code (addr_sp, gd, addr_moni)
191 *
192 * This "function" does not return, instead it continues in RAM
193 * after relocating the monitor code.
194 *
195 */
196 .globl relocate_code
197relocate_code:
198 mov r4, r0 /* save addr_sp */
199 mov r5, r1 /* save addr of gd */
200 mov r6, r2 /* save addr of destination */
Heiko Schocher271a2402010-09-17 13:10:43 +0200201
Heiko Schocher271a2402010-09-17 13:10:43 +0200202 adr r0, _start
Andreas Bießmann007b38f2010-12-01 00:58:34 +0100203 cmp r0, r6
Zhong Hongbo8c2ef802012-09-01 20:49:52 +0000204 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
Albert ARIBAUDfacdae52013-01-08 10:18:02 +0000205 beq relocate_done /* skip relocation */
Andreas Bießmann8cfbda92010-12-01 00:58:33 +0100206 mov r1, r6 /* r1 <- scratch for copy_loop */
Albert Aribaud126897e2010-11-25 22:45:02 +0100207 ldr r3, _bss_start_ofs
208 add r2, r0, r3 /* r2 <- source end address */
Heiko Schocher271a2402010-09-17 13:10:43 +0200209
Heiko Schocher271a2402010-09-17 13:10:43 +0200210copy_loop:
211 ldmia r0!, {r9-r10} /* copy from source address [r0] */
Andreas Bießmann8cfbda92010-12-01 00:58:33 +0100212 stmia r1!, {r9-r10} /* copy to target address [r1] */
Albert Aribaud0668d162010-10-05 16:06:39 +0200213 cmp r0, r2 /* until source end address [r2] */
214 blo copy_loop
Heiko Schocher271a2402010-09-17 13:10:43 +0200215
Aneesh V552a3192011-07-13 05:11:07 +0000216#ifndef CONFIG_SPL_BUILD
Albert Aribaud126897e2010-11-25 22:45:02 +0100217 /*
218 * fix .rel.dyn relocations
219 */
220 ldr r0, _TEXT_BASE /* r0 <- Text base */
Andreas Bießmann8cfbda92010-12-01 00:58:33 +0100221 sub r9, r6, r0 /* r9 <- relocation offset */
Albert Aribaud126897e2010-11-25 22:45:02 +0100222 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
223 add r10, r10, r0 /* r10 <- sym table in FLASH */
224 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
225 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
226 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
227 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
Heiko Schocher271a2402010-09-17 13:10:43 +0200228fixloop:
Albert Aribaud126897e2010-11-25 22:45:02 +0100229 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
230 add r0, r0, r9 /* r0 <- location to fix up in RAM */
231 ldr r1, [r2, #4]
Andreas Bießmann318cea12010-12-01 00:58:35 +0100232 and r7, r1, #0xff
233 cmp r7, #23 /* relative fixup? */
Albert Aribaud126897e2010-11-25 22:45:02 +0100234 beq fixrel
Andreas Bießmann318cea12010-12-01 00:58:35 +0100235 cmp r7, #2 /* absolute fixup? */
Albert Aribaud126897e2010-11-25 22:45:02 +0100236 beq fixabs
237 /* ignore unknown type of fixup */
238 b fixnext
239fixabs:
240 /* absolute fix: set location to (offset) symbol value */
241 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
242 add r1, r10, r1 /* r1 <- address of symbol in table */
243 ldr r1, [r1, #4] /* r1 <- symbol value */
Wolfgang Denk899cdd12010-12-09 11:26:24 +0100244 add r1, r1, r9 /* r1 <- relocated sym addr */
Albert Aribaud126897e2010-11-25 22:45:02 +0100245 b fixnext
246fixrel:
247 /* relative fix: increase location by offset */
248 ldr r1, [r0]
249 add r1, r1, r9
250fixnext:
251 str r1, [r0]
252 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
Heiko Schocher271a2402010-09-17 13:10:43 +0200253 cmp r2, r3
Wolfgang Denk98dd07c2010-10-23 23:22:38 +0200254 blo fixloop
Heiko Schocher271a2402010-09-17 13:10:43 +0200255#endif
Heiko Schocher271a2402010-09-17 13:10:43 +0200256
Albert ARIBAUDfacdae52013-01-08 10:18:02 +0000257relocate_done:
Heiko Schocher271a2402010-09-17 13:10:43 +0200258
Heiko Schocher271a2402010-09-17 13:10:43 +0200259 mov pc, lr
260
Albert Aribaud126897e2010-11-25 22:45:02 +0100261_rel_dyn_start_ofs:
262 .word __rel_dyn_start - _start
263_rel_dyn_end_ofs:
264 .word __rel_dyn_end - _start
265_dynsym_start_ofs:
266 .word __dynsym_start - _start
267
Albert ARIBAUDfacdae52013-01-08 10:18:02 +0000268 .globl c_runtime_cpu_setup
269c_runtime_cpu_setup:
270
271 mov pc, lr
272
wdenkfe8c2802002-11-03 00:38:21 +0000273/*
274 *************************************************************************
275 *
276 * CPU_init_critical registers
277 *
278 * setup important registers
279 * setup memory timing
280 *
281 *************************************************************************
282 */
283
284
Wolfgang Denkf2e11a72006-04-03 15:46:10 +0200285#ifndef CONFIG_SKIP_LOWLEVEL_INIT
wdenkfe8c2802002-11-03 00:38:21 +0000286cpu_init_crit:
287 /*
288 * flush v4 I/D caches
289 */
290 mov r0, #0
291 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
292 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
293
294 /*
295 * disable MMU stuff and caches
296 */
297 mrc p15, 0, r0, c1, c0, 0
298 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
299 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
300 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
301 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
302 mcr p15, 0, r0, c1, c0, 0
303
wdenkfe8c2802002-11-03 00:38:21 +0000304 /*
305 * before relocating, we have to setup RAM timing
306 * because memory timing is board-dependend, you will
wdenk336b2bc2005-04-02 23:52:25 +0000307 * find a lowlevel_init.S in your board directory.
wdenkfe8c2802002-11-03 00:38:21 +0000308 */
309 mov ip, lr
Peter Pearsede5b02c2007-08-14 10:10:52 +0100310
wdenk336b2bc2005-04-02 23:52:25 +0000311 bl lowlevel_init
Ulf Samuelsson07f9b4e2009-03-27 23:26:43 +0100312
wdenkfe8c2802002-11-03 00:38:21 +0000313 mov lr, ip
wdenkfe8c2802002-11-03 00:38:21 +0000314 mov pc, lr
Wolfgang Denkf2e11a72006-04-03 15:46:10 +0200315#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
wdenkfe8c2802002-11-03 00:38:21 +0000316
wdenkfe8c2802002-11-03 00:38:21 +0000317/*
318 *************************************************************************
319 *
320 * Interrupt handling
321 *
322 *************************************************************************
323 */
324
325@
326@ IRQ stack frame.
327@
328#define S_FRAME_SIZE 72
329
330#define S_OLD_R0 68
331#define S_PSR 64
332#define S_PC 60
333#define S_LR 56
334#define S_SP 52
335
336#define S_IP 48
337#define S_FP 44
338#define S_R10 40
339#define S_R9 36
340#define S_R8 32
341#define S_R7 28
342#define S_R6 24
343#define S_R5 20
344#define S_R4 16
345#define S_R3 12
346#define S_R2 8
347#define S_R1 4
348#define S_R0 0
349
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900350#define MODE_SVC 0x13
351#define I_BIT 0x80
wdenkfe8c2802002-11-03 00:38:21 +0000352
353/*
354 * use bad_save_user_regs for abort/prefetch/undef/swi ...
355 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
356 */
357
358 .macro bad_save_user_regs
359 sub sp, sp, #S_FRAME_SIZE
360 stmia sp, {r0 - r12} @ Calling r0-r12
Heiko Schocher271a2402010-09-17 13:10:43 +0200361 ldr r2, IRQ_STACK_START_IN
wdenkf4688a22003-05-28 08:06:31 +0000362 ldmia r2, {r2 - r3} @ get pc, cpsr
wdenkfe8c2802002-11-03 00:38:21 +0000363 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
364
365 add r5, sp, #S_SP
366 mov r1, lr
wdenkf4688a22003-05-28 08:06:31 +0000367 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
wdenkfe8c2802002-11-03 00:38:21 +0000368 mov r0, sp
369 .endm
370
371 .macro irq_save_user_regs
372 sub sp, sp, #S_FRAME_SIZE
373 stmia sp, {r0 - r12} @ Calling r0-r12
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900374 add r7, sp, #S_PC
375 stmdb r7, {sp, lr}^ @ Calling SP, LR
376 str lr, [r7, #0] @ Save calling PC
377 mrs r6, spsr
378 str r6, [r7, #4] @ Save CPSR
379 str r0, [r7, #8] @ Save OLD_R0
wdenkfe8c2802002-11-03 00:38:21 +0000380 mov r0, sp
381 .endm
382
383 .macro irq_restore_user_regs
384 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
385 mov r0, r0
386 ldr lr, [sp, #S_PC] @ Get PC
387 add sp, sp, #S_FRAME_SIZE
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900388 /* return & move spsr_svc into cpsr */
389 subs pc, lr, #4
wdenkfe8c2802002-11-03 00:38:21 +0000390 .endm
391
392 .macro get_bad_stack
Heiko Schocher271a2402010-09-17 13:10:43 +0200393 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
wdenkfe8c2802002-11-03 00:38:21 +0000394
395 str lr, [r13] @ save caller lr / spsr
396 mrs lr, spsr
kevin.morfitt@fearnside-systems.co.ukd1cacc72009-10-10 13:30:22 +0900397 str lr, [r13, #4]
wdenkfe8c2802002-11-03 00:38:21 +0000398
399 mov r13, #MODE_SVC @ prepare SVC-Mode
400 @ msr spsr_c, r13
401 msr spsr, r13
402 mov lr, pc
403 movs pc, lr
404 .endm
405
406 .macro get_irq_stack @ setup IRQ stack
407 ldr sp, IRQ_STACK_START
408 .endm
409
410 .macro get_fiq_stack @ setup FIQ stack
411 ldr sp, FIQ_STACK_START
412 .endm
413
414/*
415 * exception handlers
416 */
417 .align 5
418undefined_instruction:
419 get_bad_stack
420 bad_save_user_regs
Wolfgang Denka1be4762008-05-20 16:00:29 +0200421 bl do_undefined_instruction
wdenkfe8c2802002-11-03 00:38:21 +0000422
423 .align 5
424software_interrupt:
425 get_bad_stack
426 bad_save_user_regs
Wolfgang Denka1be4762008-05-20 16:00:29 +0200427 bl do_software_interrupt
wdenkfe8c2802002-11-03 00:38:21 +0000428
429 .align 5
430prefetch_abort:
431 get_bad_stack
432 bad_save_user_regs
Wolfgang Denka1be4762008-05-20 16:00:29 +0200433 bl do_prefetch_abort
wdenkfe8c2802002-11-03 00:38:21 +0000434
435 .align 5
436data_abort:
437 get_bad_stack
438 bad_save_user_regs
Wolfgang Denka1be4762008-05-20 16:00:29 +0200439 bl do_data_abort
wdenkfe8c2802002-11-03 00:38:21 +0000440
441 .align 5
442not_used:
443 get_bad_stack
444 bad_save_user_regs
Wolfgang Denka1be4762008-05-20 16:00:29 +0200445 bl do_not_used
wdenkfe8c2802002-11-03 00:38:21 +0000446
447#ifdef CONFIG_USE_IRQ
448
449 .align 5
450irq:
451 get_irq_stack
452 irq_save_user_regs
Wolfgang Denka1be4762008-05-20 16:00:29 +0200453 bl do_irq
wdenkfe8c2802002-11-03 00:38:21 +0000454 irq_restore_user_regs
455
456 .align 5
457fiq:
458 get_fiq_stack
459 /* someone ought to write a more effiction fiq_save_user_regs */
460 irq_save_user_regs
Wolfgang Denka1be4762008-05-20 16:00:29 +0200461 bl do_fiq
wdenkfe8c2802002-11-03 00:38:21 +0000462 irq_restore_user_regs
463
464#else
465
466 .align 5
467irq:
468 get_bad_stack
469 bad_save_user_regs
Wolfgang Denka1be4762008-05-20 16:00:29 +0200470 bl do_irq
wdenkfe8c2802002-11-03 00:38:21 +0000471
472 .align 5
473fiq:
474 get_bad_stack
475 bad_save_user_regs
Wolfgang Denka1be4762008-05-20 16:00:29 +0200476 bl do_fiq
wdenkfe8c2802002-11-03 00:38:21 +0000477
478#endif