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Simon Glass4ecaa6d2015-08-30 16:55:37 -06001/*
2 * Copyright (c) 2013 Google, Inc
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <clk.h>
9#include <dm.h>
Simon Glass4bb9ce42016-07-04 11:58:27 -060010#include <dt-structs.h>
Simon Glass4ecaa6d2015-08-30 16:55:37 -060011#include <dwmmc.h>
12#include <errno.h>
Simon Glass4bb9ce42016-07-04 11:58:27 -060013#include <mapmem.h>
Simon Glass947fd982016-01-21 19:43:34 -070014#include <pwrseq.h>
Simon Glass4ecaa6d2015-08-30 16:55:37 -060015#include <syscon.h>
Simon Glass947fd982016-01-21 19:43:34 -070016#include <asm/gpio.h>
Simon Glass4ecaa6d2015-08-30 16:55:37 -060017#include <asm/arch/clock.h>
18#include <asm/arch/periph.h>
19#include <linux/err.h>
20
21DECLARE_GLOBAL_DATA_PTR;
22
Simon Glassae696102016-05-14 14:03:08 -060023struct rockchip_mmc_plat {
Simon Glass4bb9ce42016-07-04 11:58:27 -060024#if CONFIG_IS_ENABLED(OF_PLATDATA)
25 struct dtd_rockchip_rk3288_dw_mshc dtplat;
26#endif
Simon Glassae696102016-05-14 14:03:08 -060027 struct mmc_config cfg;
28 struct mmc mmc;
29};
30
Simon Glass4ecaa6d2015-08-30 16:55:37 -060031struct rockchip_dwmmc_priv {
Stephen Warrena9622432016-06-17 09:44:00 -060032 struct clk clk;
Simon Glass4ecaa6d2015-08-30 16:55:37 -060033 struct dwmci_host host;
Simon Glass4188d942016-07-04 11:58:26 -060034 int fifo_depth;
35 bool fifo_mode;
36 u32 minmax[2];
Simon Glass4ecaa6d2015-08-30 16:55:37 -060037};
38
39static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq)
40{
41 struct udevice *dev = host->priv;
42 struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
43 int ret;
44
Stephen Warrena9622432016-06-17 09:44:00 -060045 ret = clk_set_rate(&priv->clk, freq);
Simon Glass4ecaa6d2015-08-30 16:55:37 -060046 if (ret < 0) {
Xu Ziyuanb7df12d2017-04-16 17:44:42 +080047 printf("%s: err=%d\n", __func__, ret);
Simon Glass4ecaa6d2015-08-30 16:55:37 -060048 return ret;
49 }
50
51 return freq;
52}
53
54static int rockchip_dwmmc_ofdata_to_platdata(struct udevice *dev)
55{
Simon Glass4bb9ce42016-07-04 11:58:27 -060056#if !CONFIG_IS_ENABLED(OF_PLATDATA)
Simon Glass4ecaa6d2015-08-30 16:55:37 -060057 struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
58 struct dwmci_host *host = &priv->host;
59
60 host->name = dev->name;
Simon Glassba1dea42017-05-17 17:18:05 -060061 host->ioaddr = (void *)devfdt_get_addr(dev);
Simon Glassdd79d6e2017-01-17 16:52:55 -070062 host->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
Simon Glass4ecaa6d2015-08-30 16:55:37 -060063 "bus-width", 4);
64 host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk;
65 host->priv = dev;
66
huang lin8799fc12015-11-18 09:37:25 +080067 /* use non-removeable as sdcard and emmc as judgement */
Simon Glassdd79d6e2017-01-17 16:52:55 -070068 if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev), "non-removable"))
huang linb06352f2016-01-08 14:06:49 +080069 host->dev_index = 0;
70 else
huang lin8799fc12015-11-18 09:37:25 +080071 host->dev_index = 1;
Simon Glass4ecaa6d2015-08-30 16:55:37 -060072
Simon Glassdd79d6e2017-01-17 16:52:55 -070073 priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
Simon Glass4188d942016-07-04 11:58:26 -060074 "fifo-depth", 0);
75 if (priv->fifo_depth < 0)
76 return -EINVAL;
Simon Glassdd79d6e2017-01-17 16:52:55 -070077 priv->fifo_mode = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
Simon Glass4188d942016-07-04 11:58:26 -060078 "fifo-mode");
Philipp Tomsich56b38d82017-04-25 09:52:07 +020079
80 /*
81 * 'clock-freq-min-max' is deprecated
82 * (see https://github.com/torvalds/linux/commit/b023030f10573de738bbe8df63d43acab64c9f7b)
83 */
Simon Glassdd79d6e2017-01-17 16:52:55 -070084 if (fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
Philipp Tomsich56b38d82017-04-25 09:52:07 +020085 "clock-freq-min-max", priv->minmax, 2)) {
86 int val = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
87 "max-frequency", -EINVAL);
88
89 if (val < 0)
90 return val;
91
92 priv->minmax[0] = 400000; /* 400 kHz */
93 priv->minmax[1] = val;
94 } else {
95 debug("%s: 'clock-freq-min-max' property was deprecated.\n",
96 __func__);
97 }
Simon Glass4bb9ce42016-07-04 11:58:27 -060098#endif
Simon Glass4ecaa6d2015-08-30 16:55:37 -060099 return 0;
100}
101
102static int rockchip_dwmmc_probe(struct udevice *dev)
103{
Simon Glassae696102016-05-14 14:03:08 -0600104 struct rockchip_mmc_plat *plat = dev_get_platdata(dev);
Simon Glass4ecaa6d2015-08-30 16:55:37 -0600105 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
106 struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
107 struct dwmci_host *host = &priv->host;
Simon Glass947fd982016-01-21 19:43:34 -0700108 struct udevice *pwr_dev __maybe_unused;
Simon Glass4ecaa6d2015-08-30 16:55:37 -0600109 int ret;
110
Simon Glass4bb9ce42016-07-04 11:58:27 -0600111#if CONFIG_IS_ENABLED(OF_PLATDATA)
112 struct dtd_rockchip_rk3288_dw_mshc *dtplat = &plat->dtplat;
113
114 host->name = dev->name;
115 host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
116 host->buswidth = dtplat->bus_width;
117 host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk;
118 host->priv = dev;
119 host->dev_index = 0;
120 priv->fifo_depth = dtplat->fifo_depth;
121 priv->fifo_mode = 0;
122 memcpy(priv->minmax, dtplat->clock_freq_min_max, sizeof(priv->minmax));
123
124 ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk);
125 if (ret < 0)
126 return ret;
127#else
Xu Ziyuanb7df12d2017-04-16 17:44:42 +0800128 ret = clk_get_by_name(dev, "ciu", &priv->clk);
Simon Glass8d32f4b2016-01-21 19:43:38 -0700129 if (ret < 0)
Simon Glass4ecaa6d2015-08-30 16:55:37 -0600130 return ret;
Simon Glass4bb9ce42016-07-04 11:58:27 -0600131#endif
huang linb1b71cd2015-11-17 14:20:24 +0800132 host->fifoth_val = MSIZE(0x2) |
Simon Glass4188d942016-07-04 11:58:26 -0600133 RX_WMARK(priv->fifo_depth / 2 - 1) |
134 TX_WMARK(priv->fifo_depth / 2);
huang linb1b71cd2015-11-17 14:20:24 +0800135
Simon Glass4188d942016-07-04 11:58:26 -0600136 host->fifo_mode = priv->fifo_mode;
huang linb1b71cd2015-11-17 14:20:24 +0800137
Simon Glass947fd982016-01-21 19:43:34 -0700138#ifdef CONFIG_PWRSEQ
139 /* Enable power if needed */
140 ret = uclass_get_device_by_phandle(UCLASS_PWRSEQ, dev, "mmc-pwrseq",
141 &pwr_dev);
142 if (!ret) {
143 ret = pwrseq_set_power(pwr_dev, true);
144 if (ret)
145 return ret;
146 }
147#endif
Jaehoon Chungbf819d02016-09-23 19:13:16 +0900148 dwmci_setup_cfg(&plat->cfg, host, priv->minmax[1], priv->minmax[0]);
Simon Glassae696102016-05-14 14:03:08 -0600149 host->mmc = &plat->mmc;
Simon Glassae696102016-05-14 14:03:08 -0600150 host->mmc->priv = &priv->host;
Simon Glass77ca42b2016-05-01 13:52:34 -0600151 host->mmc->dev = dev;
Simon Glass4ecaa6d2015-08-30 16:55:37 -0600152 upriv->mmc = host->mmc;
153
Simon Glassfaeef3b2016-06-12 23:30:24 -0600154 return dwmci_probe(dev);
Simon Glass4ecaa6d2015-08-30 16:55:37 -0600155}
156
Simon Glassae696102016-05-14 14:03:08 -0600157static int rockchip_dwmmc_bind(struct udevice *dev)
158{
Simon Glassae696102016-05-14 14:03:08 -0600159 struct rockchip_mmc_plat *plat = dev_get_platdata(dev);
Simon Glassae696102016-05-14 14:03:08 -0600160
Masahiro Yamadacdb67f32016-09-06 22:17:32 +0900161 return dwmci_bind(dev, &plat->mmc, &plat->cfg);
Simon Glassae696102016-05-14 14:03:08 -0600162}
163
Simon Glass4ecaa6d2015-08-30 16:55:37 -0600164static const struct udevice_id rockchip_dwmmc_ids[] = {
165 { .compatible = "rockchip,rk3288-dw-mshc" },
166 { }
167};
168
169U_BOOT_DRIVER(rockchip_dwmmc_drv) = {
Simon Glass4bb9ce42016-07-04 11:58:27 -0600170 .name = "rockchip_rk3288_dw_mshc",
Simon Glass4ecaa6d2015-08-30 16:55:37 -0600171 .id = UCLASS_MMC,
172 .of_match = rockchip_dwmmc_ids,
173 .ofdata_to_platdata = rockchip_dwmmc_ofdata_to_platdata,
Simon Glassfaeef3b2016-06-12 23:30:24 -0600174 .ops = &dm_dwmci_ops,
Simon Glassae696102016-05-14 14:03:08 -0600175 .bind = rockchip_dwmmc_bind,
Simon Glass4ecaa6d2015-08-30 16:55:37 -0600176 .probe = rockchip_dwmmc_probe,
177 .priv_auto_alloc_size = sizeof(struct rockchip_dwmmc_priv),
Simon Glassae696102016-05-14 14:03:08 -0600178 .platdata_auto_alloc_size = sizeof(struct rockchip_mmc_plat),
Simon Glass4ecaa6d2015-08-30 16:55:37 -0600179};
Simon Glass947fd982016-01-21 19:43:34 -0700180
181#ifdef CONFIG_PWRSEQ
182static int rockchip_dwmmc_pwrseq_set_power(struct udevice *dev, bool enable)
183{
184 struct gpio_desc reset;
185 int ret;
186
187 ret = gpio_request_by_name(dev, "reset-gpios", 0, &reset, GPIOD_IS_OUT);
188 if (ret)
189 return ret;
190 dm_gpio_set_value(&reset, 1);
191 udelay(1);
192 dm_gpio_set_value(&reset, 0);
193 udelay(200);
194
195 return 0;
196}
197
198static const struct pwrseq_ops rockchip_dwmmc_pwrseq_ops = {
199 .set_power = rockchip_dwmmc_pwrseq_set_power,
200};
201
202static const struct udevice_id rockchip_dwmmc_pwrseq_ids[] = {
203 { .compatible = "mmc-pwrseq-emmc" },
204 { }
205};
206
207U_BOOT_DRIVER(rockchip_dwmmc_pwrseq_drv) = {
208 .name = "mmc_pwrseq_emmc",
209 .id = UCLASS_PWRSEQ,
210 .of_match = rockchip_dwmmc_pwrseq_ids,
211 .ops = &rockchip_dwmmc_pwrseq_ops,
212};
213#endif