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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Marek Vasut32ada572015-08-01 21:35:18 +02002/*
3 * Copyright (C) 2015 Marek Vasut <marex@denx.de>
Marek Vasut32ada572015-08-01 21:35:18 +02004 */
5
Tom Riniabb9a042024-05-18 20:20:43 -06006#include <common.h>
Marek Vasut32ada572015-08-01 21:35:18 +02007#include <errno.h>
8#include <asm/arch/sdram.h>
Marek Vasut32ada572015-08-01 21:35:18 +02009
Marek Vasut372f70d2015-08-10 21:21:07 +020010/* Board-specific header. */
11#include <qts/sdram_config.h>
Marek Vasut3384e742015-08-02 17:15:19 +020012
Marek Vasut32ada572015-08-01 21:35:18 +020013static const struct socfpga_sdram_config sdram_config = {
14 .ctrl_cfg =
Tom Rinidcdd3bd2022-10-28 20:27:14 -040015 (CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<
Marek Vasut32ada572015-08-01 21:35:18 +020016 SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -040017 (CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL <<
Marek Vasut32ada572015-08-01 21:35:18 +020018 SDR_CTRLGRP_CTRLCFG_MEMBL_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -040019 (CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER <<
Marek Vasut32ada572015-08-01 21:35:18 +020020 SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -040021 (CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN <<
Marek Vasut32ada572015-08-01 21:35:18 +020022 SDR_CTRLGRP_CTRLCFG_ECCEN_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -040023 (CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN <<
Marek Vasut32ada572015-08-01 21:35:18 +020024 SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -040025 (CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN <<
Marek Vasut32ada572015-08-01 21:35:18 +020026 SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -040027 (CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT <<
Marek Vasut32ada572015-08-01 21:35:18 +020028 SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -040029 (CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN <<
Marek Vasut32ada572015-08-01 21:35:18 +020030 SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -040031 (CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS <<
Marek Vasut32ada572015-08-01 21:35:18 +020032 SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB),
33 .dram_timing1 =
Tom Rinidcdd3bd2022-10-28 20:27:14 -040034 (CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL <<
Marek Vasut32ada572015-08-01 21:35:18 +020035 SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -040036 (CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL <<
Marek Vasut32ada572015-08-01 21:35:18 +020037 SDR_CTRLGRP_DRAMTIMING1_TAL_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -040038 (CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL <<
Marek Vasut32ada572015-08-01 21:35:18 +020039 SDR_CTRLGRP_DRAMTIMING1_TCL_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -040040 (CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD <<
Marek Vasut32ada572015-08-01 21:35:18 +020041 SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -040042 (CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW <<
Marek Vasut32ada572015-08-01 21:35:18 +020043 SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -040044 (CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC <<
Marek Vasut32ada572015-08-01 21:35:18 +020045 SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB),
46 .dram_timing2 =
Tom Rinidcdd3bd2022-10-28 20:27:14 -040047 (CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI <<
Marek Vasut32ada572015-08-01 21:35:18 +020048 SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -040049 (CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD <<
Marek Vasut32ada572015-08-01 21:35:18 +020050 SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -040051 (CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP <<
Marek Vasut32ada572015-08-01 21:35:18 +020052 SDR_CTRLGRP_DRAMTIMING2_TRP_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -040053 (CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR <<
Marek Vasut32ada572015-08-01 21:35:18 +020054 SDR_CTRLGRP_DRAMTIMING2_TWR_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -040055 (CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR <<
Marek Vasut32ada572015-08-01 21:35:18 +020056 SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB),
57 .dram_timing3 =
Tom Rinidcdd3bd2022-10-28 20:27:14 -040058 (CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP <<
Marek Vasut32ada572015-08-01 21:35:18 +020059 SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -040060 (CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS <<
Marek Vasut32ada572015-08-01 21:35:18 +020061 SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -040062 (CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC <<
Marek Vasut32ada572015-08-01 21:35:18 +020063 SDR_CTRLGRP_DRAMTIMING3_TRC_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -040064 (CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD <<
Marek Vasut32ada572015-08-01 21:35:18 +020065 SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -040066 (CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD <<
Marek Vasut32ada572015-08-01 21:35:18 +020067 SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB),
68 .dram_timing4 =
Tom Rinidcdd3bd2022-10-28 20:27:14 -040069 (CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT <<
Marek Vasut32ada572015-08-01 21:35:18 +020070 SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -040071 (CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT <<
Marek Vasut32ada572015-08-01 21:35:18 +020072 SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB),
73 .lowpwr_timing =
Tom Rinidcdd3bd2022-10-28 20:27:14 -040074 (CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES <<
Marek Vasut32ada572015-08-01 21:35:18 +020075 SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -040076 (CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES <<
Marek Vasut32ada572015-08-01 21:35:18 +020077 SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB),
78 .dram_odt =
Tom Rinidcdd3bd2022-10-28 20:27:14 -040079 (CFG_HPS_SDR_CTRLCFG_DRAMODT_READ <<
Marek Vasut32ada572015-08-01 21:35:18 +020080 SDR_CTRLGRP_DRAMODT_READ_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -040081 (CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
Marek Vasut32ada572015-08-01 21:35:18 +020082 SDR_CTRLGRP_DRAMODT_WRITE_LSB),
Tom Rinidcdd3bd2022-10-28 20:27:14 -040083#if (CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 2) /* DDR3 */
Chin Liang See3ea59512016-09-21 10:25:56 +080084 .extratime1 =
Tom Rinidcdd3bd2022-10-28 20:27:14 -040085 (CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR <<
Marek Vasut6bccacf2019-10-18 00:22:31 +020086 SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -040087 (CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC <<
Marek Vasut6bccacf2019-10-18 00:22:31 +020088 SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -040089 (CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP <<
Marek Vasut6bccacf2019-10-18 00:22:31 +020090 SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB),
91#endif
Marek Vasut32ada572015-08-01 21:35:18 +020092 .dram_addrw =
Tom Rinidcdd3bd2022-10-28 20:27:14 -040093 (CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
Marek Vasut32ada572015-08-01 21:35:18 +020094 SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -040095 (CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS <<
Marek Vasut32ada572015-08-01 21:35:18 +020096 SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -040097 (CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS <<
Marek Vasut32ada572015-08-01 21:35:18 +020098 SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -040099 ((CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) <<
Marek Vasut32ada572015-08-01 21:35:18 +0200100 SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB),
101 .dram_if_width =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400102 (CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH <<
Marek Vasut32ada572015-08-01 21:35:18 +0200103 SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB),
104 .dram_dev_width =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400105 (CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH <<
Marek Vasut32ada572015-08-01 21:35:18 +0200106 SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB),
107 .dram_intr =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400108 (CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN <<
Marek Vasut32ada572015-08-01 21:35:18 +0200109 SDR_CTRLGRP_DRAMINTR_INTREN_LSB),
110 .lowpwr_eq =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400111 (CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK <<
Marek Vasut32ada572015-08-01 21:35:18 +0200112 SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB),
113 .static_cfg =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400114 (CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL <<
Marek Vasut32ada572015-08-01 21:35:18 +0200115 SDR_CTRLGRP_STATICCFG_MEMBL_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400116 (CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA <<
Marek Vasut32ada572015-08-01 21:35:18 +0200117 SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB),
118 .ctrl_width =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400119 (CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH <<
Marek Vasut32ada572015-08-01 21:35:18 +0200120 SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB),
121 .cport_width =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400122 (CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH <<
Marek Vasut32ada572015-08-01 21:35:18 +0200123 SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB),
124 .cport_wmap =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400125 (CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP <<
Marek Vasut32ada572015-08-01 21:35:18 +0200126 SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB),
127 .cport_rmap =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400128 (CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP <<
Marek Vasut32ada572015-08-01 21:35:18 +0200129 SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB),
130 .rfifo_cmap =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400131 (CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP <<
Marek Vasut32ada572015-08-01 21:35:18 +0200132 SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB),
133 .wfifo_cmap =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400134 (CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP <<
Marek Vasut32ada572015-08-01 21:35:18 +0200135 SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB),
136 .cport_rdwr =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400137 (CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR <<
Marek Vasut32ada572015-08-01 21:35:18 +0200138 SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB),
139 .port_cfg =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400140 (CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN <<
Marek Vasut32ada572015-08-01 21:35:18 +0200141 SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB),
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400142 .fpgaport_rst = CFG_HPS_SDR_CTRLCFG_FPGAPORTRST,
Marek Vasut32ada572015-08-01 21:35:18 +0200143 .fifo_cfg =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400144 (CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE <<
Marek Vasut32ada572015-08-01 21:35:18 +0200145 SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400146 (CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC <<
Marek Vasut32ada572015-08-01 21:35:18 +0200147 SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB),
148 .mp_priority =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400149 (CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY <<
Marek Vasut32ada572015-08-01 21:35:18 +0200150 SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB),
151 .mp_weight0 =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400152 (CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 <<
Marek Vasut32ada572015-08-01 21:35:18 +0200153 SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB),
154 .mp_weight1 =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400155 (CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 <<
Marek Vasut32ada572015-08-01 21:35:18 +0200156 SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400157 (CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 <<
Marek Vasut32ada572015-08-01 21:35:18 +0200158 SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB),
159 .mp_weight2 =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400160 (CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 <<
Marek Vasut32ada572015-08-01 21:35:18 +0200161 SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB),
162 .mp_weight3 =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400163 (CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 <<
Marek Vasut32ada572015-08-01 21:35:18 +0200164 SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB),
165 .mp_pacing0 =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400166 (CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<
Marek Vasut32ada572015-08-01 21:35:18 +0200167 SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB),
168 .mp_pacing1 =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400169 (CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 <<
Marek Vasut32ada572015-08-01 21:35:18 +0200170 SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400171 (CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
Marek Vasut32ada572015-08-01 21:35:18 +0200172 SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB),
173 .mp_pacing2 =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400174 (CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 <<
Marek Vasut32ada572015-08-01 21:35:18 +0200175 SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB),
176 .mp_pacing3 =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400177 (CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<
Marek Vasut32ada572015-08-01 21:35:18 +0200178 SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB),
179 .mp_threshold0 =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400180 (CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
Marek Vasut32ada572015-08-01 21:35:18 +0200181 SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB),
182 .mp_threshold1 =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400183 (CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<
Marek Vasut32ada572015-08-01 21:35:18 +0200184 SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB),
185 .mp_threshold2 =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400186 (CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
Marek Vasut32ada572015-08-01 21:35:18 +0200187 SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB),
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400188 .phy_ctrl0 = CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0,
Marek Vasut32ada572015-08-01 21:35:18 +0200189};
190
Marek Vasut39b620e2015-08-02 18:12:08 +0200191static const struct socfpga_sdram_rw_mgr_config rw_mgr_config = {
192 .activate_0_and_1 = RW_MGR_ACTIVATE_0_AND_1,
193 .activate_0_and_1_wait1 = RW_MGR_ACTIVATE_0_AND_1_WAIT1,
194 .activate_0_and_1_wait2 = RW_MGR_ACTIVATE_0_AND_1_WAIT2,
Marek Vasut39b620e2015-08-02 18:12:08 +0200195 .clear_dqs_enable = RW_MGR_CLEAR_DQS_ENABLE,
196 .guaranteed_read = RW_MGR_GUARANTEED_READ,
197 .guaranteed_read_cont = RW_MGR_GUARANTEED_READ_CONT,
198 .guaranteed_write = RW_MGR_GUARANTEED_WRITE,
199 .guaranteed_write_wait0 = RW_MGR_GUARANTEED_WRITE_WAIT0,
200 .guaranteed_write_wait1 = RW_MGR_GUARANTEED_WRITE_WAIT1,
201 .guaranteed_write_wait2 = RW_MGR_GUARANTEED_WRITE_WAIT2,
202 .guaranteed_write_wait3 = RW_MGR_GUARANTEED_WRITE_WAIT3,
Marek Vasut39b620e2015-08-02 18:12:08 +0200203 .idle_loop1 = RW_MGR_IDLE_LOOP1,
204 .idle_loop2 = RW_MGR_IDLE_LOOP2,
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400205#if (CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 1) /* DDR2 */
Marek Vasut6bccacf2019-10-18 00:22:31 +0200206 .emr = RW_MGR_EMR,
207 .emr2 = RW_MGR_EMR2,
208 .emr3 = RW_MGR_EMR3,
209 .init_reset_0_cke_0 = RW_MGR_INIT_CKE_0,
210 .nop = RW_MGR_NOP,
211 .refresh = RW_MGR_REFRESH,
212 .mr_calib = RW_MGR_MR_CALIB,
213 .mr_user = RW_MGR_MR_USER,
214 .mr_dll_reset = RW_MGR_MR_DLL_RESET,
215 .emr_ocd_enable = RW_MGR_EMR_OCD_ENABLE,
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400216#elif (CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 2) /* DDR3 */
Marek Vasut6bccacf2019-10-18 00:22:31 +0200217 .activate_1 = RW_MGR_ACTIVATE_1,
218 .idle = RW_MGR_IDLE,
Marek Vasut39b620e2015-08-02 18:12:08 +0200219 .init_reset_0_cke_0 = RW_MGR_INIT_RESET_0_CKE_0,
220 .init_reset_1_cke_0 = RW_MGR_INIT_RESET_1_CKE_0,
Marek Vasut6bccacf2019-10-18 00:22:31 +0200221 .mrs1 = RW_MGR_MRS1,
222 .mrs1_mirr = RW_MGR_MRS1_MIRR,
223 .mrs2 = RW_MGR_MRS2,
224 .mrs2_mirr = RW_MGR_MRS2_MIRR,
225 .mrs3 = RW_MGR_MRS3,
226 .mrs3_mirr = RW_MGR_MRS3_MIRR,
227 .refresh_all = RW_MGR_REFRESH_ALL,
228 .rreturn = RW_MGR_RETURN,
229 .sgle_read = RW_MGR_SGLE_READ,
230 .zqcl = RW_MGR_ZQCL,
231 .mrs0_dll_reset = RW_MGR_MRS0_DLL_RESET,
232 .mrs0_dll_reset_mirr = RW_MGR_MRS0_DLL_RESET_MIRR,
233 .mrs0_user = RW_MGR_MRS0_USER,
234 .mrs0_user_mirr = RW_MGR_MRS0_USER_MIRR,
235#else
236#error LPDDR2 and other DRAM types are not yet supported
237#endif
Marek Vasut39b620e2015-08-02 18:12:08 +0200238 .lfsr_wr_rd_bank_0 = RW_MGR_LFSR_WR_RD_BANK_0,
239 .lfsr_wr_rd_bank_0_data = RW_MGR_LFSR_WR_RD_BANK_0_DATA,
240 .lfsr_wr_rd_bank_0_dqs = RW_MGR_LFSR_WR_RD_BANK_0_DQS,
241 .lfsr_wr_rd_bank_0_nop = RW_MGR_LFSR_WR_RD_BANK_0_NOP,
242 .lfsr_wr_rd_bank_0_wait = RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
243 .lfsr_wr_rd_bank_0_wl_1 = RW_MGR_LFSR_WR_RD_BANK_0_WL_1,
244 .lfsr_wr_rd_dm_bank_0 = RW_MGR_LFSR_WR_RD_DM_BANK_0,
245 .lfsr_wr_rd_dm_bank_0_data = RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
246 .lfsr_wr_rd_dm_bank_0_dqs = RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
247 .lfsr_wr_rd_dm_bank_0_nop = RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
248 .lfsr_wr_rd_dm_bank_0_wait = RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
249 .lfsr_wr_rd_dm_bank_0_wl_1 = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1,
Marek Vasut39b620e2015-08-02 18:12:08 +0200250 .precharge_all = RW_MGR_PRECHARGE_ALL,
251 .read_b2b = RW_MGR_READ_B2B,
252 .read_b2b_wait1 = RW_MGR_READ_B2B_WAIT1,
253 .read_b2b_wait2 = RW_MGR_READ_B2B_WAIT2,
Marek Vasut39b620e2015-08-02 18:12:08 +0200254
255 .true_mem_data_mask_width = RW_MGR_TRUE_MEM_DATA_MASK_WIDTH,
256 .mem_address_mirroring = RW_MGR_MEM_ADDRESS_MIRRORING,
257 .mem_data_mask_width = RW_MGR_MEM_DATA_MASK_WIDTH,
258 .mem_data_width = RW_MGR_MEM_DATA_WIDTH,
259 .mem_dq_per_read_dqs = RW_MGR_MEM_DQ_PER_READ_DQS,
260 .mem_dq_per_write_dqs = RW_MGR_MEM_DQ_PER_WRITE_DQS,
261 .mem_if_read_dqs_width = RW_MGR_MEM_IF_READ_DQS_WIDTH,
262 .mem_if_write_dqs_width = RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
263 .mem_number_of_cs_per_dimm = RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
264 .mem_number_of_ranks = RW_MGR_MEM_NUMBER_OF_RANKS,
265 .mem_virtual_groups_per_read_dqs =
266 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
267 .mem_virtual_groups_per_write_dqs =
268 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS,
269};
270
Simon Goldschmidtceab2692018-11-14 21:05:12 +0100271static const struct socfpga_sdram_io_config io_config = {
Marek Vasut3bf92042015-08-02 19:00:23 +0200272 .delay_per_dchain_tap = IO_DELAY_PER_DCHAIN_TAP,
273 .delay_per_dqs_en_dchain_tap = IO_DELAY_PER_DQS_EN_DCHAIN_TAP,
274 .delay_per_opa_tap = IO_DELAY_PER_OPA_TAP,
275 .dll_chain_length = IO_DLL_CHAIN_LENGTH,
276 .dqdqs_out_phase_max = IO_DQDQS_OUT_PHASE_MAX,
277 .dqs_en_delay_max = IO_DQS_EN_DELAY_MAX,
278 .dqs_en_delay_offset = IO_DQS_EN_DELAY_OFFSET,
279 .dqs_en_phase_max = IO_DQS_EN_PHASE_MAX,
280 .dqs_in_delay_max = IO_DQS_IN_DELAY_MAX,
281 .dqs_in_reserve = IO_DQS_IN_RESERVE,
282 .dqs_out_reserve = IO_DQS_OUT_RESERVE,
283 .io_in_delay_max = IO_IO_IN_DELAY_MAX,
284 .io_out1_delay_max = IO_IO_OUT1_DELAY_MAX,
285 .io_out2_delay_max = IO_IO_OUT2_DELAY_MAX,
286 .shift_dqs_en_when_shift_dqs = IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS,
287};
288
Simon Goldschmidtceab2692018-11-14 21:05:12 +0100289static const struct socfpga_sdram_misc_config misc_config = {
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400290#if (CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 1) /* DDR2 */
Marek Vasut6bccacf2019-10-18 00:22:31 +0200291 .afi_clk_freq = AFI_CLK_FREQ,
292#endif
Marek Vasutf00a6ea2015-08-02 19:18:47 +0200293 .afi_rate_ratio = AFI_RATE_RATIO,
294 .calib_lfifo_offset = CALIB_LFIFO_OFFSET,
295 .calib_vfifo_offset = CALIB_VFIFO_OFFSET,
296 .enable_super_quick_calibration = ENABLE_SUPER_QUICK_CALIBRATION,
297 .max_latency_count_width = MAX_LATENCY_COUNT_WIDTH,
298 .read_valid_fifo_size = READ_VALID_FIFO_SIZE,
299 .reg_file_init_seq_signature = REG_FILE_INIT_SEQ_SIGNATURE,
300 .tinit_cntr0_val = TINIT_CNTR0_VAL,
301 .tinit_cntr1_val = TINIT_CNTR1_VAL,
302 .tinit_cntr2_val = TINIT_CNTR2_VAL,
303 .treset_cntr0_val = TRESET_CNTR0_VAL,
304 .treset_cntr1_val = TRESET_CNTR1_VAL,
305 .treset_cntr2_val = TRESET_CNTR2_VAL,
306};
307
Marek Vasut32ada572015-08-01 21:35:18 +0200308const struct socfpga_sdram_config *socfpga_get_sdram_config(void)
309{
310 return &sdram_config;
311}
Marek Vasut3384e742015-08-02 17:15:19 +0200312
313void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem)
314{
315 *init = ac_rom_init;
316 *nelem = ARRAY_SIZE(ac_rom_init);
317}
318
319void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem)
320{
321 *init = inst_rom_init;
322 *nelem = ARRAY_SIZE(inst_rom_init);
323}
Marek Vasut39b620e2015-08-02 18:12:08 +0200324
325const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void)
326{
327 return &rw_mgr_config;
328}
Marek Vasut3bf92042015-08-02 19:00:23 +0200329
330const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void)
331{
332 return &io_config;
333}
Marek Vasutf00a6ea2015-08-02 19:18:47 +0200334
335const struct socfpga_sdram_misc_config *socfpga_get_sdram_misc_config(void)
336{
337 return &misc_config;
338}