global: Migrate CONFIG_HPS* symbols to the CFG namespace
Migrate all of CONFIG_HPS* to the CFG namespace.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
diff --git a/arch/arm/mach-socfpga/wrap_sdram_config.c b/arch/arm/mach-socfpga/wrap_sdram_config.c
index 4ea32e7..cd3a0f6 100644
--- a/arch/arm/mach-socfpga/wrap_sdram_config.c
+++ b/arch/arm/mach-socfpga/wrap_sdram_config.c
@@ -12,180 +12,180 @@
static const struct socfpga_sdram_config sdram_config = {
.ctrl_cfg =
- (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<
+ (CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<
SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL <<
+ (CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL <<
SDR_CTRLGRP_CTRLCFG_MEMBL_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER <<
+ (CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER <<
SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN <<
+ (CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN <<
SDR_CTRLGRP_CTRLCFG_ECCEN_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN <<
+ (CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN <<
SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN <<
+ (CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN <<
SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT <<
+ (CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT <<
SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN <<
+ (CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN <<
SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS <<
+ (CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS <<
SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB),
.dram_timing1 =
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL <<
SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL <<
SDR_CTRLGRP_DRAMTIMING1_TAL_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL <<
SDR_CTRLGRP_DRAMTIMING1_TCL_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD <<
SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW <<
SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC <<
SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB),
.dram_timing2 =
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI <<
SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD <<
SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP <<
SDR_CTRLGRP_DRAMTIMING2_TRP_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR <<
SDR_CTRLGRP_DRAMTIMING2_TWR_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR <<
SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB),
.dram_timing3 =
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP <<
SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS <<
SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC <<
SDR_CTRLGRP_DRAMTIMING3_TRC_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD <<
SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD <<
SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB),
.dram_timing4 =
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT <<
SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT <<
SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB),
.lowpwr_timing =
- (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES <<
+ (CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES <<
SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES <<
+ (CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES <<
SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB),
.dram_odt =
- (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMODT_READ <<
SDR_CTRLGRP_DRAMODT_READ_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
SDR_CTRLGRP_DRAMODT_WRITE_LSB),
-#if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 2) /* DDR3 */
+#if (CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 2) /* DDR3 */
.extratime1 =
- (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR <<
+ (CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR <<
SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC <<
+ (CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC <<
SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP <<
+ (CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP <<
SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB),
#endif
.dram_addrw =
- (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS <<
SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS <<
SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB) |
- ((CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) <<
+ ((CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) <<
SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB),
.dram_if_width =
- (CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH <<
SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB),
.dram_dev_width =
- (CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH <<
SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB),
.dram_intr =
- (CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN <<
+ (CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN <<
SDR_CTRLGRP_DRAMINTR_INTREN_LSB),
.lowpwr_eq =
- (CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK <<
+ (CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK <<
SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB),
.static_cfg =
- (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL <<
+ (CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL <<
SDR_CTRLGRP_STATICCFG_MEMBL_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA <<
+ (CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA <<
SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB),
.ctrl_width =
- (CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH <<
+ (CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH <<
SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB),
.cport_width =
- (CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH <<
+ (CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH <<
SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB),
.cport_wmap =
- (CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP <<
+ (CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP <<
SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB),
.cport_rmap =
- (CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP <<
+ (CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP <<
SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB),
.rfifo_cmap =
- (CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP <<
+ (CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP <<
SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB),
.wfifo_cmap =
- (CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP <<
+ (CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP <<
SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB),
.cport_rdwr =
- (CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR <<
+ (CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR <<
SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB),
.port_cfg =
- (CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN <<
+ (CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN <<
SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB),
- .fpgaport_rst = CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST,
+ .fpgaport_rst = CFG_HPS_SDR_CTRLCFG_FPGAPORTRST,
.fifo_cfg =
- (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE <<
+ (CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE <<
SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC <<
+ (CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC <<
SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB),
.mp_priority =
- (CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY <<
+ (CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY <<
SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB),
.mp_weight0 =
- (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 <<
+ (CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 <<
SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB),
.mp_weight1 =
- (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 <<
+ (CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 <<
SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 <<
+ (CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 <<
SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB),
.mp_weight2 =
- (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 <<
+ (CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 <<
SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB),
.mp_weight3 =
- (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 <<
+ (CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 <<
SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB),
.mp_pacing0 =
- (CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<
+ (CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<
SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB),
.mp_pacing1 =
- (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 <<
+ (CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 <<
SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB) |
- (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
+ (CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB),
.mp_pacing2 =
- (CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 <<
+ (CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 <<
SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB),
.mp_pacing3 =
- (CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<
+ (CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<
SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB),
.mp_threshold0 =
- (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
+ (CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB),
.mp_threshold1 =
- (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<
+ (CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<
SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB),
.mp_threshold2 =
- (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
+ (CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB),
- .phy_ctrl0 = CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0,
+ .phy_ctrl0 = CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0,
};
static const struct socfpga_sdram_rw_mgr_config rw_mgr_config = {
@@ -202,7 +202,7 @@
.guaranteed_write_wait3 = RW_MGR_GUARANTEED_WRITE_WAIT3,
.idle_loop1 = RW_MGR_IDLE_LOOP1,
.idle_loop2 = RW_MGR_IDLE_LOOP2,
-#if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 1) /* DDR2 */
+#if (CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 1) /* DDR2 */
.emr = RW_MGR_EMR,
.emr2 = RW_MGR_EMR2,
.emr3 = RW_MGR_EMR3,
@@ -213,7 +213,7 @@
.mr_user = RW_MGR_MR_USER,
.mr_dll_reset = RW_MGR_MR_DLL_RESET,
.emr_ocd_enable = RW_MGR_EMR_OCD_ENABLE,
-#elif (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 2) /* DDR3 */
+#elif (CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 2) /* DDR3 */
.activate_1 = RW_MGR_ACTIVATE_1,
.idle = RW_MGR_IDLE,
.init_reset_0_cke_0 = RW_MGR_INIT_RESET_0_CKE_0,
@@ -287,7 +287,7 @@
};
static const struct socfpga_sdram_misc_config misc_config = {
-#if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 1) /* DDR2 */
+#if (CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 1) /* DDR2 */
.afi_clk_freq = AFI_CLK_FREQ,
#endif
.afi_rate_ratio = AFI_RATE_RATIO,