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Michal Simek6fc7c452011-10-06 20:35:35 +00001/*
2 * Copyright (C) 2011 Michal Simek <monstr@monstr.eu>
3 * Copyright (C) 2011 PetaLogix
4 * Copyright (C) 2010 Xilinx, Inc. All rights reserved.
5 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Michal Simek6fc7c452011-10-06 20:35:35 +00007 */
8
9#include <config.h>
10#include <common.h>
Michal Simek682baac2015-12-08 15:44:41 +010011#include <dm.h>
Michal Simek6fc7c452011-10-06 20:35:35 +000012#include <net.h>
13#include <malloc.h>
14#include <asm/io.h>
15#include <phy.h>
16#include <miiphy.h>
Siva Durga Prasad Paladugu20633622017-01-06 16:18:50 +053017#include <wait_bit.h>
Michal Simek6fc7c452011-10-06 20:35:35 +000018
Michal Simek682baac2015-12-08 15:44:41 +010019DECLARE_GLOBAL_DATA_PTR;
20
Michal Simek6fc7c452011-10-06 20:35:35 +000021/* Link setup */
22#define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */
23#define XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */
24#define XAE_EMMC_LINKSPD_100 0x40000000 /* Link Speed mask for 100 Mbit */
25#define XAE_EMMC_LINKSPD_1000 0x80000000 /* Link Speed mask for 1000 Mbit */
26
27/* Interrupt Status/Enable/Mask Registers bit definitions */
28#define XAE_INT_RXRJECT_MASK 0x00000008 /* Rx frame rejected */
29#define XAE_INT_MGTRDY_MASK 0x00000080 /* MGT clock Lock */
30
31/* Receive Configuration Word 1 (RCW1) Register bit definitions */
32#define XAE_RCW1_RX_MASK 0x10000000 /* Receiver enable */
33
34/* Transmitter Configuration (TC) Register bit definitions */
35#define XAE_TC_TX_MASK 0x10000000 /* Transmitter enable */
36
37#define XAE_UAW1_UNICASTADDR_MASK 0x0000FFFF
38
39/* MDIO Management Configuration (MC) Register bit definitions */
40#define XAE_MDIO_MC_MDIOEN_MASK 0x00000040 /* MII management enable*/
41
42/* MDIO Management Control Register (MCR) Register bit definitions */
43#define XAE_MDIO_MCR_PHYAD_MASK 0x1F000000 /* Phy Address Mask */
44#define XAE_MDIO_MCR_PHYAD_SHIFT 24 /* Phy Address Shift */
45#define XAE_MDIO_MCR_REGAD_MASK 0x001F0000 /* Reg Address Mask */
46#define XAE_MDIO_MCR_REGAD_SHIFT 16 /* Reg Address Shift */
47#define XAE_MDIO_MCR_OP_READ_MASK 0x00008000 /* Op Code Read Mask */
48#define XAE_MDIO_MCR_OP_WRITE_MASK 0x00004000 /* Op Code Write Mask */
49#define XAE_MDIO_MCR_INITIATE_MASK 0x00000800 /* Ready Mask */
50#define XAE_MDIO_MCR_READY_MASK 0x00000080 /* Ready Mask */
51
52#define XAE_MDIO_DIV_DFT 29 /* Default MDIO clock divisor */
53
Siva Durga Prasad Paladuguf8026032017-01-06 16:27:15 +053054#define XAXIDMA_BD_STS_ACTUAL_LEN_MASK 0x007FFFFF /* Actual len */
55
Michal Simek6fc7c452011-10-06 20:35:35 +000056/* DMA macros */
57/* Bitmasks of XAXIDMA_CR_OFFSET register */
58#define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */
59#define XAXIDMA_CR_RESET_MASK 0x00000004 /* Reset DMA engine */
60
61/* Bitmasks of XAXIDMA_SR_OFFSET register */
62#define XAXIDMA_HALTED_MASK 0x00000001 /* DMA channel halted */
63
64/* Bitmask for interrupts */
65#define XAXIDMA_IRQ_IOC_MASK 0x00001000 /* Completion intr */
66#define XAXIDMA_IRQ_DELAY_MASK 0x00002000 /* Delay interrupt */
67#define XAXIDMA_IRQ_ALL_MASK 0x00007000 /* All interrupts */
68
69/* Bitmasks of XAXIDMA_BD_CTRL_OFFSET register */
70#define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */
71#define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */
72
73#define DMAALIGN 128
74
75static u8 rxframe[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN)));
76
77/* Reflect dma offsets */
78struct axidma_reg {
79 u32 control; /* DMACR */
80 u32 status; /* DMASR */
Vipul Kumar3b06a0f2018-01-23 14:52:35 +053081 u32 current; /* CURDESC low 32 bit */
82 u32 current_hi; /* CURDESC high 32 bit */
83 u32 tail; /* TAILDESC low 32 bit */
84 u32 tail_hi; /* TAILDESC high 32 bit */
Michal Simek6fc7c452011-10-06 20:35:35 +000085};
86
87/* Private driver structures */
88struct axidma_priv {
89 struct axidma_reg *dmatx;
90 struct axidma_reg *dmarx;
91 int phyaddr;
Michal Simek6cb55e72015-12-09 14:39:42 +010092 struct axi_regs *iobase;
Michal Simek682baac2015-12-08 15:44:41 +010093 phy_interface_t interface;
Michal Simek6fc7c452011-10-06 20:35:35 +000094 struct phy_device *phydev;
95 struct mii_dev *bus;
Siva Durga Prasad Paladuguf8026032017-01-06 16:27:15 +053096 u8 eth_hasnobuf;
Michal Simek6fc7c452011-10-06 20:35:35 +000097};
98
99/* BD descriptors */
100struct axidma_bd {
101 u32 next; /* Next descriptor pointer */
102 u32 reserved1;
103 u32 phys; /* Buffer address */
104 u32 reserved2;
105 u32 reserved3;
106 u32 reserved4;
107 u32 cntrl; /* Control */
108 u32 status; /* Status */
109 u32 app0;
110 u32 app1; /* TX start << 16 | insert */
111 u32 app2; /* TX csum seed */
112 u32 app3;
113 u32 app4;
114 u32 sw_id_offset;
115 u32 reserved5;
116 u32 reserved6;
117};
118
119/* Static BDs - driver uses only one BD */
120static struct axidma_bd tx_bd __attribute((aligned(DMAALIGN)));
121static struct axidma_bd rx_bd __attribute((aligned(DMAALIGN)));
122
123struct axi_regs {
124 u32 reserved[3];
125 u32 is; /* 0xC: Interrupt status */
126 u32 reserved2;
127 u32 ie; /* 0x14: Interrupt enable */
128 u32 reserved3[251];
129 u32 rcw1; /* 0x404: Rx Configuration Word 1 */
130 u32 tc; /* 0x408: Tx Configuration */
131 u32 reserved4;
132 u32 emmc; /* 0x410: EMAC mode configuration */
133 u32 reserved5[59];
134 u32 mdio_mc; /* 0x500: MII Management Config */
135 u32 mdio_mcr; /* 0x504: MII Management Control */
136 u32 mdio_mwd; /* 0x508: MII Management Write Data */
137 u32 mdio_mrd; /* 0x50C: MII Management Read Data */
138 u32 reserved6[124];
139 u32 uaw0; /* 0x700: Unicast address word 0 */
140 u32 uaw1; /* 0x704: Unicast address word 1 */
141};
142
143/* Use MII register 1 (MII status register) to detect PHY */
144#define PHY_DETECT_REG 1
145
146/*
147 * Mask used to verify certain PHY features (or register contents)
148 * in the register above:
149 * 0x1000: 10Mbps full duplex support
150 * 0x0800: 10Mbps half duplex support
151 * 0x0008: Auto-negotiation support
152 */
153#define PHY_DETECT_MASK 0x1808
154
Michal Simekf5221872015-12-09 14:36:31 +0100155static inline int mdio_wait(struct axi_regs *regs)
Michal Simek6fc7c452011-10-06 20:35:35 +0000156{
Michal Simek6fc7c452011-10-06 20:35:35 +0000157 u32 timeout = 200;
158
159 /* Wait till MDIO interface is ready to accept a new transaction. */
Siva Durga Prasad Paladugud227c9a2017-11-23 12:23:12 +0530160 while (timeout && (!(readl(&regs->mdio_mcr)
Michal Simek6fc7c452011-10-06 20:35:35 +0000161 & XAE_MDIO_MCR_READY_MASK))) {
162 timeout--;
163 udelay(1);
164 }
165 if (!timeout) {
166 printf("%s: Timeout\n", __func__);
167 return 1;
168 }
169 return 0;
170}
171
Vipul Kumar3b06a0f2018-01-23 14:52:35 +0530172/**
173 * axienet_dma_write - Memory mapped Axi DMA register Buffer Descriptor write.
174 * @bd: pointer to BD descriptor structure
175 * @desc: Address offset of DMA descriptors
176 *
177 * This function writes the value into the corresponding Axi DMA register.
178 */
179static inline void axienet_dma_write(struct axidma_bd *bd, u32 *desc)
180{
181#if defined(CONFIG_PHYS_64BIT)
182 writeq(bd, desc);
183#else
184 writel((u32)bd, desc);
185#endif
186}
187
Michal Simek41beca12015-12-09 14:44:38 +0100188static u32 phyread(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
189 u16 *val)
Michal Simek6fc7c452011-10-06 20:35:35 +0000190{
Michal Simek41beca12015-12-09 14:44:38 +0100191 struct axi_regs *regs = priv->iobase;
Michal Simek6fc7c452011-10-06 20:35:35 +0000192 u32 mdioctrlreg = 0;
193
Michal Simekf5221872015-12-09 14:36:31 +0100194 if (mdio_wait(regs))
Michal Simek6fc7c452011-10-06 20:35:35 +0000195 return 1;
196
197 mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
198 XAE_MDIO_MCR_PHYAD_MASK) |
199 ((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
200 & XAE_MDIO_MCR_REGAD_MASK) |
201 XAE_MDIO_MCR_INITIATE_MASK |
202 XAE_MDIO_MCR_OP_READ_MASK;
203
Siva Durga Prasad Paladugud227c9a2017-11-23 12:23:12 +0530204 writel(mdioctrlreg, &regs->mdio_mcr);
Michal Simek6fc7c452011-10-06 20:35:35 +0000205
Michal Simekf5221872015-12-09 14:36:31 +0100206 if (mdio_wait(regs))
Michal Simek6fc7c452011-10-06 20:35:35 +0000207 return 1;
208
209 /* Read data */
Siva Durga Prasad Paladugud227c9a2017-11-23 12:23:12 +0530210 *val = readl(&regs->mdio_mrd);
Michal Simek6fc7c452011-10-06 20:35:35 +0000211 return 0;
212}
213
Michal Simek41beca12015-12-09 14:44:38 +0100214static u32 phywrite(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
215 u32 data)
Michal Simek6fc7c452011-10-06 20:35:35 +0000216{
Michal Simek41beca12015-12-09 14:44:38 +0100217 struct axi_regs *regs = priv->iobase;
Michal Simek6fc7c452011-10-06 20:35:35 +0000218 u32 mdioctrlreg = 0;
219
Michal Simekf5221872015-12-09 14:36:31 +0100220 if (mdio_wait(regs))
Michal Simek6fc7c452011-10-06 20:35:35 +0000221 return 1;
222
223 mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
224 XAE_MDIO_MCR_PHYAD_MASK) |
225 ((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
226 & XAE_MDIO_MCR_REGAD_MASK) |
227 XAE_MDIO_MCR_INITIATE_MASK |
228 XAE_MDIO_MCR_OP_WRITE_MASK;
229
230 /* Write data */
Siva Durga Prasad Paladugud227c9a2017-11-23 12:23:12 +0530231 writel(data, &regs->mdio_mwd);
Michal Simek6fc7c452011-10-06 20:35:35 +0000232
Siva Durga Prasad Paladugud227c9a2017-11-23 12:23:12 +0530233 writel(mdioctrlreg, &regs->mdio_mcr);
Michal Simek6fc7c452011-10-06 20:35:35 +0000234
Michal Simekf5221872015-12-09 14:36:31 +0100235 if (mdio_wait(regs))
Michal Simek6fc7c452011-10-06 20:35:35 +0000236 return 1;
237
238 return 0;
239}
240
Michal Simek0b13ee22015-12-08 16:10:05 +0100241static int axiemac_phy_init(struct udevice *dev)
Michal Simek6fc7c452011-10-06 20:35:35 +0000242{
243 u16 phyreg;
Michal Simek0b13ee22015-12-08 16:10:05 +0100244 u32 i, ret;
Michal Simek682baac2015-12-08 15:44:41 +0100245 struct axidma_priv *priv = dev_get_priv(dev);
Michal Simek6cb55e72015-12-09 14:39:42 +0100246 struct axi_regs *regs = priv->iobase;
Michal Simek6fc7c452011-10-06 20:35:35 +0000247 struct phy_device *phydev;
248
249 u32 supported = SUPPORTED_10baseT_Half |
250 SUPPORTED_10baseT_Full |
251 SUPPORTED_100baseT_Half |
252 SUPPORTED_100baseT_Full |
253 SUPPORTED_1000baseT_Half |
254 SUPPORTED_1000baseT_Full;
255
Michal Simek0b13ee22015-12-08 16:10:05 +0100256 /* Set default MDIO divisor */
Siva Durga Prasad Paladugud227c9a2017-11-23 12:23:12 +0530257 writel(XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK, &regs->mdio_mc);
Michal Simek0b13ee22015-12-08 16:10:05 +0100258
Michal Simek6fc7c452011-10-06 20:35:35 +0000259 if (priv->phyaddr == -1) {
260 /* Detect the PHY address */
261 for (i = 31; i >= 0; i--) {
Michal Simek41beca12015-12-09 14:44:38 +0100262 ret = phyread(priv, i, PHY_DETECT_REG, &phyreg);
Michal Simek6fc7c452011-10-06 20:35:35 +0000263 if (!ret && (phyreg != 0xFFFF) &&
264 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
265 /* Found a valid PHY address */
266 priv->phyaddr = i;
267 debug("axiemac: Found valid phy address, %x\n",
Michal Simek2f1e0652015-12-09 10:54:53 +0100268 i);
Michal Simek6fc7c452011-10-06 20:35:35 +0000269 break;
270 }
271 }
272 }
273
274 /* Interface - look at tsec */
Siva Durga Prasad Paladugu49348512016-02-21 15:46:14 +0530275 phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
Michal Simek6fc7c452011-10-06 20:35:35 +0000276
277 phydev->supported &= supported;
278 phydev->advertising = phydev->supported;
279 priv->phydev = phydev;
280 phy_config(phydev);
Michal Simek0b13ee22015-12-08 16:10:05 +0100281
282 return 0;
283}
284
285/* Setting axi emac and phy to proper setting */
286static int setup_phy(struct udevice *dev)
287{
Siva Durga Prasad Paladugua1c6ed82016-02-21 15:46:15 +0530288 u16 temp;
289 u32 speed, emmc_reg, ret;
Michal Simek0b13ee22015-12-08 16:10:05 +0100290 struct axidma_priv *priv = dev_get_priv(dev);
291 struct axi_regs *regs = priv->iobase;
292 struct phy_device *phydev = priv->phydev;
293
Siva Durga Prasad Paladugua1c6ed82016-02-21 15:46:15 +0530294 if (priv->interface == PHY_INTERFACE_MODE_SGMII) {
295 /*
296 * In SGMII cases the isolate bit might set
297 * after DMA and ethernet resets and hence
298 * check and clear if set.
299 */
300 ret = phyread(priv, priv->phyaddr, MII_BMCR, &temp);
301 if (ret)
302 return 0;
303 if (temp & BMCR_ISOLATE) {
304 temp &= ~BMCR_ISOLATE;
305 ret = phywrite(priv, priv->phyaddr, MII_BMCR, temp);
306 if (ret)
307 return 0;
308 }
309 }
310
Timur Tabi42387462012-07-09 08:52:43 +0000311 if (phy_startup(phydev)) {
312 printf("axiemac: could not initialize PHY %s\n",
313 phydev->dev->name);
314 return 0;
315 }
Michal Simek5848f132013-11-21 16:15:51 +0100316 if (!phydev->link) {
317 printf("%s: No link.\n", phydev->dev->name);
318 return 0;
319 }
Michal Simek6fc7c452011-10-06 20:35:35 +0000320
321 switch (phydev->speed) {
322 case 1000:
323 speed = XAE_EMMC_LINKSPD_1000;
324 break;
325 case 100:
326 speed = XAE_EMMC_LINKSPD_100;
327 break;
328 case 10:
329 speed = XAE_EMMC_LINKSPD_10;
330 break;
331 default:
332 return 0;
333 }
334
335 /* Setup the emac for the phy speed */
Siva Durga Prasad Paladugud227c9a2017-11-23 12:23:12 +0530336 emmc_reg = readl(&regs->emmc);
Michal Simek6fc7c452011-10-06 20:35:35 +0000337 emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK;
338 emmc_reg |= speed;
339
340 /* Write new speed setting out to Axi Ethernet */
Siva Durga Prasad Paladugud227c9a2017-11-23 12:23:12 +0530341 writel(emmc_reg, &regs->emmc);
Michal Simek6fc7c452011-10-06 20:35:35 +0000342
343 /*
344 * Setting the operating speed of the MAC needs a delay. There
345 * doesn't seem to be register to poll, so please consider this
346 * during your application design.
347 */
348 udelay(1);
349
350 return 1;
351}
352
353/* STOP DMA transfers */
Michal Simek8fbf79f2015-12-16 09:18:12 +0100354static void axiemac_stop(struct udevice *dev)
Michal Simek6fc7c452011-10-06 20:35:35 +0000355{
Michal Simek682baac2015-12-08 15:44:41 +0100356 struct axidma_priv *priv = dev_get_priv(dev);
Michal Simek6fc7c452011-10-06 20:35:35 +0000357 u32 temp;
358
359 /* Stop the hardware */
Siva Durga Prasad Paladugud227c9a2017-11-23 12:23:12 +0530360 temp = readl(&priv->dmatx->control);
Michal Simek6fc7c452011-10-06 20:35:35 +0000361 temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
Siva Durga Prasad Paladugud227c9a2017-11-23 12:23:12 +0530362 writel(temp, &priv->dmatx->control);
Michal Simek6fc7c452011-10-06 20:35:35 +0000363
Siva Durga Prasad Paladugud227c9a2017-11-23 12:23:12 +0530364 temp = readl(&priv->dmarx->control);
Michal Simek6fc7c452011-10-06 20:35:35 +0000365 temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
Siva Durga Prasad Paladugud227c9a2017-11-23 12:23:12 +0530366 writel(temp, &priv->dmarx->control);
Michal Simek6fc7c452011-10-06 20:35:35 +0000367
368 debug("axiemac: Halted\n");
369}
370
Michal Simek638c0ef2015-12-09 14:53:51 +0100371static int axi_ethernet_init(struct axidma_priv *priv)
Michal Simek6fc7c452011-10-06 20:35:35 +0000372{
Michal Simek638c0ef2015-12-09 14:53:51 +0100373 struct axi_regs *regs = priv->iobase;
Siva Durga Prasad Paladugu20633622017-01-06 16:18:50 +0530374 int err;
Michal Simek6fc7c452011-10-06 20:35:35 +0000375
376 /*
377 * Check the status of the MgtRdy bit in the interrupt status
378 * registers. This must be done to allow the MGT clock to become stable
379 * for the Sgmii and 1000BaseX PHY interfaces. No other register reads
380 * will be valid until this bit is valid.
381 * The bit is always a 1 for all other PHY interfaces.
Siva Durga Prasad Paladuguf8026032017-01-06 16:27:15 +0530382 * Interrupt status and enable registers are not available in non
383 * processor mode and hence bypass in this mode
Michal Simek6fc7c452011-10-06 20:35:35 +0000384 */
Siva Durga Prasad Paladuguf8026032017-01-06 16:27:15 +0530385 if (!priv->eth_hasnobuf) {
Álvaro Fernández Rojas918de032018-01-23 17:14:55 +0100386 err = wait_for_bit_le32(&regs->is, XAE_INT_MGTRDY_MASK,
387 true, 200, false);
Siva Durga Prasad Paladuguf8026032017-01-06 16:27:15 +0530388 if (err) {
389 printf("%s: Timeout\n", __func__);
390 return 1;
391 }
Michal Simek6fc7c452011-10-06 20:35:35 +0000392
Siva Durga Prasad Paladuguf8026032017-01-06 16:27:15 +0530393 /*
394 * Stop the device and reset HW
395 * Disable interrupts
396 */
Siva Durga Prasad Paladugud227c9a2017-11-23 12:23:12 +0530397 writel(0, &regs->ie);
Siva Durga Prasad Paladuguf8026032017-01-06 16:27:15 +0530398 }
Michal Simek6fc7c452011-10-06 20:35:35 +0000399
400 /* Disable the receiver */
Siva Durga Prasad Paladugud227c9a2017-11-23 12:23:12 +0530401 writel(readl(&regs->rcw1) & ~XAE_RCW1_RX_MASK, &regs->rcw1);
Michal Simek6fc7c452011-10-06 20:35:35 +0000402
403 /*
404 * Stopping the receiver in mid-packet causes a dropped packet
405 * indication from HW. Clear it.
406 */
Siva Durga Prasad Paladuguf8026032017-01-06 16:27:15 +0530407 if (!priv->eth_hasnobuf) {
408 /* Set the interrupt status register to clear the interrupt */
Siva Durga Prasad Paladugud227c9a2017-11-23 12:23:12 +0530409 writel(XAE_INT_RXRJECT_MASK, &regs->is);
Siva Durga Prasad Paladuguf8026032017-01-06 16:27:15 +0530410 }
Michal Simek6fc7c452011-10-06 20:35:35 +0000411
412 /* Setup HW */
413 /* Set default MDIO divisor */
Siva Durga Prasad Paladugud227c9a2017-11-23 12:23:12 +0530414 writel(XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK, &regs->mdio_mc);
Michal Simek6fc7c452011-10-06 20:35:35 +0000415
416 debug("axiemac: InitHw done\n");
417 return 0;
418}
419
Michal Simek8fbf79f2015-12-16 09:18:12 +0100420static int axiemac_write_hwaddr(struct udevice *dev)
Michal Simek6fc7c452011-10-06 20:35:35 +0000421{
Michal Simek682baac2015-12-08 15:44:41 +0100422 struct eth_pdata *pdata = dev_get_platdata(dev);
423 struct axidma_priv *priv = dev_get_priv(dev);
424 struct axi_regs *regs = priv->iobase;
Michal Simek6fc7c452011-10-06 20:35:35 +0000425
426 /* Set the MAC address */
Michal Simek682baac2015-12-08 15:44:41 +0100427 int val = ((pdata->enetaddr[3] << 24) | (pdata->enetaddr[2] << 16) |
428 (pdata->enetaddr[1] << 8) | (pdata->enetaddr[0]));
Siva Durga Prasad Paladugud227c9a2017-11-23 12:23:12 +0530429 writel(val, &regs->uaw0);
Michal Simek6fc7c452011-10-06 20:35:35 +0000430
Michal Simek682baac2015-12-08 15:44:41 +0100431 val = (pdata->enetaddr[5] << 8) | pdata->enetaddr[4];
Siva Durga Prasad Paladugud227c9a2017-11-23 12:23:12 +0530432 val |= readl(&regs->uaw1) & ~XAE_UAW1_UNICASTADDR_MASK;
433 writel(val, &regs->uaw1);
Michal Simek6fc7c452011-10-06 20:35:35 +0000434 return 0;
435}
436
437/* Reset DMA engine */
Michal Simek638c0ef2015-12-09 14:53:51 +0100438static void axi_dma_init(struct axidma_priv *priv)
Michal Simek6fc7c452011-10-06 20:35:35 +0000439{
Michal Simek6fc7c452011-10-06 20:35:35 +0000440 u32 timeout = 500;
441
442 /* Reset the engine so the hardware starts from a known state */
Siva Durga Prasad Paladugud227c9a2017-11-23 12:23:12 +0530443 writel(XAXIDMA_CR_RESET_MASK, &priv->dmatx->control);
444 writel(XAXIDMA_CR_RESET_MASK, &priv->dmarx->control);
Michal Simek6fc7c452011-10-06 20:35:35 +0000445
446 /* At the initialization time, hardware should finish reset quickly */
447 while (timeout--) {
448 /* Check transmit/receive channel */
449 /* Reset is done when the reset bit is low */
Siva Durga Prasad Paladugud227c9a2017-11-23 12:23:12 +0530450 if (!((readl(&priv->dmatx->control) |
451 readl(&priv->dmarx->control))
Michal Simek5aa45392015-10-28 11:00:47 +0100452 & XAXIDMA_CR_RESET_MASK)) {
Michal Simek6fc7c452011-10-06 20:35:35 +0000453 break;
454 }
455 }
456 if (!timeout)
457 printf("%s: Timeout\n", __func__);
458}
459
Michal Simek8fbf79f2015-12-16 09:18:12 +0100460static int axiemac_start(struct udevice *dev)
Michal Simek6fc7c452011-10-06 20:35:35 +0000461{
Michal Simek682baac2015-12-08 15:44:41 +0100462 struct axidma_priv *priv = dev_get_priv(dev);
463 struct axi_regs *regs = priv->iobase;
Michal Simek6fc7c452011-10-06 20:35:35 +0000464 u32 temp;
465
466 debug("axiemac: Init started\n");
467 /*
468 * Initialize AXIDMA engine. AXIDMA engine must be initialized before
469 * AxiEthernet. During AXIDMA engine initialization, AXIDMA hardware is
470 * reset, and since AXIDMA reset line is connected to AxiEthernet, this
471 * would ensure a reset of AxiEthernet.
472 */
Michal Simek638c0ef2015-12-09 14:53:51 +0100473 axi_dma_init(priv);
Michal Simek6fc7c452011-10-06 20:35:35 +0000474
475 /* Initialize AxiEthernet hardware. */
Michal Simek638c0ef2015-12-09 14:53:51 +0100476 if (axi_ethernet_init(priv))
Michal Simek6fc7c452011-10-06 20:35:35 +0000477 return -1;
478
479 /* Disable all RX interrupts before RxBD space setup */
Siva Durga Prasad Paladugud227c9a2017-11-23 12:23:12 +0530480 temp = readl(&priv->dmarx->control);
Michal Simek6fc7c452011-10-06 20:35:35 +0000481 temp &= ~XAXIDMA_IRQ_ALL_MASK;
Siva Durga Prasad Paladugud227c9a2017-11-23 12:23:12 +0530482 writel(temp, &priv->dmarx->control);
Michal Simek6fc7c452011-10-06 20:35:35 +0000483
484 /* Start DMA RX channel. Now it's ready to receive data.*/
Vipul Kumar3b06a0f2018-01-23 14:52:35 +0530485 axienet_dma_write(&rx_bd, &priv->dmarx->current);
Michal Simek6fc7c452011-10-06 20:35:35 +0000486
487 /* Setup the BD. */
488 memset(&rx_bd, 0, sizeof(rx_bd));
489 rx_bd.next = (u32)&rx_bd;
490 rx_bd.phys = (u32)&rxframe;
491 rx_bd.cntrl = sizeof(rxframe);
492 /* Flush the last BD so DMA core could see the updates */
493 flush_cache((u32)&rx_bd, sizeof(rx_bd));
494
495 /* It is necessary to flush rxframe because if you don't do it
496 * then cache can contain uninitialized data */
497 flush_cache((u32)&rxframe, sizeof(rxframe));
498
499 /* Start the hardware */
Siva Durga Prasad Paladugud227c9a2017-11-23 12:23:12 +0530500 temp = readl(&priv->dmarx->control);
Michal Simek6fc7c452011-10-06 20:35:35 +0000501 temp |= XAXIDMA_CR_RUNSTOP_MASK;
Siva Durga Prasad Paladugud227c9a2017-11-23 12:23:12 +0530502 writel(temp, &priv->dmarx->control);
Michal Simek6fc7c452011-10-06 20:35:35 +0000503
504 /* Rx BD is ready - start */
Vipul Kumar3b06a0f2018-01-23 14:52:35 +0530505 axienet_dma_write(&rx_bd, &priv->dmarx->tail);
Michal Simek6fc7c452011-10-06 20:35:35 +0000506
507 /* Enable TX */
Siva Durga Prasad Paladugud227c9a2017-11-23 12:23:12 +0530508 writel(XAE_TC_TX_MASK, &regs->tc);
Michal Simek6fc7c452011-10-06 20:35:35 +0000509 /* Enable RX */
Siva Durga Prasad Paladugud227c9a2017-11-23 12:23:12 +0530510 writel(XAE_RCW1_RX_MASK, &regs->rcw1);
Michal Simek6fc7c452011-10-06 20:35:35 +0000511
512 /* PHY setup */
513 if (!setup_phy(dev)) {
Michal Simek8fbf79f2015-12-16 09:18:12 +0100514 axiemac_stop(dev);
Michal Simek6fc7c452011-10-06 20:35:35 +0000515 return -1;
516 }
517
518 debug("axiemac: Init complete\n");
519 return 0;
520}
521
Michal Simek682baac2015-12-08 15:44:41 +0100522static int axiemac_send(struct udevice *dev, void *ptr, int len)
Michal Simek6fc7c452011-10-06 20:35:35 +0000523{
Michal Simek682baac2015-12-08 15:44:41 +0100524 struct axidma_priv *priv = dev_get_priv(dev);
Michal Simek6fc7c452011-10-06 20:35:35 +0000525 u32 timeout;
526
527 if (len > PKTSIZE_ALIGN)
528 len = PKTSIZE_ALIGN;
529
530 /* Flush packet to main memory to be trasfered by DMA */
531 flush_cache((u32)ptr, len);
532
533 /* Setup Tx BD */
534 memset(&tx_bd, 0, sizeof(tx_bd));
535 /* At the end of the ring, link the last BD back to the top */
536 tx_bd.next = (u32)&tx_bd;
537 tx_bd.phys = (u32)ptr;
538 /* Save len */
539 tx_bd.cntrl = len | XAXIDMA_BD_CTRL_TXSOF_MASK |
540 XAXIDMA_BD_CTRL_TXEOF_MASK;
541
542 /* Flush the last BD so DMA core could see the updates */
543 flush_cache((u32)&tx_bd, sizeof(tx_bd));
544
Siva Durga Prasad Paladugud227c9a2017-11-23 12:23:12 +0530545 if (readl(&priv->dmatx->status) & XAXIDMA_HALTED_MASK) {
Michal Simek6fc7c452011-10-06 20:35:35 +0000546 u32 temp;
Vipul Kumar3b06a0f2018-01-23 14:52:35 +0530547 axienet_dma_write(&tx_bd, &priv->dmatx->current);
Michal Simek6fc7c452011-10-06 20:35:35 +0000548 /* Start the hardware */
Siva Durga Prasad Paladugud227c9a2017-11-23 12:23:12 +0530549 temp = readl(&priv->dmatx->control);
Michal Simek6fc7c452011-10-06 20:35:35 +0000550 temp |= XAXIDMA_CR_RUNSTOP_MASK;
Siva Durga Prasad Paladugud227c9a2017-11-23 12:23:12 +0530551 writel(temp, &priv->dmatx->control);
Michal Simek6fc7c452011-10-06 20:35:35 +0000552 }
553
554 /* Start transfer */
Vipul Kumar3b06a0f2018-01-23 14:52:35 +0530555 axienet_dma_write(&tx_bd, &priv->dmatx->tail);
Michal Simek6fc7c452011-10-06 20:35:35 +0000556
557 /* Wait for transmission to complete */
558 debug("axiemac: Waiting for tx to be done\n");
559 timeout = 200;
Siva Durga Prasad Paladugud227c9a2017-11-23 12:23:12 +0530560 while (timeout && (!(readl(&priv->dmatx->status) &
Michal Simek5aa45392015-10-28 11:00:47 +0100561 (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))) {
Michal Simek6fc7c452011-10-06 20:35:35 +0000562 timeout--;
563 udelay(1);
564 }
565 if (!timeout) {
566 printf("%s: Timeout\n", __func__);
567 return 1;
568 }
569
570 debug("axiemac: Sending complete\n");
571 return 0;
572}
573
Michal Simek638c0ef2015-12-09 14:53:51 +0100574static int isrxready(struct axidma_priv *priv)
Michal Simek6fc7c452011-10-06 20:35:35 +0000575{
576 u32 status;
Michal Simek6fc7c452011-10-06 20:35:35 +0000577
578 /* Read pending interrupts */
Siva Durga Prasad Paladugud227c9a2017-11-23 12:23:12 +0530579 status = readl(&priv->dmarx->status);
Michal Simek6fc7c452011-10-06 20:35:35 +0000580
581 /* Acknowledge pending interrupts */
Siva Durga Prasad Paladugud227c9a2017-11-23 12:23:12 +0530582 writel(status & XAXIDMA_IRQ_ALL_MASK, &priv->dmarx->status);
Michal Simek6fc7c452011-10-06 20:35:35 +0000583
584 /*
585 * If Reception done interrupt is asserted, call RX call back function
586 * to handle the processed BDs and then raise the according flag.
587 */
588 if ((status & (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))
589 return 1;
590
591 return 0;
592}
593
Michal Simek682baac2015-12-08 15:44:41 +0100594static int axiemac_recv(struct udevice *dev, int flags, uchar **packetp)
Michal Simek6fc7c452011-10-06 20:35:35 +0000595{
596 u32 length;
Michal Simek682baac2015-12-08 15:44:41 +0100597 struct axidma_priv *priv = dev_get_priv(dev);
Michal Simek6fc7c452011-10-06 20:35:35 +0000598 u32 temp;
599
600 /* Wait for an incoming packet */
Michal Simek638c0ef2015-12-09 14:53:51 +0100601 if (!isrxready(priv))
Michal Simek682baac2015-12-08 15:44:41 +0100602 return -1;
Michal Simek6fc7c452011-10-06 20:35:35 +0000603
604 debug("axiemac: RX data ready\n");
605
606 /* Disable IRQ for a moment till packet is handled */
Siva Durga Prasad Paladugud227c9a2017-11-23 12:23:12 +0530607 temp = readl(&priv->dmarx->control);
Michal Simek6fc7c452011-10-06 20:35:35 +0000608 temp &= ~XAXIDMA_IRQ_ALL_MASK;
Siva Durga Prasad Paladugud227c9a2017-11-23 12:23:12 +0530609 writel(temp, &priv->dmarx->control);
Siva Durga Prasad Paladuguf8026032017-01-06 16:27:15 +0530610 if (!priv->eth_hasnobuf)
611 length = rx_bd.app4 & 0xFFFF; /* max length mask */
612 else
613 length = rx_bd.status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK;
Michal Simek6fc7c452011-10-06 20:35:35 +0000614
Michal Simek6fc7c452011-10-06 20:35:35 +0000615#ifdef DEBUG
616 print_buffer(&rxframe, &rxframe[0], 1, length, 16);
617#endif
Michal Simek0305be82015-12-09 14:13:23 +0100618
619 *packetp = rxframe;
620 return length;
621}
622
623static int axiemac_free_pkt(struct udevice *dev, uchar *packet, int length)
624{
625 struct axidma_priv *priv = dev_get_priv(dev);
Michal Simek6fc7c452011-10-06 20:35:35 +0000626
627#ifdef DEBUG
628 /* It is useful to clear buffer to be sure that it is consistent */
629 memset(rxframe, 0, sizeof(rxframe));
630#endif
631 /* Setup RxBD */
632 /* Clear the whole buffer and setup it again - all flags are cleared */
633 memset(&rx_bd, 0, sizeof(rx_bd));
634 rx_bd.next = (u32)&rx_bd;
635 rx_bd.phys = (u32)&rxframe;
636 rx_bd.cntrl = sizeof(rxframe);
637
638 /* Write bd to HW */
639 flush_cache((u32)&rx_bd, sizeof(rx_bd));
640
641 /* It is necessary to flush rxframe because if you don't do it
642 * then cache will contain previous packet */
643 flush_cache((u32)&rxframe, sizeof(rxframe));
644
645 /* Rx BD is ready - start again */
Vipul Kumar3b06a0f2018-01-23 14:52:35 +0530646 axienet_dma_write(&rx_bd, &priv->dmarx->tail);
Michal Simek6fc7c452011-10-06 20:35:35 +0000647
648 debug("axiemac: RX completed, framelength = %d\n", length);
649
Michal Simek682baac2015-12-08 15:44:41 +0100650 return 0;
Michal Simek6fc7c452011-10-06 20:35:35 +0000651}
652
Michal Simek682baac2015-12-08 15:44:41 +0100653static int axiemac_miiphy_read(struct mii_dev *bus, int addr,
654 int devad, int reg)
Michal Simek6fc7c452011-10-06 20:35:35 +0000655{
Michal Simek682baac2015-12-08 15:44:41 +0100656 int ret;
657 u16 value;
Michal Simek6fc7c452011-10-06 20:35:35 +0000658
Michal Simek682baac2015-12-08 15:44:41 +0100659 ret = phyread(bus->priv, addr, reg, &value);
660 debug("axiemac: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg,
661 value, ret);
662 return value;
Michal Simek6fc7c452011-10-06 20:35:35 +0000663}
664
Michal Simek682baac2015-12-08 15:44:41 +0100665static int axiemac_miiphy_write(struct mii_dev *bus, int addr, int devad,
666 int reg, u16 value)
Michal Simek6fc7c452011-10-06 20:35:35 +0000667{
Michal Simek682baac2015-12-08 15:44:41 +0100668 debug("axiemac: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value);
669 return phywrite(bus->priv, addr, reg, value);
Michal Simek6fc7c452011-10-06 20:35:35 +0000670}
671
Michal Simek682baac2015-12-08 15:44:41 +0100672static int axi_emac_probe(struct udevice *dev)
Michal Simek6fc7c452011-10-06 20:35:35 +0000673{
Michal Simek682baac2015-12-08 15:44:41 +0100674 struct axidma_priv *priv = dev_get_priv(dev);
675 int ret;
676
677 priv->bus = mdio_alloc();
678 priv->bus->read = axiemac_miiphy_read;
679 priv->bus->write = axiemac_miiphy_write;
680 priv->bus->priv = priv;
Michal Simek682baac2015-12-08 15:44:41 +0100681
Michal Simeke4dab432016-12-08 10:25:44 +0100682 ret = mdio_register_seq(priv->bus, dev->seq);
Michal Simek682baac2015-12-08 15:44:41 +0100683 if (ret)
684 return ret;
685
Michal Simek0b13ee22015-12-08 16:10:05 +0100686 axiemac_phy_init(dev);
687
Michal Simek6fc7c452011-10-06 20:35:35 +0000688 return 0;
689}
690
Michal Simek682baac2015-12-08 15:44:41 +0100691static int axi_emac_remove(struct udevice *dev)
Michal Simek6fc7c452011-10-06 20:35:35 +0000692{
Michal Simek682baac2015-12-08 15:44:41 +0100693 struct axidma_priv *priv = dev_get_priv(dev);
Michal Simek6fc7c452011-10-06 20:35:35 +0000694
Michal Simek682baac2015-12-08 15:44:41 +0100695 free(priv->phydev);
696 mdio_unregister(priv->bus);
697 mdio_free(priv->bus);
Michal Simek6fc7c452011-10-06 20:35:35 +0000698
Michal Simek682baac2015-12-08 15:44:41 +0100699 return 0;
700}
701
702static const struct eth_ops axi_emac_ops = {
Michal Simek8fbf79f2015-12-16 09:18:12 +0100703 .start = axiemac_start,
Michal Simek682baac2015-12-08 15:44:41 +0100704 .send = axiemac_send,
705 .recv = axiemac_recv,
Michal Simek0305be82015-12-09 14:13:23 +0100706 .free_pkt = axiemac_free_pkt,
Michal Simek8fbf79f2015-12-16 09:18:12 +0100707 .stop = axiemac_stop,
708 .write_hwaddr = axiemac_write_hwaddr,
Michal Simek682baac2015-12-08 15:44:41 +0100709};
710
711static int axi_emac_ofdata_to_platdata(struct udevice *dev)
712{
713 struct eth_pdata *pdata = dev_get_platdata(dev);
714 struct axidma_priv *priv = dev_get_priv(dev);
Simon Glassdd79d6e2017-01-17 16:52:55 -0700715 int node = dev_of_offset(dev);
Michal Simek682baac2015-12-08 15:44:41 +0100716 int offset = 0;
717 const char *phy_mode;
Michal Simek6fc7c452011-10-06 20:35:35 +0000718
Simon Glassba1dea42017-05-17 17:18:05 -0600719 pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
Michal Simek682baac2015-12-08 15:44:41 +0100720 priv->iobase = (struct axi_regs *)pdata->iobase;
Michal Simek6fc7c452011-10-06 20:35:35 +0000721
Simon Glassdd79d6e2017-01-17 16:52:55 -0700722 offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
Michal Simek682baac2015-12-08 15:44:41 +0100723 "axistream-connected");
724 if (offset <= 0) {
725 printf("%s: axistream is not found\n", __func__);
726 return -EINVAL;
727 }
Siva Durga Prasad Paladugu6372e3f2017-06-22 11:14:55 +0530728 priv->dmatx = (struct axidma_reg *)fdtdec_get_addr(gd->fdt_blob,
729 offset, "reg");
Michal Simek682baac2015-12-08 15:44:41 +0100730 if (!priv->dmatx) {
731 printf("%s: axi_dma register space not found\n", __func__);
732 return -EINVAL;
733 }
Michal Simek6fc7c452011-10-06 20:35:35 +0000734 /* RX channel offset is 0x30 */
Michal Simek682baac2015-12-08 15:44:41 +0100735 priv->dmarx = (struct axidma_reg *)((u32)priv->dmatx + 0x30);
Michal Simek6fc7c452011-10-06 20:35:35 +0000736
Michal Simek6fc7c452011-10-06 20:35:35 +0000737 priv->phyaddr = -1;
Michal Simek6fc7c452011-10-06 20:35:35 +0000738
Simon Glassdd79d6e2017-01-17 16:52:55 -0700739 offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle");
Michal Simek682baac2015-12-08 15:44:41 +0100740 if (offset > 0)
741 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
Michal Simek6fc7c452011-10-06 20:35:35 +0000742
Simon Glassdd79d6e2017-01-17 16:52:55 -0700743 phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
Michal Simek682baac2015-12-08 15:44:41 +0100744 if (phy_mode)
745 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
746 if (pdata->phy_interface == -1) {
Michal Simek9dbfc0d2016-02-08 13:54:05 +0100747 printf("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
Michal Simek682baac2015-12-08 15:44:41 +0100748 return -EINVAL;
749 }
750 priv->interface = pdata->phy_interface;
751
Siva Durga Prasad Paladuguf8026032017-01-06 16:27:15 +0530752 priv->eth_hasnobuf = fdtdec_get_bool(gd->fdt_blob, node,
753 "xlnx,eth-hasnobuf");
754
Michal Simek682baac2015-12-08 15:44:41 +0100755 printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase,
756 priv->phyaddr, phy_string_for_interface(priv->interface));
757
758 return 0;
Michal Simek6fc7c452011-10-06 20:35:35 +0000759}
Michal Simek682baac2015-12-08 15:44:41 +0100760
761static const struct udevice_id axi_emac_ids[] = {
762 { .compatible = "xlnx,axi-ethernet-1.00.a" },
763 { }
764};
765
766U_BOOT_DRIVER(axi_emac) = {
767 .name = "axi_emac",
768 .id = UCLASS_ETH,
769 .of_match = axi_emac_ids,
770 .ofdata_to_platdata = axi_emac_ofdata_to_platdata,
771 .probe = axi_emac_probe,
772 .remove = axi_emac_remove,
773 .ops = &axi_emac_ops,
774 .priv_auto_alloc_size = sizeof(struct axidma_priv),
775 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
776};