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Scott Woodf64c98c2015-03-20 19:28:12 -07001/*
Mingkai Hu0e58b512015-10-26 19:47:50 +08002 * Copyright 2014-2015 Freescale Semiconductor
Scott Woodf64c98c2015-03-20 19:28:12 -07003 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <fsl_ifc.h>
Tang Yuantian57894be2015-12-09 15:32:18 +08009#include <ahci.h>
10#include <scsi.h>
Hou Zhiqiang4b23ca82016-08-02 19:03:27 +080011#include <asm/arch/fsl_serdes.h>
Mingkai Hu0e58b512015-10-26 19:47:50 +080012#include <asm/arch/soc.h>
Scott Woodae1df322015-03-20 19:28:13 -070013#include <asm/io.h>
Scott Wood8e728cd2015-03-24 13:25:02 -070014#include <asm/global_data.h>
Prabhakar Kushwaha22cfe962015-11-05 12:00:14 +053015#include <asm/arch-fsl-layerscape/config.h>
Hou Zhiqiang4b23ca82016-08-02 19:03:27 +080016#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
Hou Zhiqiang5ac9a5c2016-08-02 19:03:23 +080017#include <fsl_csu.h>
Hou Zhiqiang4b23ca82016-08-02 19:03:27 +080018#endif
Prabhakar Kushwahad169ebe2016-06-03 18:41:31 +053019#ifdef CONFIG_SYS_FSL_DDR
Shengzhou Liuddf060b2016-04-07 16:22:21 +080020#include <fsl_ddr_sdram.h>
21#include <fsl_ddr.h>
Prabhakar Kushwahad169ebe2016-06-03 18:41:31 +053022#endif
Aneesh Bansal39d5b3b2016-01-22 16:37:26 +053023#ifdef CONFIG_CHAIN_OF_TRUST
24#include <fsl_validate.h>
25#endif
Scott Wood8e728cd2015-03-24 13:25:02 -070026
27DECLARE_GLOBAL_DATA_PTR;
Scott Woodae1df322015-03-20 19:28:13 -070028
York Suncbe8e1c2016-04-04 11:41:26 -070029bool soc_has_dp_ddr(void)
30{
31 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
32 u32 svr = gur_in32(&gur->svr);
33
Priyanka Jain4a6f1732016-11-17 12:29:55 +053034 /* LS2085A, LS2088A, LS2048A has DP_DDR */
35 if ((SVR_SOC_VER(svr) == SVR_LS2085A) ||
36 (SVR_SOC_VER(svr) == SVR_LS2088A) ||
37 (SVR_SOC_VER(svr) == SVR_LS2048A))
York Suncbe8e1c2016-04-04 11:41:26 -070038 return true;
39
40 return false;
41}
42
43bool soc_has_aiop(void)
44{
45 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
46 u32 svr = gur_in32(&gur->svr);
47
48 /* LS2085A has AIOP */
Prabhakar Kushwahaac7f2422016-06-24 13:48:13 +053049 if (SVR_SOC_VER(svr) == SVR_LS2085A)
York Suncbe8e1c2016-04-04 11:41:26 -070050 return true;
51
52 return false;
53}
54
Shengzhou Liua3117ee2016-11-11 18:11:05 +080055#if defined(CONFIG_FSL_LSCH3)
Yao Yuanfae88052015-12-05 14:59:14 +080056/*
57 * This erratum requires setting a value to eddrtqcr1 to
58 * optimal the DDR performance.
59 */
60static void erratum_a008336(void)
61{
Shengzhou Liua3117ee2016-11-11 18:11:05 +080062#ifdef CONFIG_SYS_FSL_ERRATUM_A008336
Yao Yuanfae88052015-12-05 14:59:14 +080063 u32 *eddrtqcr1;
64
Yao Yuanfae88052015-12-05 14:59:14 +080065#ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
66 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
Shengzhou Liu7beb0c42016-08-26 18:30:38 +080067 if (fsl_ddr_get_version(0) == 0x50200)
68 out_le32(eddrtqcr1, 0x63b30002);
Yao Yuanfae88052015-12-05 14:59:14 +080069#endif
70#ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
71 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
Shengzhou Liu7beb0c42016-08-26 18:30:38 +080072 if (fsl_ddr_get_version(0) == 0x50200)
73 out_le32(eddrtqcr1, 0x63b30002);
Yao Yuanfae88052015-12-05 14:59:14 +080074#endif
75#endif
76}
77
78/*
79 * This erratum requires a register write before being Memory
80 * controller 3 being enabled.
81 */
82static void erratum_a008514(void)
83{
Shengzhou Liua3117ee2016-11-11 18:11:05 +080084#ifdef CONFIG_SYS_FSL_ERRATUM_A008514
Yao Yuanfae88052015-12-05 14:59:14 +080085 u32 *eddrtqcr1;
86
Yao Yuanfae88052015-12-05 14:59:14 +080087#ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR
88 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
89 out_le32(eddrtqcr1, 0x63b20002);
90#endif
91#endif
92}
Prabhakar Kushwaha22cfe962015-11-05 12:00:14 +053093#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
94#define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val"
95
96static unsigned long get_internval_val_mhz(void)
97{
98 char *interval = getenv(PLATFORM_CYCLE_ENV_VAR);
99 /*
100 * interval is the number of platform cycles(MHz) between
101 * wake up events generated by EPU.
102 */
103 ulong interval_mhz = get_bus_freq(0) / (1000 * 1000);
104
105 if (interval)
106 interval_mhz = simple_strtoul(interval, NULL, 10);
107
108 return interval_mhz;
109}
110
111void erratum_a009635(void)
112{
113 u32 val;
114 unsigned long interval_mhz = get_internval_val_mhz();
115
116 if (!interval_mhz)
117 return;
118
119 val = in_le32(DCSR_CGACRE5);
120 writel(val | 0x00000200, DCSR_CGACRE5);
121
122 val = in_le32(EPU_EPCMPR5);
123 writel(interval_mhz, EPU_EPCMPR5);
124 val = in_le32(EPU_EPCCR5);
125 writel(val | 0x82820000, EPU_EPCCR5);
126 val = in_le32(EPU_EPSMCR5);
127 writel(val | 0x002f0000, EPU_EPSMCR5);
128 val = in_le32(EPU_EPECR5);
129 writel(val | 0x20000000, EPU_EPECR5);
130 val = in_le32(EPU_EPGCR);
131 writel(val | 0x80000000, EPU_EPGCR);
132}
133#endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */
134
Scott Wood8e728cd2015-03-24 13:25:02 -0700135static void erratum_rcw_src(void)
136{
137#if defined(CONFIG_SPL)
138 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
139 u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
140 u32 val;
141
142 val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
143 val &= ~DCFG_PORSR1_RCW_SRC;
144 val |= DCFG_PORSR1_RCW_SRC_NOR;
145 out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
146#endif
147}
148
York Sun0404a392015-03-23 10:41:35 -0700149#define I2C_DEBUG_REG 0x6
150#define I2C_GLITCH_EN 0x8
151/*
152 * This erratum requires setting glitch_en bit to enable
153 * digital glitch filter to improve clock stability.
154 */
155static void erratum_a009203(void)
156{
157 u8 __iomem *ptr;
158#ifdef CONFIG_SYS_I2C
159#ifdef I2C1_BASE_ADDR
160 ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
161
162 writeb(I2C_GLITCH_EN, ptr);
163#endif
164#ifdef I2C2_BASE_ADDR
165 ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG);
166
167 writeb(I2C_GLITCH_EN, ptr);
168#endif
169#ifdef I2C3_BASE_ADDR
170 ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG);
171
172 writeb(I2C_GLITCH_EN, ptr);
173#endif
174#ifdef I2C4_BASE_ADDR
175 ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG);
176
177 writeb(I2C_GLITCH_EN, ptr);
178#endif
179#endif
180}
Shengzhou Liua3117ee2016-11-11 18:11:05 +0800181
Saksham Jain5d8ffe12016-03-23 16:24:40 +0530182void bypass_smmu(void)
183{
184 u32 val;
185 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
186 out_le32(SMMU_SCR0, val);
187 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
188 out_le32(SMMU_NSCR0, val);
189}
Scott Woodf64c98c2015-03-20 19:28:12 -0700190void fsl_lsch3_early_init_f(void)
191{
Scott Wood8e728cd2015-03-24 13:25:02 -0700192 erratum_rcw_src();
Scott Woodf64c98c2015-03-20 19:28:12 -0700193 init_early_memctl_regs(); /* tighten IFC timing */
York Sun0404a392015-03-23 10:41:35 -0700194 erratum_a009203();
Yao Yuanfae88052015-12-05 14:59:14 +0800195 erratum_a008514();
196 erratum_a008336();
Saksham Jain5d8ffe12016-03-23 16:24:40 +0530197#ifdef CONFIG_CHAIN_OF_TRUST
198 /* In case of Secure Boot, the IBR configures the SMMU
199 * to allow only Secure transactions.
200 * SMMU must be reset in bypass mode.
201 * Set the ClientPD bit and Clear the USFCFG Bit
202 */
203 if (fsl_check_boot_mode_secure() == 1)
204 bypass_smmu();
205#endif
Scott Woodf64c98c2015-03-20 19:28:12 -0700206}
Mingkai Hue4e93ea2015-10-26 19:47:51 +0800207
Tang Yuantian57894be2015-12-09 15:32:18 +0800208#ifdef CONFIG_SCSI_AHCI_PLAT
209int sata_init(void)
210{
211 struct ccsr_ahci __iomem *ccsr_ahci;
212
213 ccsr_ahci = (void *)CONFIG_SYS_SATA2;
214 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
215 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
Tang Yuantianab9c8312016-12-01 17:06:58 +0800216 out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
Tang Yuantian57894be2015-12-09 15:32:18 +0800217
218 ccsr_ahci = (void *)CONFIG_SYS_SATA1;
219 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
220 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
Tang Yuantianab9c8312016-12-01 17:06:58 +0800221 out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
Tang Yuantian57894be2015-12-09 15:32:18 +0800222
223 ahci_init((void __iomem *)CONFIG_SYS_SATA1);
224 scsi_scan(0);
225
226 return 0;
227}
228#endif
229
Prabhakar Kushwaha1966d012016-06-03 18:41:27 +0530230#elif defined(CONFIG_FSL_LSCH2)
Tang Yuantian57894be2015-12-09 15:32:18 +0800231#ifdef CONFIG_SCSI_AHCI_PLAT
232int sata_init(void)
233{
234 struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
235
York Sunbad49842016-09-26 08:09:24 -0700236#ifdef CONFIG_ARCH_LS1046A
Shaohui Xieed81e2b2016-09-07 17:56:12 +0800237 /* Disable SATA ECC */
238 out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x80000000);
239#endif
Tang Yuantian57894be2015-12-09 15:32:18 +0800240 out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
Tang Yuantian57894be2015-12-09 15:32:18 +0800241 out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
Tang Yuantian2945ae02016-08-08 15:07:20 +0800242 out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
Tang Yuantian57894be2015-12-09 15:32:18 +0800243
244 ahci_init((void __iomem *)CONFIG_SYS_SATA);
245 scsi_scan(0);
246
247 return 0;
248}
249#endif
250
Mingkai Hu8beb0752015-12-07 16:58:54 +0800251static void erratum_a009929(void)
252{
253#ifdef CONFIG_SYS_FSL_ERRATUM_A009929
254 struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
255 u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR;
256 u32 rstrqmr1 = gur_in32(&gur->rstrqmr1);
257
258 rstrqmr1 |= 0x00000400;
259 gur_out32(&gur->rstrqmr1, rstrqmr1);
260 writel(0x01000000, dcsr_cop_ccp);
261#endif
262}
263
Mingkai Hu172081c2016-02-02 11:28:03 +0800264/*
265 * This erratum requires setting a value to eddrtqcr1 to optimal
266 * the DDR performance. The eddrtqcr1 register is in SCFG space
267 * of LS1043A and the offset is 0x157_020c.
268 */
269#if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \
270 && defined(CONFIG_SYS_FSL_ERRATUM_A008514)
271#error A009660 and A008514 can not be both enabled.
272#endif
273
274static void erratum_a009660(void)
275{
276#ifdef CONFIG_SYS_FSL_ERRATUM_A009660
277 u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
278 out_be32(eddrtqcr1, 0x63b20042);
279#endif
280}
281
Shengzhou Liuddf060b2016-04-07 16:22:21 +0800282static void erratum_a008850_early(void)
283{
284#ifdef CONFIG_SYS_FSL_ERRATUM_A008850
285 /* part 1 of 2 */
286 struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
287 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
288
289 /* disables propagation of barrier transactions to DDRC from CCI400 */
290 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
291
292 /* disable the re-ordering in DDRC */
293 ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
294#endif
295}
296
297void erratum_a008850_post(void)
298{
299#ifdef CONFIG_SYS_FSL_ERRATUM_A008850
300 /* part 2 of 2 */
301 struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
302 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
303 u32 tmp;
304
305 /* enable propagation of barrier transactions to DDRC from CCI400 */
306 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
307
308 /* enable the re-ordering in DDRC */
309 tmp = ddr_in32(&ddr->eor);
310 tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
311 ddr_out32(&ddr->eor, tmp);
312#endif
313}
Hou Zhiqiang4b23ca82016-08-02 19:03:27 +0800314
315#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
316void erratum_a010315(void)
317{
318 int i;
319
320 for (i = PCIE1; i <= PCIE4; i++)
321 if (!is_serdes_configured(i)) {
322 debug("PCIe%d: disabled all R/W permission!\n", i);
323 set_pcie_ns_access(i, 0);
324 }
325}
326#endif
Shengzhou Liuddf060b2016-04-07 16:22:21 +0800327
Hou Zhiqiangc06b30a2016-09-29 12:42:44 +0800328static void erratum_a010539(void)
329{
330#if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT)
331 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
332 u32 porsr1;
333
334 porsr1 = in_be32(&gur->porsr1);
335 porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
336 out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
337 porsr1);
338#endif
339}
340
Hou Zhiqiang4ad59992016-12-09 16:09:00 +0800341/* Get VDD in the unit mV from voltage ID */
342int get_core_volt_from_fuse(void)
343{
344 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
345 int vdd;
346 u32 fusesr;
347 u8 vid;
348
349 fusesr = in_be32(&gur->dcfg_fusesr);
350 debug("%s: fusesr = 0x%x\n", __func__, fusesr);
351 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) &
352 FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK;
353 if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) {
354 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) &
355 FSL_CHASSIS2_DCFG_FUSESR_VID_MASK;
356 }
357 debug("%s: VID = 0x%x\n", __func__, vid);
358 switch (vid) {
359 case 0x00: /* VID isn't supported */
360 vdd = -EINVAL;
361 debug("%s: The VID feature is not supported\n", __func__);
362 break;
363 case 0x08: /* 0.9V silicon */
364 vdd = 900;
365 break;
366 case 0x10: /* 1.0V silicon */
367 vdd = 1000;
368 break;
369 default: /* Other core voltage */
370 vdd = -EINVAL;
371 printf("%s: The VID(%x) isn't supported\n", __func__, vid);
372 break;
373 }
374 debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
375
376 return vdd;
377}
378
379__weak int board_switch_core_volt(u32 vdd)
380{
381 return 0;
382}
383
384static int setup_core_volt(u32 vdd)
385{
386 return board_setup_core_volt(vdd);
387}
388
389#ifdef CONFIG_SYS_FSL_DDR
390static void ddr_enable_0v9_volt(bool en)
391{
392 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
393 u32 tmp;
394
395 tmp = ddr_in32(&ddr->ddr_cdr1);
396
397 if (en)
398 tmp |= DDR_CDR1_V0PT9_EN;
399 else
400 tmp &= ~DDR_CDR1_V0PT9_EN;
401
402 ddr_out32(&ddr->ddr_cdr1, tmp);
403}
404#endif
405
406int setup_chip_volt(void)
407{
408 int vdd;
409
410 vdd = get_core_volt_from_fuse();
411 /* Nothing to do for silicons doesn't support VID */
412 if (vdd < 0)
413 return vdd;
414
415 if (setup_core_volt(vdd))
416 printf("%s: Switch core VDD to %dmV failed\n", __func__, vdd);
417#ifdef CONFIG_SYS_HAS_SERDES
418 if (setup_serdes_volt(vdd))
419 printf("%s: Switch SVDD to %dmV failed\n", __func__, vdd);
420#endif
421
422#ifdef CONFIG_SYS_FSL_DDR
423 if (vdd == 900)
424 ddr_enable_0v9_volt(true);
425#endif
426
427 return 0;
428}
429
Mingkai Hue4e93ea2015-10-26 19:47:51 +0800430void fsl_lsch2_early_init_f(void)
431{
432 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
Aneesh Bansal13d984d2015-12-08 13:54:27 +0530433 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
Mingkai Hue4e93ea2015-10-26 19:47:51 +0800434
Hou Zhiqiang5ac9a5c2016-08-02 19:03:23 +0800435#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
436 enable_layerscape_ns_access();
437#endif
438
Mingkai Hue4e93ea2015-10-26 19:47:51 +0800439#ifdef CONFIG_FSL_IFC
440 init_early_memctl_regs(); /* tighten IFC timing */
441#endif
442
Qianyu Gong5ab2d0a2016-03-16 18:01:52 +0800443#if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT)
Gong Qianyu760df892016-01-25 15:16:06 +0800444 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
445#endif
Aneesh Bansal13d984d2015-12-08 13:54:27 +0530446 /* Make SEC reads and writes snoopable */
447 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
Tang Yuantian2945ae02016-08-08 15:07:20 +0800448 SCFG_SNPCNFGCR_SECWRSNP |
449 SCFG_SNPCNFGCR_SATARDSNP |
450 SCFG_SNPCNFGCR_SATAWRSNP);
Aneesh Bansal13d984d2015-12-08 13:54:27 +0530451
Mingkai Hue4e93ea2015-10-26 19:47:51 +0800452 /*
453 * Enable snoop requests and DVM message requests for
454 * Slave insterface S4 (A53 core cluster)
455 */
456 out_le32(&cci->slave[4].snoop_ctrl,
457 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
Mingkai Hu8beb0752015-12-07 16:58:54 +0800458
459 /* Erratum */
Shengzhou Liuddf060b2016-04-07 16:22:21 +0800460 erratum_a008850_early(); /* part 1 of 2 */
Mingkai Hu8beb0752015-12-07 16:58:54 +0800461 erratum_a009929();
Mingkai Hu172081c2016-02-02 11:28:03 +0800462 erratum_a009660();
Hou Zhiqiangc06b30a2016-09-29 12:42:44 +0800463 erratum_a010539();
Mingkai Hue4e93ea2015-10-26 19:47:51 +0800464}
Mingkai Hu0e58b512015-10-26 19:47:50 +0800465#endif
Scott Wood8e728cd2015-03-24 13:25:02 -0700466
Yuan Yao52ae4fd2016-12-01 10:13:52 +0800467#ifdef CONFIG_QSPI_AHB_INIT
468/* Enable 4bytes address support and fast read */
469int qspi_ahb_init(void)
470{
471 u32 *qspi_lut, lut_key, *qspi_key;
472
473 qspi_key = (void *)SYS_FSL_QSPI_ADDR + 0x300;
474 qspi_lut = (void *)SYS_FSL_QSPI_ADDR + 0x310;
475
476 lut_key = in_be32(qspi_key);
477
478 if (lut_key == 0x5af05af0) {
479 /* That means the register is BE */
480 out_be32(qspi_key, 0x5af05af0);
481 /* Unlock the lut table */
482 out_be32(qspi_key + 1, 0x00000002);
483 out_be32(qspi_lut, 0x0820040c);
484 out_be32(qspi_lut + 1, 0x1c080c08);
485 out_be32(qspi_lut + 2, 0x00002400);
486 /* Lock the lut table */
487 out_be32(qspi_key, 0x5af05af0);
488 out_be32(qspi_key + 1, 0x00000001);
489 } else {
490 /* That means the register is LE */
491 out_le32(qspi_key, 0x5af05af0);
492 /* Unlock the lut table */
493 out_le32(qspi_key + 1, 0x00000002);
494 out_le32(qspi_lut, 0x0820040c);
495 out_le32(qspi_lut + 1, 0x1c080c08);
496 out_le32(qspi_lut + 2, 0x00002400);
497 /* Lock the lut table */
498 out_le32(qspi_key, 0x5af05af0);
499 out_le32(qspi_key + 1, 0x00000001);
500 }
501
502 return 0;
503}
504#endif
505
Mingkai Hu0e58b512015-10-26 19:47:50 +0800506#ifdef CONFIG_BOARD_LATE_INIT
507int board_late_init(void)
Scott Wood8e728cd2015-03-24 13:25:02 -0700508{
Tang Yuantian57894be2015-12-09 15:32:18 +0800509#ifdef CONFIG_SCSI_AHCI_PLAT
510 sata_init();
511#endif
Aneesh Bansal39d5b3b2016-01-22 16:37:26 +0530512#ifdef CONFIG_CHAIN_OF_TRUST
513 fsl_setenv_chain_of_trust();
514#endif
Yuan Yao52ae4fd2016-12-01 10:13:52 +0800515#ifdef CONFIG_QSPI_AHB_INIT
516 qspi_ahb_init();
517#endif
Tang Yuantian57894be2015-12-09 15:32:18 +0800518
Mingkai Hu0e58b512015-10-26 19:47:50 +0800519 return 0;
Scott Wood8e728cd2015-03-24 13:25:02 -0700520}
521#endif