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David Feng3b5458c2013-12-14 11:47:37 +08001/*
2 * (C) Copyright 2013
3 * David Feng <fenghua@phytium.com.cn>
4 * Sharma Bhupesh <bhupesh.sharma@freescale.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8#include <common.h>
Simon Glass11c89f32017-05-17 17:18:03 -06009#include <dm.h>
David Feng3b5458c2013-12-14 11:47:37 +080010#include <malloc.h>
11#include <errno.h>
12#include <netdev.h>
13#include <asm/io.h>
14#include <linux/compiler.h>
David Fengab33c2c2015-01-31 11:55:29 +080015#include <dm/platform_data/serial_pl01x.h>
Liviu Dudau8d1fdc32015-10-19 11:08:32 +010016#include "pcie.h"
Alexander Graf5889e392016-03-04 01:09:51 +010017#include <asm/armv8/mmu.h>
David Feng3b5458c2013-12-14 11:47:37 +080018
19DECLARE_GLOBAL_DATA_PTR;
20
David Fengab33c2c2015-01-31 11:55:29 +080021static const struct pl01x_serial_platdata serial_platdata = {
22 .base = V2M_UART0,
23 .type = TYPE_PL011,
Linus Walleij31e476e2015-04-14 10:01:35 +020024 .clock = CONFIG_PL011_CLOCK,
David Fengab33c2c2015-01-31 11:55:29 +080025};
26
27U_BOOT_DEVICE(vexpress_serials) = {
28 .name = "serial_pl01x",
29 .platdata = &serial_platdata,
30};
31
Alexander Graf5889e392016-03-04 01:09:51 +010032static struct mm_region vexpress64_mem_map[] = {
33 {
York Sunc7104e52016-06-24 16:46:22 -070034 .virt = 0x0UL,
35 .phys = 0x0UL,
Alexander Graf5889e392016-03-04 01:09:51 +010036 .size = 0x80000000UL,
37 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
38 PTE_BLOCK_NON_SHARE |
39 PTE_BLOCK_PXN | PTE_BLOCK_UXN
40 }, {
York Sunc7104e52016-06-24 16:46:22 -070041 .virt = 0x80000000UL,
42 .phys = 0x80000000UL,
Alexander Graf5889e392016-03-04 01:09:51 +010043 .size = 0xff80000000UL,
44 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
45 PTE_BLOCK_INNER_SHARE
46 }, {
47 /* List terminator */
48 0,
49 }
50};
51
52struct mm_region *mem_map = vexpress64_mem_map;
53
Ryan Harkin8961d502015-11-18 10:39:06 +000054/* This function gets replaced by platforms supporting PCIe.
55 * The replacement function, eg. on Juno, initialises the PCIe bus.
56 */
57__weak void vexpress64_pcie_init(void)
58{
59}
60
David Feng3b5458c2013-12-14 11:47:37 +080061int board_init(void)
62{
Liviu Dudau8d1fdc32015-10-19 11:08:32 +010063 vexpress64_pcie_init();
David Feng3b5458c2013-12-14 11:47:37 +080064 return 0;
65}
66
67int dram_init(void)
68{
David Feng3b5458c2013-12-14 11:47:37 +080069 gd->ram_size = PHYS_SDRAM_1_SIZE;
70 return 0;
71}
72
Simon Glass2f949c32017-03-31 08:40:32 -060073int dram_init_banksize(void)
Liviu Dudau086c9772015-10-19 11:08:31 +010074{
75 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
76 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
Ryan Harkin98d2fff2015-11-18 10:39:07 +000077#ifdef PHYS_SDRAM_2
Liviu Dudau086c9772015-10-19 11:08:31 +010078 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
79 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
Ryan Harkin98d2fff2015-11-18 10:39:07 +000080#endif
Simon Glass2f949c32017-03-31 08:40:32 -060081
82 return 0;
Liviu Dudau086c9772015-10-19 11:08:31 +010083}
84
David Feng3b5458c2013-12-14 11:47:37 +080085/*
86 * Board specific reset that is system reset.
87 */
88void reset_cpu(ulong addr)
89{
Darwin Rambod32d4112014-06-09 11:12:59 -070090}
91
David Feng3b5458c2013-12-14 11:47:37 +080092/*
93 * Board specific ethernet initialization routine.
94 */
95int board_eth_init(bd_t *bis)
96{
97 int rc = 0;
98#ifdef CONFIG_SMC91111
99 rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
100#endif
Linus Walleij48b47552015-02-17 11:35:25 +0100101#ifdef CONFIG_SMC911X
102 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
103#endif
David Feng3b5458c2013-12-14 11:47:37 +0800104 return rc;
105}