blob: 8dfb2eea43f0bc948081a37ba7355456ac56db56 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Felipe Balbi4750eb62014-11-10 14:02:44 -06002/*
3 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
4 *
5 * Author: Felipe Balbi <balbi@ti.com>
6 *
7 * Based on board/ti/dra7xx/evm.c
Felipe Balbi4750eb62014-11-10 14:02:44 -06008 */
9
10#include <common.h>
11#include <palmas.h>
12#include <sata.h>
13#include <usb.h>
14#include <asm/omap_common.h>
Andreas Dannenberg5cf344b2016-06-27 09:19:22 -050015#include <asm/omap_sec_common.h>
Felipe Balbi4750eb62014-11-10 14:02:44 -060016#include <asm/emif.h>
Lokesh Vutla9f150672015-06-16 20:36:05 +053017#include <asm/gpio.h>
18#include <asm/arch/gpio.h>
Felipe Balbi4750eb62014-11-10 14:02:44 -060019#include <asm/arch/clock.h>
Lokesh Vutlac3d39f92015-06-04 16:42:41 +053020#include <asm/arch/dra7xx_iodelay.h>
Felipe Balbi4750eb62014-11-10 14:02:44 -060021#include <asm/arch/sys_proto.h>
22#include <asm/arch/mmc_host_def.h>
23#include <asm/arch/sata.h>
24#include <asm/arch/gpio.h>
Kishon Vijay Abraham I5f19b2d2015-08-19 14:13:19 +053025#include <asm/arch/omap.h>
Felipe Balbi4750eb62014-11-10 14:02:44 -060026#include <environment.h>
Kishon Vijay Abraham I5f19b2d2015-08-19 14:13:19 +053027#include <usb.h>
28#include <linux/usb/gadget.h>
29#include <dwc3-uboot.h>
30#include <dwc3-omap-uboot.h>
31#include <ti-usb-phy-uboot.h>
Kishon Vijay Abraham I110ed012018-01-30 16:01:52 +010032#include <mmc.h>
Felipe Balbi4750eb62014-11-10 14:02:44 -060033
Kipisz, Steven161f1382016-02-24 12:30:58 -060034#include "../common/board_detect.h"
Felipe Balbi4750eb62014-11-10 14:02:44 -060035#include "mux_data.h"
36
Kipisz, Steven161f1382016-02-24 12:30:58 -060037#define board_is_x15() board_ti_is("BBRDX15_")
Lokesh Vutla638e1c02016-11-25 11:14:20 +053038#define board_is_x15_revb1() (board_ti_is("BBRDX15_") && \
Lokesh Vutlaab4f71e2017-07-16 19:59:18 +053039 !strncmp("B.10", board_ti_get_rev(), 3))
Lokesh Vutla816178b2017-07-16 19:59:19 +053040#define board_is_x15_revc() (board_ti_is("BBRDX15_") && \
41 !strncmp("C.00", board_ti_get_rev(), 3))
Kipisz, Steven161f1382016-02-24 12:30:58 -060042#define board_is_am572x_evm() board_ti_is("AM572PM_")
Nishanth Menona2aea1c2016-11-25 11:14:19 +053043#define board_is_am572x_evm_reva3() \
44 (board_ti_is("AM572PM_") && \
Lokesh Vutlaab4f71e2017-07-16 19:59:18 +053045 !strncmp("A.30", board_ti_get_rev(), 3))
Lokesh Vutla374aea02017-12-29 11:47:52 +053046#define board_is_am574x_idk() board_ti_is("AM574IDK")
Steve Kipisz0ac8cea2016-04-08 17:01:29 -050047#define board_is_am572x_idk() board_ti_is("AM572IDK")
Steve Kipiszc95cddd2016-11-25 11:14:24 +053048#define board_is_am571x_idk() board_ti_is("AM571IDK")
Kipisz, Steven161f1382016-02-24 12:30:58 -060049
Felipe Balbi4750eb62014-11-10 14:02:44 -060050#ifdef CONFIG_DRIVER_TI_CPSW
51#include <cpsw.h>
52#endif
53
54DECLARE_GLOBAL_DATA_PTR;
55
Roger Quadros26130592017-03-13 15:04:28 +020056#define GPIO_ETH_LCD GPIO_TO_PIN(2, 22)
Lokesh Vutla9f150672015-06-16 20:36:05 +053057/* GPIO 7_11 */
58#define GPIO_DDR_VTT_EN 203
59
Nishanth Menond0f399c2017-03-13 15:04:30 +020060/* Touch screen controller to identify the LCD */
61#define OSD_TS_FT_BUS_ADDRESS 0
62#define OSD_TS_FT_CHIP_ADDRESS 0x38
63#define OSD_TS_FT_REG_ID 0xA3
64/*
65 * Touchscreen IDs for various OSD panels
66 * Ref: http://www.osddisplays.com/TI/OSD101T2587-53TS_A.1.pdf
67 */
68/* Used on newer osd101t2587 Panels */
69#define OSD_TS_FT_ID_5x46 0x54
70/* Used on older osd101t2045 Panels */
71#define OSD_TS_FT_ID_5606 0x08
72
Kipisz, Steven161f1382016-02-24 12:30:58 -060073#define SYSINFO_BOARD_NAME_MAX_LEN 45
74
Keerthyee85ebe2016-11-30 15:02:53 +053075#define TPS65903X_PRIMARY_SECONDARY_PAD2 0xFB
76#define TPS65903X_PAD2_POWERHOLD_MASK 0x20
77
Felipe Balbi4750eb62014-11-10 14:02:44 -060078const struct omap_sysinfo sysinfo = {
Kipisz, Steven161f1382016-02-24 12:30:58 -060079 "Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN\n"
Felipe Balbi4750eb62014-11-10 14:02:44 -060080};
81
82static const struct dmm_lisa_map_regs beagle_x15_lisa_regs = {
83 .dmm_lisa_map_3 = 0x80740300,
84 .is_ma_present = 0x1
85};
86
Steve Kipiszc95cddd2016-11-25 11:14:24 +053087static const struct dmm_lisa_map_regs am571x_idk_lisa_regs = {
88 .dmm_lisa_map_3 = 0x80640100,
89 .is_ma_present = 0x1
90};
91
Lokesh Vutlacbd70db2017-12-29 11:47:54 +053092static const struct dmm_lisa_map_regs am574x_idk_lisa_regs = {
93 .dmm_lisa_map_2 = 0xc0600200,
94 .dmm_lisa_map_3 = 0x80600100,
95 .is_ma_present = 0x1
96};
97
Felipe Balbi4750eb62014-11-10 14:02:44 -060098void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
99{
Steve Kipiszc95cddd2016-11-25 11:14:24 +0530100 if (board_is_am571x_idk())
101 *dmm_lisa_regs = &am571x_idk_lisa_regs;
Lokesh Vutlacbd70db2017-12-29 11:47:54 +0530102 else if (board_is_am574x_idk())
103 *dmm_lisa_regs = &am574x_idk_lisa_regs;
Steve Kipiszc95cddd2016-11-25 11:14:24 +0530104 else
105 *dmm_lisa_regs = &beagle_x15_lisa_regs;
Felipe Balbi4750eb62014-11-10 14:02:44 -0600106}
107
108static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
Keerthy66dd8062016-05-24 11:45:07 +0530109 .sdram_config_init = 0x61851b32,
110 .sdram_config = 0x61851b32,
111 .sdram_config2 = 0x08000000,
112 .ref_ctrl = 0x000040F1,
113 .ref_ctrl_final = 0x00001035,
114 .sdram_tim1 = 0xcccf36ab,
115 .sdram_tim2 = 0x308f7fda,
116 .sdram_tim3 = 0x409f88a8,
117 .read_idle_ctrl = 0x00050000,
118 .zq_config = 0x5007190b,
119 .temp_alert_config = 0x00000000,
120 .emif_ddr_phy_ctlr_1_init = 0x0024400b,
121 .emif_ddr_phy_ctlr_1 = 0x0e24400b,
122 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
123 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
124 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
125 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
126 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
127 .emif_rd_wr_lvl_rmp_win = 0x00000000,
128 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
129 .emif_rd_wr_lvl_ctl = 0x00000000,
130 .emif_rd_wr_exec_thresh = 0x00000305
Felipe Balbi4750eb62014-11-10 14:02:44 -0600131};
132
Lokesh Vutla979d2c32015-06-03 14:43:21 +0530133/* Ext phy ctrl regs 1-35 */
Felipe Balbi4750eb62014-11-10 14:02:44 -0600134static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
Lokesh Vutla979d2c32015-06-03 14:43:21 +0530135 0x10040100,
Lokesh Vutla306b5972016-03-08 09:11:35 +0530136 0x00910091,
137 0x00950095,
138 0x009B009B,
139 0x009E009E,
140 0x00980098,
Felipe Balbi4750eb62014-11-10 14:02:44 -0600141 0x00340034,
Felipe Balbi4750eb62014-11-10 14:02:44 -0600142 0x00350035,
Lokesh Vutla306b5972016-03-08 09:11:35 +0530143 0x00340034,
144 0x00310031,
145 0x00340034,
146 0x007F007F,
147 0x007F007F,
148 0x007F007F,
149 0x007F007F,
150 0x007F007F,
151 0x00480048,
152 0x004A004A,
153 0x00520052,
154 0x00550055,
155 0x00500050,
Felipe Balbi4750eb62014-11-10 14:02:44 -0600156 0x00000000,
157 0x00600020,
Lokesh Vutla979d2c32015-06-03 14:43:21 +0530158 0x40011080,
Felipe Balbi4750eb62014-11-10 14:02:44 -0600159 0x08102040,
Lokesh Vutla306b5972016-03-08 09:11:35 +0530160 0x0,
161 0x0,
162 0x0,
163 0x0,
Lokesh Vutla51a0f1f2015-06-03 14:43:22 +0530164 0x0,
165 0x0,
166 0x0,
167 0x0,
Lokesh Vutla306b5972016-03-08 09:11:35 +0530168 0x0,
Lokesh Vutla51a0f1f2015-06-03 14:43:22 +0530169 0x0
Felipe Balbi4750eb62014-11-10 14:02:44 -0600170};
171
172static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
Keerthy66dd8062016-05-24 11:45:07 +0530173 .sdram_config_init = 0x61851b32,
174 .sdram_config = 0x61851b32,
175 .sdram_config2 = 0x08000000,
176 .ref_ctrl = 0x000040F1,
177 .ref_ctrl_final = 0x00001035,
178 .sdram_tim1 = 0xcccf36b3,
179 .sdram_tim2 = 0x308f7fda,
180 .sdram_tim3 = 0x407f88a8,
181 .read_idle_ctrl = 0x00050000,
182 .zq_config = 0x5007190b,
183 .temp_alert_config = 0x00000000,
184 .emif_ddr_phy_ctlr_1_init = 0x0024400b,
185 .emif_ddr_phy_ctlr_1 = 0x0e24400b,
186 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
187 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
188 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
189 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
190 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
191 .emif_rd_wr_lvl_rmp_win = 0x00000000,
192 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
193 .emif_rd_wr_lvl_ctl = 0x00000000,
194 .emif_rd_wr_exec_thresh = 0x00000305
Felipe Balbi4750eb62014-11-10 14:02:44 -0600195};
196
197static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
Lokesh Vutla979d2c32015-06-03 14:43:21 +0530198 0x10040100,
Lokesh Vutla306b5972016-03-08 09:11:35 +0530199 0x00910091,
200 0x00950095,
201 0x009B009B,
202 0x009E009E,
203 0x00980098,
204 0x00340034,
Felipe Balbi4750eb62014-11-10 14:02:44 -0600205 0x00350035,
Lokesh Vutla306b5972016-03-08 09:11:35 +0530206 0x00340034,
207 0x00310031,
208 0x00340034,
209 0x007F007F,
210 0x007F007F,
211 0x007F007F,
212 0x007F007F,
213 0x007F007F,
214 0x00480048,
215 0x004A004A,
216 0x00520052,
217 0x00550055,
218 0x00500050,
Felipe Balbi4750eb62014-11-10 14:02:44 -0600219 0x00000000,
220 0x00600020,
Lokesh Vutla979d2c32015-06-03 14:43:21 +0530221 0x40011080,
Felipe Balbi4750eb62014-11-10 14:02:44 -0600222 0x08102040,
Lokesh Vutla306b5972016-03-08 09:11:35 +0530223 0x0,
224 0x0,
225 0x0,
226 0x0,
227 0x0,
Lokesh Vutla51a0f1f2015-06-03 14:43:22 +0530228 0x0,
229 0x0,
230 0x0,
231 0x0,
232 0x0
Felipe Balbi4750eb62014-11-10 14:02:44 -0600233};
234
Steve Kipisz81c46742017-08-22 13:52:58 +0530235static const struct emif_regs am571x_emif1_ddr3_666mhz_emif_regs = {
236 .sdram_config_init = 0x61863332,
237 .sdram_config = 0x61863332,
238 .sdram_config2 = 0x08000000,
239 .ref_ctrl = 0x0000514d,
240 .ref_ctrl_final = 0x0000144a,
241 .sdram_tim1 = 0xd333887c,
Lokesh Vutlacbd70db2017-12-29 11:47:54 +0530242 .sdram_tim2 = 0x30b37fe3,
243 .sdram_tim3 = 0x409f8ad8,
Steve Kipisz81c46742017-08-22 13:52:58 +0530244 .read_idle_ctrl = 0x00050000,
245 .zq_config = 0x5007190b,
246 .temp_alert_config = 0x00000000,
247 .emif_ddr_phy_ctlr_1_init = 0x0024400f,
248 .emif_ddr_phy_ctlr_1 = 0x0e24400f,
249 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
250 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
251 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
252 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
253 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
254 .emif_rd_wr_lvl_rmp_win = 0x00000000,
255 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
256 .emif_rd_wr_lvl_ctl = 0x00000000,
257 .emif_rd_wr_exec_thresh = 0x00000305
258};
259
Lokesh Vutlacbd70db2017-12-29 11:47:54 +0530260static const struct emif_regs am574x_emif1_ddr3_666mhz_emif_ecc_regs = {
261 .sdram_config_init = 0x61863332,
262 .sdram_config = 0x61863332,
263 .sdram_config2 = 0x08000000,
264 .ref_ctrl = 0x0000514d,
265 .ref_ctrl_final = 0x0000144a,
266 .sdram_tim1 = 0xd333887c,
267 .sdram_tim2 = 0x30b37fe3,
268 .sdram_tim3 = 0x409f8ad8,
269 .read_idle_ctrl = 0x00050000,
270 .zq_config = 0x5007190b,
271 .temp_alert_config = 0x00000000,
272 .emif_ddr_phy_ctlr_1_init = 0x0024400f,
273 .emif_ddr_phy_ctlr_1 = 0x0e24400f,
274 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
275 .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
276 .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
277 .emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
278 .emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
279 .emif_rd_wr_lvl_rmp_win = 0x00000000,
280 .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
281 .emif_rd_wr_lvl_ctl = 0x00000000,
282 .emif_rd_wr_exec_thresh = 0x00000305,
283 .emif_ecc_ctrl_reg = 0xD0000001,
284 .emif_ecc_address_range_1 = 0x3FFF0000,
285 .emif_ecc_address_range_2 = 0x00000000
286};
287
Felipe Balbi4750eb62014-11-10 14:02:44 -0600288void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
289{
290 switch (emif_nr) {
291 case 1:
Steve Kipisz81c46742017-08-22 13:52:58 +0530292 if (board_is_am571x_idk())
293 *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
Lokesh Vutlacbd70db2017-12-29 11:47:54 +0530294 else if (board_is_am574x_idk())
295 *regs = &am574x_emif1_ddr3_666mhz_emif_ecc_regs;
Steve Kipisz81c46742017-08-22 13:52:58 +0530296 else
297 *regs = &beagle_x15_emif1_ddr3_532mhz_emif_regs;
Felipe Balbi4750eb62014-11-10 14:02:44 -0600298 break;
299 case 2:
Lokesh Vutlacbd70db2017-12-29 11:47:54 +0530300 if (board_is_am574x_idk())
301 *regs = &am571x_emif1_ddr3_666mhz_emif_regs;
302 else
303 *regs = &beagle_x15_emif2_ddr3_532mhz_emif_regs;
Felipe Balbi4750eb62014-11-10 14:02:44 -0600304 break;
305 }
306}
307
308void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
309{
310 switch (emif_nr) {
311 case 1:
312 *regs = beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs;
313 *size = ARRAY_SIZE(beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs);
314 break;
315 case 2:
316 *regs = beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs;
317 *size = ARRAY_SIZE(beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs);
318 break;
319 }
320}
321
322struct vcores_data beagle_x15_volts = {
Lokesh Vutla6ede0fd2016-11-23 12:54:39 +0530323 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
324 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
Felipe Balbi4750eb62014-11-10 14:02:44 -0600325 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
326 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
327 .mpu.pmic = &tps659038,
Keerthy66dd8062016-05-24 11:45:07 +0530328 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
Felipe Balbi4750eb62014-11-10 14:02:44 -0600329
Lokesh Vutla6ede0fd2016-11-23 12:54:39 +0530330 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
331 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
332 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
333 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
334 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
335 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
Felipe Balbi4750eb62014-11-10 14:02:44 -0600336 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
337 .eve.addr = TPS659038_REG_ADDR_SMPS45,
338 .eve.pmic = &tps659038,
Nishanth Menon59b92af2016-04-21 14:34:25 -0500339 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
Felipe Balbi4750eb62014-11-10 14:02:44 -0600340
Lokesh Vutla6ede0fd2016-11-23 12:54:39 +0530341 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
342 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
343 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
344 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
345 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
346 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
Felipe Balbi4750eb62014-11-10 14:02:44 -0600347 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
348 .gpu.addr = TPS659038_REG_ADDR_SMPS45,
349 .gpu.pmic = &tps659038,
Nishanth Menon59b92af2016-04-21 14:34:25 -0500350 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
Felipe Balbi4750eb62014-11-10 14:02:44 -0600351
Lokesh Vutla6ede0fd2016-11-23 12:54:39 +0530352 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
353 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
Felipe Balbi4750eb62014-11-10 14:02:44 -0600354 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
355 .core.addr = TPS659038_REG_ADDR_SMPS6,
356 .core.pmic = &tps659038,
357
Lokesh Vutla6ede0fd2016-11-23 12:54:39 +0530358 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
359 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
360 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
361 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
362 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
363 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
Felipe Balbi4750eb62014-11-10 14:02:44 -0600364 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
365 .iva.addr = TPS659038_REG_ADDR_SMPS45,
366 .iva.pmic = &tps659038,
Nishanth Menon59b92af2016-04-21 14:34:25 -0500367 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
Felipe Balbi4750eb62014-11-10 14:02:44 -0600368};
369
Keerthy152e9932016-05-24 11:45:06 +0530370struct vcores_data am572x_idk_volts = {
Lokesh Vutla6ede0fd2016-11-23 12:54:39 +0530371 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
372 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
Keerthy152e9932016-05-24 11:45:06 +0530373 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
374 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
375 .mpu.pmic = &tps659038,
376 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
377
Lokesh Vutla6ede0fd2016-11-23 12:54:39 +0530378 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
379 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
380 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
381 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
382 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
383 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
Keerthy152e9932016-05-24 11:45:06 +0530384 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
385 .eve.addr = TPS659038_REG_ADDR_SMPS45,
386 .eve.pmic = &tps659038,
387 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
388
Lokesh Vutla6ede0fd2016-11-23 12:54:39 +0530389 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
390 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
391 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
392 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
393 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
394 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
Keerthy152e9932016-05-24 11:45:06 +0530395 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
396 .gpu.addr = TPS659038_REG_ADDR_SMPS6,
397 .gpu.pmic = &tps659038,
398 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
399
Lokesh Vutla6ede0fd2016-11-23 12:54:39 +0530400 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
401 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
Keerthy152e9932016-05-24 11:45:06 +0530402 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
403 .core.addr = TPS659038_REG_ADDR_SMPS7,
404 .core.pmic = &tps659038,
405
Lokesh Vutla6ede0fd2016-11-23 12:54:39 +0530406 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
407 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
408 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
409 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
410 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
411 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
Keerthy152e9932016-05-24 11:45:06 +0530412 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
413 .iva.addr = TPS659038_REG_ADDR_SMPS8,
414 .iva.pmic = &tps659038,
415 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
416};
417
Keerthy9cc2aee2017-05-25 15:37:34 +0530418struct vcores_data am571x_idk_volts = {
419 .mpu.value[OPP_NOM] = VDD_MPU_DRA7_NOM,
420 .mpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_MPU_NOM,
421 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
422 .mpu.addr = TPS659038_REG_ADDR_SMPS12,
423 .mpu.pmic = &tps659038,
424 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
425
426 .eve.value[OPP_NOM] = VDD_EVE_DRA7_NOM,
427 .eve.value[OPP_OD] = VDD_EVE_DRA7_OD,
428 .eve.value[OPP_HIGH] = VDD_EVE_DRA7_HIGH,
429 .eve.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
430 .eve.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_DSPEVE_OD,
431 .eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
432 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
433 .eve.addr = TPS659038_REG_ADDR_SMPS45,
434 .eve.pmic = &tps659038,
435 .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
436
437 .gpu.value[OPP_NOM] = VDD_GPU_DRA7_NOM,
438 .gpu.value[OPP_OD] = VDD_GPU_DRA7_OD,
439 .gpu.value[OPP_HIGH] = VDD_GPU_DRA7_HIGH,
440 .gpu.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_GPU_NOM,
441 .gpu.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_GPU_OD,
442 .gpu.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_GPU_HIGH,
443 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
444 .gpu.addr = TPS659038_REG_ADDR_SMPS6,
445 .gpu.pmic = &tps659038,
446 .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
447
448 .core.value[OPP_NOM] = VDD_CORE_DRA7_NOM,
449 .core.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_CORE_NOM,
450 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
451 .core.addr = TPS659038_REG_ADDR_SMPS7,
452 .core.pmic = &tps659038,
453
454 .iva.value[OPP_NOM] = VDD_IVA_DRA7_NOM,
455 .iva.value[OPP_OD] = VDD_IVA_DRA7_OD,
456 .iva.value[OPP_HIGH] = VDD_IVA_DRA7_HIGH,
457 .iva.efuse.reg[OPP_NOM] = STD_FUSE_OPP_VMIN_IVA_NOM,
458 .iva.efuse.reg[OPP_OD] = STD_FUSE_OPP_VMIN_IVA_OD,
459 .iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
460 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
461 .iva.addr = TPS659038_REG_ADDR_SMPS45,
462 .iva.pmic = &tps659038,
463 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
464};
465
Lokesh Vutla6ede0fd2016-11-23 12:54:39 +0530466int get_voltrail_opp(int rail_offset)
467{
468 int opp;
469
470 switch (rail_offset) {
471 case VOLT_MPU:
472 opp = DRA7_MPU_OPP;
473 break;
474 case VOLT_CORE:
475 opp = DRA7_CORE_OPP;
476 break;
477 case VOLT_GPU:
478 opp = DRA7_GPU_OPP;
479 break;
480 case VOLT_EVE:
481 opp = DRA7_DSPEVE_OPP;
482 break;
483 case VOLT_IVA:
484 opp = DRA7_IVA_OPP;
485 break;
486 default:
487 opp = OPP_NOM;
488 }
489
490 return opp;
491}
492
493
Kipisz, Steven161f1382016-02-24 12:30:58 -0600494#ifdef CONFIG_SPL_BUILD
495/* No env to setup for SPL */
496static inline void setup_board_eeprom_env(void) { }
497
498/* Override function to read eeprom information */
499void do_board_detect(void)
500{
501 int rc;
502
503 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
504 CONFIG_EEPROM_CHIP_ADDRESS);
505 if (rc)
506 printf("ti_i2c_eeprom_init failed %d\n", rc);
507}
508
509#else /* CONFIG_SPL_BUILD */
510
511/* Override function to read eeprom information: actual i2c read done by SPL*/
512void do_board_detect(void)
513{
514 char *bname = NULL;
515 int rc;
516
517 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
518 CONFIG_EEPROM_CHIP_ADDRESS);
519 if (rc)
520 printf("ti_i2c_eeprom_init failed %d\n", rc);
521
522 if (board_is_x15())
523 bname = "BeagleBoard X15";
524 else if (board_is_am572x_evm())
525 bname = "AM572x EVM";
Lokesh Vutla374aea02017-12-29 11:47:52 +0530526 else if (board_is_am574x_idk())
527 bname = "AM574x IDK";
Steve Kipisz0ac8cea2016-04-08 17:01:29 -0500528 else if (board_is_am572x_idk())
529 bname = "AM572x IDK";
Steve Kipiszc95cddd2016-11-25 11:14:24 +0530530 else if (board_is_am571x_idk())
531 bname = "AM571x IDK";
Kipisz, Steven161f1382016-02-24 12:30:58 -0600532
533 if (bname)
534 snprintf(sysinfo.board_string, SYSINFO_BOARD_NAME_MAX_LEN,
535 "Board: %s REV %s\n", bname, board_ti_get_rev());
536}
537
538static void setup_board_eeprom_env(void)
539{
540 char *name = "beagle_x15";
541 int rc;
542
543 rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
544 CONFIG_EEPROM_CHIP_ADDRESS);
545 if (rc)
546 goto invalid_eeprom;
547
Nishanth Menona2aea1c2016-11-25 11:14:19 +0530548 if (board_is_x15()) {
Lokesh Vutla638e1c02016-11-25 11:14:20 +0530549 if (board_is_x15_revb1())
550 name = "beagle_x15_revb1";
Lokesh Vutla816178b2017-07-16 19:59:19 +0530551 else if (board_is_x15_revc())
552 name = "beagle_x15_revc";
Lokesh Vutla638e1c02016-11-25 11:14:20 +0530553 else
554 name = "beagle_x15";
Nishanth Menona2aea1c2016-11-25 11:14:19 +0530555 } else if (board_is_am572x_evm()) {
556 if (board_is_am572x_evm_reva3())
557 name = "am57xx_evm_reva3";
558 else
559 name = "am57xx_evm";
Lokesh Vutla374aea02017-12-29 11:47:52 +0530560 } else if (board_is_am574x_idk()) {
561 name = "am574x_idk";
Nishanth Menona2aea1c2016-11-25 11:14:19 +0530562 } else if (board_is_am572x_idk()) {
Steve Kipisz0ac8cea2016-04-08 17:01:29 -0500563 name = "am572x_idk";
Steve Kipiszc95cddd2016-11-25 11:14:24 +0530564 } else if (board_is_am571x_idk()) {
565 name = "am571x_idk";
Nishanth Menona2aea1c2016-11-25 11:14:19 +0530566 } else {
Kipisz, Steven161f1382016-02-24 12:30:58 -0600567 printf("Unidentified board claims %s in eeprom header\n",
568 board_ti_get_name());
Nishanth Menona2aea1c2016-11-25 11:14:19 +0530569 }
Kipisz, Steven161f1382016-02-24 12:30:58 -0600570
571invalid_eeprom:
572 set_board_info_env(name);
573}
574
575#endif /* CONFIG_SPL_BUILD */
576
Keerthy152e9932016-05-24 11:45:06 +0530577void vcores_init(void)
578{
Lokesh Vutla6e9635c2017-12-29 11:47:53 +0530579 if (board_is_am572x_idk() || board_is_am574x_idk())
Keerthy152e9932016-05-24 11:45:06 +0530580 *omap_vcores = &am572x_idk_volts;
Keerthy9cc2aee2017-05-25 15:37:34 +0530581 else if (board_is_am571x_idk())
582 *omap_vcores = &am571x_idk_volts;
Keerthy152e9932016-05-24 11:45:06 +0530583 else
584 *omap_vcores = &beagle_x15_volts;
585}
586
Felipe Balbi4750eb62014-11-10 14:02:44 -0600587void hw_data_init(void)
588{
589 *prcm = &dra7xx_prcm;
Steve Kipisz81c46742017-08-22 13:52:58 +0530590 if (is_dra72x())
591 *dplls_data = &dra72x_dplls;
Lokesh Vutla6e9635c2017-12-29 11:47:53 +0530592 else if (is_dra76x())
593 *dplls_data = &dra76x_dplls;
Steve Kipisz81c46742017-08-22 13:52:58 +0530594 else
595 *dplls_data = &dra7xx_dplls;
Felipe Balbi4750eb62014-11-10 14:02:44 -0600596 *ctrl = &dra7xx_ctrl;
597}
598
Roger Quadros26130592017-03-13 15:04:28 +0200599bool am571x_idk_needs_lcd(void)
600{
601 bool needs_lcd;
602
603 gpio_request(GPIO_ETH_LCD, "nLCD_Detect");
604 if (gpio_get_value(GPIO_ETH_LCD))
605 needs_lcd = false;
606 else
607 needs_lcd = true;
608
609 gpio_free(GPIO_ETH_LCD);
610
611 return needs_lcd;
612}
613
Felipe Balbi4750eb62014-11-10 14:02:44 -0600614int board_init(void)
615{
616 gpmc_init();
617 gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
618
619 return 0;
620}
621
Nishanth Menond0f399c2017-03-13 15:04:30 +0200622void am57x_idk_lcd_detect(void)
Felipe Balbi4750eb62014-11-10 14:02:44 -0600623{
Nishanth Menond0f399c2017-03-13 15:04:30 +0200624 int r = -ENODEV;
625 char *idk_lcd = "no";
626 uint8_t buf = 0;
627
628 /* Only valid for IDKs */
629 if (board_is_x15() || board_is_am572x_evm())
630 return;
631
632 /* Only AM571x IDK has gpio control detect.. so check that */
633 if (board_is_am571x_idk() && !am571x_idk_needs_lcd())
634 goto out;
635
636 r = i2c_set_bus_num(OSD_TS_FT_BUS_ADDRESS);
637 if (r) {
638 printf("%s: Failed to set bus address to %d: %d\n",
639 __func__, OSD_TS_FT_BUS_ADDRESS, r);
640 goto out;
641 }
642 r = i2c_probe(OSD_TS_FT_CHIP_ADDRESS);
643 if (r) {
644 /* AM572x IDK has no explicit settings for optional LCD kit */
645 if (board_is_am571x_idk()) {
646 printf("%s: Touch screen detect failed: %d!\n",
647 __func__, r);
648 }
649 goto out;
650 }
651
652 /* Read FT ID */
653 r = i2c_read(OSD_TS_FT_CHIP_ADDRESS, OSD_TS_FT_REG_ID, 1, &buf, 1);
654 if (r) {
655 printf("%s: Touch screen ID read %d:0x%02x[0x%02x] failed:%d\n",
656 __func__, OSD_TS_FT_BUS_ADDRESS, OSD_TS_FT_CHIP_ADDRESS,
657 OSD_TS_FT_REG_ID, r);
658 goto out;
659 }
660
661 switch (buf) {
662 case OSD_TS_FT_ID_5606:
663 idk_lcd = "osd101t2045";
664 break;
665 case OSD_TS_FT_ID_5x46:
666 idk_lcd = "osd101t2587";
667 break;
668 default:
669 printf("%s: Unidentifed Touch screen ID 0x%02x\n",
670 __func__, buf);
671 /* we will let default be "no lcd" */
672 }
673out:
Simon Glass6a38e412017-08-03 12:22:09 -0600674 env_set("idk_lcd", idk_lcd);
Nishanth Menond0f399c2017-03-13 15:04:30 +0200675 return;
676}
Roger Quadros26130592017-03-13 15:04:28 +0200677
Vignesh R98c5f632018-11-29 10:57:42 +0100678#if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
679static int device_okay(const char *path)
680{
681 int node;
682
683 node = fdt_path_offset(gd->fdt_blob, path);
684 if (node < 0)
685 return 0;
686
687 return fdtdec_get_is_enabled(gd->fdt_blob, node);
688}
689#endif
690
Nishanth Menond0f399c2017-03-13 15:04:30 +0200691int board_late_init(void)
692{
Kipisz, Steven161f1382016-02-24 12:30:58 -0600693 setup_board_eeprom_env();
Keerthyee85ebe2016-11-30 15:02:53 +0530694 u8 val;
Kipisz, Steven161f1382016-02-24 12:30:58 -0600695
Felipe Balbi4750eb62014-11-10 14:02:44 -0600696 /*
697 * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
698 * This is the POWERHOLD-in-Low behavior.
699 */
700 palmas_i2c_write_u8(TPS65903X_CHIP_P1, 0xA0, 0x1);
Lokesh Vutla2c47e8c2016-11-29 11:58:02 +0530701
702 /*
703 * Default FIT boot on HS devices. Non FIT images are not allowed
704 * on HS devices.
705 */
706 if (get_device_type() == HS_DEVICE)
Simon Glass6a38e412017-08-03 12:22:09 -0600707 env_set("boot_fit", "1");
Lokesh Vutla2c47e8c2016-11-29 11:58:02 +0530708
Keerthyee85ebe2016-11-30 15:02:53 +0530709 /*
710 * Set the GPIO7 Pad to POWERHOLD. This has higher priority
711 * over DEV_CTRL.DEV_ON bit. This can be reset in case of
712 * PMIC Power off. So to be on the safer side set it back
713 * to POWERHOLD mode irrespective of the current state.
714 */
715 palmas_i2c_read_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
716 &val);
717 val = val | TPS65903X_PAD2_POWERHOLD_MASK;
718 palmas_i2c_write_u8(TPS65903X_CHIP_P1, TPS65903X_PRIMARY_SECONDARY_PAD2,
719 val);
720
Semen Protsenko4b0721f2017-02-13 19:09:37 +0200721 omap_die_id_serial();
Semen Protsenkob72dccd2017-05-22 19:16:41 +0300722 omap_set_fastboot_vars();
Semen Protsenko4b0721f2017-02-13 19:09:37 +0200723
Nishanth Menond0f399c2017-03-13 15:04:30 +0200724 am57x_idk_lcd_detect();
Roger Quadros26130592017-03-13 15:04:28 +0200725
726#if !defined(CONFIG_SPL_BUILD)
727 board_ti_set_ethaddr(2);
728#endif
729
Vignesh R98c5f632018-11-29 10:57:42 +0100730#if CONFIG_IS_ENABLED(DM_USB) && CONFIG_IS_ENABLED(OF_CONTROL)
731 if (device_okay("/ocp/omap_dwc3_1@48880000"))
732 enable_usb_clocks(0);
733 if (device_okay("/ocp/omap_dwc3_2@488c0000"))
734 enable_usb_clocks(1);
735#endif
Felipe Balbi4750eb62014-11-10 14:02:44 -0600736 return 0;
737}
738
Paul Kocialkowskia00b1e52016-02-27 19:18:56 +0100739void set_muxconf_regs(void)
Felipe Balbi4750eb62014-11-10 14:02:44 -0600740{
741 do_set_mux32((*ctrl)->control_padconf_core_base,
Lokesh Vutlac3d39f92015-06-04 16:42:41 +0530742 early_padconf, ARRAY_SIZE(early_padconf));
Felipe Balbi4750eb62014-11-10 14:02:44 -0600743}
744
Lokesh Vutlac3d39f92015-06-04 16:42:41 +0530745#ifdef CONFIG_IODELAY_RECALIBRATION
746void recalibrate_iodelay(void)
747{
Steve Kipisz0ac8cea2016-04-08 17:01:29 -0500748 const struct pad_conf_entry *pconf;
Lokesh Vutla3cb4c622017-06-05 14:48:16 +0530749 const struct iodelay_cfg_entry *iod, *delta_iod;
750 int pconf_sz, iod_sz, delta_iod_sz = 0;
Nishanth Menon8e3212e2016-11-25 11:14:22 +0530751 int ret;
Steve Kipisz0ac8cea2016-04-08 17:01:29 -0500752
Lokesh Vutla1e3425c2017-12-29 11:47:55 +0530753 if (board_is_am572x_idk()) {
Steve Kipisz0ac8cea2016-04-08 17:01:29 -0500754 pconf = core_padconf_array_essential_am572x_idk;
755 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am572x_idk);
756 iod = iodelay_cfg_array_am572x_idk;
757 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am572x_idk);
Lokesh Vutla1e3425c2017-12-29 11:47:55 +0530758 } else if (board_is_am574x_idk()) {
759 pconf = core_padconf_array_essential_am574x_idk;
760 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am574x_idk);
761 iod = iodelay_cfg_array_am574x_idk;
762 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am574x_idk);
Steve Kipiszc95cddd2016-11-25 11:14:24 +0530763 } else if (board_is_am571x_idk()) {
764 pconf = core_padconf_array_essential_am571x_idk;
765 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_am571x_idk);
766 iod = iodelay_cfg_array_am571x_idk;
767 iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk);
Steve Kipisz0ac8cea2016-04-08 17:01:29 -0500768 } else {
769 /* Common for X15/GPEVM */
770 pconf = core_padconf_array_essential_x15;
771 pconf_sz = ARRAY_SIZE(core_padconf_array_essential_x15);
Nishanth Menon8e3212e2016-11-25 11:14:22 +0530772 /* There never was an SR1.0 X15.. So.. */
773 if (omap_revision() == DRA752_ES1_1) {
774 iod = iodelay_cfg_array_x15_sr1_1;
775 iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr1_1);
776 } else {
777 /* Since full production should switch to SR2.0 */
778 iod = iodelay_cfg_array_x15_sr2_0;
779 iod_sz = ARRAY_SIZE(iodelay_cfg_array_x15_sr2_0);
780 }
Steve Kipisz0ac8cea2016-04-08 17:01:29 -0500781 }
782
Nishanth Menon8e3212e2016-11-25 11:14:22 +0530783 /* Setup I/O isolation */
784 ret = __recalibrate_iodelay_start();
785 if (ret)
786 goto err;
787
788 /* Do the muxing here */
789 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
790
791 /* Now do the weird minor deltas that should be safe */
792 if (board_is_x15() || board_is_am572x_evm()) {
Lokesh Vutla816178b2017-07-16 19:59:19 +0530793 if (board_is_x15_revb1() || board_is_am572x_evm_reva3() ||
794 board_is_x15_revc()) {
Nishanth Menon8e3212e2016-11-25 11:14:22 +0530795 pconf = core_padconf_array_delta_x15_sr2_0;
796 pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr2_0);
797 } else {
798 pconf = core_padconf_array_delta_x15_sr1_1;
799 pconf_sz = ARRAY_SIZE(core_padconf_array_delta_x15_sr1_1);
800 }
801 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
802 }
803
Roger Quadros26130592017-03-13 15:04:28 +0200804 if (board_is_am571x_idk()) {
805 if (am571x_idk_needs_lcd()) {
806 pconf = core_padconf_array_vout_am571x_idk;
807 pconf_sz = ARRAY_SIZE(core_padconf_array_vout_am571x_idk);
Lokesh Vutla3cb4c622017-06-05 14:48:16 +0530808 delta_iod = iodelay_cfg_array_am571x_idk_4port;
809 delta_iod_sz = ARRAY_SIZE(iodelay_cfg_array_am571x_idk_4port);
810
Roger Quadros26130592017-03-13 15:04:28 +0200811 } else {
812 pconf = core_padconf_array_icss1eth_am571x_idk;
813 pconf_sz = ARRAY_SIZE(core_padconf_array_icss1eth_am571x_idk);
814 }
815 do_set_mux32((*ctrl)->control_padconf_core_base, pconf, pconf_sz);
816 }
817
Nishanth Menon8e3212e2016-11-25 11:14:22 +0530818 /* Setup IOdelay configuration */
819 ret = do_set_iodelay((*ctrl)->iodelay_config_base, iod, iod_sz);
Lokesh Vutla3cb4c622017-06-05 14:48:16 +0530820 if (delta_iod_sz)
821 ret = do_set_iodelay((*ctrl)->iodelay_config_base, delta_iod,
822 delta_iod_sz);
823
Nishanth Menon8e3212e2016-11-25 11:14:22 +0530824err:
825 /* Closeup.. remove isolation */
826 __recalibrate_iodelay_end(ret);
Lokesh Vutlac3d39f92015-06-04 16:42:41 +0530827}
828#endif
829
Masahiro Yamada0a780172017-05-09 20:31:39 +0900830#if defined(CONFIG_MMC)
Felipe Balbi4750eb62014-11-10 14:02:44 -0600831int board_mmc_init(bd_t *bis)
832{
833 omap_mmc_init(0, 0, 0, -1, -1);
834 omap_mmc_init(1, 0, 0, -1, -1);
835 return 0;
836}
Kishon Vijay Abraham I110ed012018-01-30 16:01:52 +0100837
838static const struct mmc_platform_fixups am57x_es1_1_mmc1_fixups = {
839 .hw_rev = "rev11",
840 .unsupported_caps = MMC_CAP(MMC_HS_200) |
841 MMC_CAP(UHS_SDR104),
842 .max_freq = 96000000,
843};
844
845static const struct mmc_platform_fixups am57x_es1_1_mmc23_fixups = {
846 .hw_rev = "rev11",
847 .unsupported_caps = MMC_CAP(MMC_HS_200) |
848 MMC_CAP(UHS_SDR104) |
849 MMC_CAP(UHS_SDR50),
850 .max_freq = 48000000,
851};
852
853const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr)
854{
855 switch (omap_revision()) {
856 case DRA752_ES1_0:
857 case DRA752_ES1_1:
858 if (addr == OMAP_HSMMC1_BASE)
859 return &am57x_es1_1_mmc1_fixups;
860 else
861 return &am57x_es1_1_mmc23_fixups;
862 default:
863 return NULL;
864 }
865}
Felipe Balbi4750eb62014-11-10 14:02:44 -0600866#endif
867
868#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT)
869int spl_start_uboot(void)
870{
871 /* break into full u-boot on 'c' */
872 if (serial_tstc() && serial_getc() == 'c')
873 return 1;
874
875#ifdef CONFIG_SPL_ENV_SUPPORT
876 env_init();
Simon Glass17539572017-08-03 12:22:07 -0600877 env_load();
Simon Glass22c34c22017-08-03 12:22:13 -0600878 if (env_get_yesno("boot_os") != 1)
Felipe Balbi4750eb62014-11-10 14:02:44 -0600879 return 1;
880#endif
881
882 return 0;
883}
884#endif
885
886#ifdef CONFIG_DRIVER_TI_CPSW
887
888/* Delay value to add to calibrated value */
889#define RGMII0_TXCTL_DLY_VAL ((0x3 << 5) + 0x8)
890#define RGMII0_TXD0_DLY_VAL ((0x3 << 5) + 0x8)
891#define RGMII0_TXD1_DLY_VAL ((0x3 << 5) + 0x2)
892#define RGMII0_TXD2_DLY_VAL ((0x4 << 5) + 0x0)
893#define RGMII0_TXD3_DLY_VAL ((0x4 << 5) + 0x0)
894#define VIN2A_D13_DLY_VAL ((0x3 << 5) + 0x8)
895#define VIN2A_D17_DLY_VAL ((0x3 << 5) + 0x8)
896#define VIN2A_D16_DLY_VAL ((0x3 << 5) + 0x2)
897#define VIN2A_D15_DLY_VAL ((0x4 << 5) + 0x0)
898#define VIN2A_D14_DLY_VAL ((0x4 << 5) + 0x0)
899
900static void cpsw_control(int enabled)
901{
902 /* VTP can be added here */
903}
904
905static struct cpsw_slave_data cpsw_slaves[] = {
906 {
907 .slave_reg_ofs = 0x208,
908 .sliver_reg_ofs = 0xd80,
909 .phy_addr = 1,
910 },
911 {
912 .slave_reg_ofs = 0x308,
913 .sliver_reg_ofs = 0xdc0,
914 .phy_addr = 2,
915 },
916};
917
918static struct cpsw_platform_data cpsw_data = {
919 .mdio_base = CPSW_MDIO_BASE,
920 .cpsw_base = CPSW_BASE,
921 .mdio_div = 0xff,
922 .channels = 8,
923 .cpdma_reg_ofs = 0x800,
924 .slaves = 1,
925 .slave_data = cpsw_slaves,
926 .ale_reg_ofs = 0xd00,
927 .ale_entries = 1024,
928 .host_port_reg_ofs = 0x108,
929 .hw_stats_reg_ofs = 0x900,
930 .bd_ram_ofs = 0x2000,
931 .mac_control = (1 << 5),
932 .control = cpsw_control,
933 .host_port_num = 0,
934 .version = CPSW_CTRL_VERSION_2,
935};
936
Roger Quadros64217a22016-03-18 13:18:12 +0200937static u64 mac_to_u64(u8 mac[6])
938{
939 int i;
940 u64 addr = 0;
941
942 for (i = 0; i < 6; i++) {
943 addr <<= 8;
944 addr |= mac[i];
945 }
946
947 return addr;
948}
949
950static void u64_to_mac(u64 addr, u8 mac[6])
951{
952 mac[5] = addr;
953 mac[4] = addr >> 8;
954 mac[3] = addr >> 16;
955 mac[2] = addr >> 24;
956 mac[1] = addr >> 32;
957 mac[0] = addr >> 40;
958}
959
Felipe Balbi4750eb62014-11-10 14:02:44 -0600960int board_eth_init(bd_t *bis)
961{
962 int ret;
963 uint8_t mac_addr[6];
964 uint32_t mac_hi, mac_lo;
965 uint32_t ctrl_val;
Roger Quadros64217a22016-03-18 13:18:12 +0200966 int i;
967 u64 mac1, mac2;
968 u8 mac_addr1[6], mac_addr2[6];
969 int num_macs;
Felipe Balbi4750eb62014-11-10 14:02:44 -0600970
971 /* try reading mac address from efuse */
972 mac_lo = readl((*ctrl)->control_core_mac_id_0_lo);
973 mac_hi = readl((*ctrl)->control_core_mac_id_0_hi);
974 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
975 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
976 mac_addr[2] = mac_hi & 0xFF;
977 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
978 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
979 mac_addr[5] = mac_lo & 0xFF;
980
Simon Glass64b723f2017-08-03 12:22:12 -0600981 if (!env_get("ethaddr")) {
Felipe Balbi4750eb62014-11-10 14:02:44 -0600982 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
983
Joe Hershberger8ecdbed2015-04-08 01:41:04 -0500984 if (is_valid_ethaddr(mac_addr))
Simon Glass8551d552017-08-03 12:22:11 -0600985 eth_env_set_enetaddr("ethaddr", mac_addr);
Felipe Balbi4750eb62014-11-10 14:02:44 -0600986 }
987
988 mac_lo = readl((*ctrl)->control_core_mac_id_1_lo);
989 mac_hi = readl((*ctrl)->control_core_mac_id_1_hi);
990 mac_addr[0] = (mac_hi & 0xFF0000) >> 16;
991 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
992 mac_addr[2] = mac_hi & 0xFF;
993 mac_addr[3] = (mac_lo & 0xFF0000) >> 16;
994 mac_addr[4] = (mac_lo & 0xFF00) >> 8;
995 mac_addr[5] = mac_lo & 0xFF;
996
Simon Glass64b723f2017-08-03 12:22:12 -0600997 if (!env_get("eth1addr")) {
Joe Hershberger8ecdbed2015-04-08 01:41:04 -0500998 if (is_valid_ethaddr(mac_addr))
Simon Glass8551d552017-08-03 12:22:11 -0600999 eth_env_set_enetaddr("eth1addr", mac_addr);
Felipe Balbi4750eb62014-11-10 14:02:44 -06001000 }
1001
1002 ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33);
1003 ctrl_val |= 0x22;
1004 writel(ctrl_val, (*ctrl)->control_core_control_io1);
1005
Steve Kipiszc95cddd2016-11-25 11:14:24 +05301006 /* The phy address for the AM57xx IDK are different than x15 */
Lokesh Vutla6e9635c2017-12-29 11:47:53 +05301007 if (board_is_am572x_idk() || board_is_am571x_idk() ||
1008 board_is_am574x_idk()) {
Steve Kipisz0ac8cea2016-04-08 17:01:29 -05001009 cpsw_data.slave_data[0].phy_addr = 0;
1010 cpsw_data.slave_data[1].phy_addr = 1;
1011 }
1012
Felipe Balbi4750eb62014-11-10 14:02:44 -06001013 ret = cpsw_register(&cpsw_data);
1014 if (ret < 0)
1015 printf("Error %d registering CPSW switch\n", ret);
1016
Roger Quadros64217a22016-03-18 13:18:12 +02001017 /*
1018 * Export any Ethernet MAC addresses from EEPROM.
1019 * On AM57xx the 2 MAC addresses define the address range
1020 */
1021 board_ti_get_eth_mac_addr(0, mac_addr1);
1022 board_ti_get_eth_mac_addr(1, mac_addr2);
1023
1024 if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) {
1025 mac1 = mac_to_u64(mac_addr1);
1026 mac2 = mac_to_u64(mac_addr2);
1027
1028 /* must contain an address range */
1029 num_macs = mac2 - mac1 + 1;
1030 /* <= 50 to protect against user programming error */
1031 if (num_macs > 0 && num_macs <= 50) {
1032 for (i = 0; i < num_macs; i++) {
1033 u64_to_mac(mac1 + i, mac_addr);
1034 if (is_valid_ethaddr(mac_addr)) {
Simon Glass8551d552017-08-03 12:22:11 -06001035 eth_env_set_enetaddr_by_index("eth",
1036 i + 2,
1037 mac_addr);
Roger Quadros64217a22016-03-18 13:18:12 +02001038 }
1039 }
1040 }
1041 }
1042
Felipe Balbi4750eb62014-11-10 14:02:44 -06001043 return ret;
1044}
1045#endif
Lokesh Vutla9f150672015-06-16 20:36:05 +05301046
1047#ifdef CONFIG_BOARD_EARLY_INIT_F
1048/* VTT regulator enable */
1049static inline void vtt_regulator_enable(void)
1050{
1051 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1052 return;
1053
1054 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
1055 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
1056}
1057
1058int board_early_init_f(void)
1059{
1060 vtt_regulator_enable();
1061 return 0;
1062}
1063#endif
Daniel Allred7ceffb22016-05-19 19:10:54 -05001064
1065#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1066int ft_board_setup(void *blob, bd_t *bd)
1067{
1068 ft_cpu_setup(blob, bd);
1069
1070 return 0;
1071}
1072#endif
Lokesh Vutla00bf8b22016-06-10 09:35:43 +05301073
1074#ifdef CONFIG_SPL_LOAD_FIT
1075int board_fit_config_name_match(const char *name)
1076{
Lokesh Vutla638e1c02016-11-25 11:14:20 +05301077 if (board_is_x15()) {
1078 if (board_is_x15_revb1()) {
1079 if (!strcmp(name, "am57xx-beagle-x15-revb1"))
1080 return 0;
Lokesh Vutlaf35589c2017-08-23 11:39:06 +05301081 } else if (board_is_x15_revc()) {
1082 if (!strcmp(name, "am57xx-beagle-x15-revc"))
1083 return 0;
Lokesh Vutla638e1c02016-11-25 11:14:20 +05301084 } else if (!strcmp(name, "am57xx-beagle-x15")) {
1085 return 0;
1086 }
1087 } else if (board_is_am572x_evm() &&
1088 !strcmp(name, "am57xx-beagle-x15")) {
Lokesh Vutla00bf8b22016-06-10 09:35:43 +05301089 return 0;
Lokesh Vutla638e1c02016-11-25 11:14:20 +05301090 } else if (board_is_am572x_idk() && !strcmp(name, "am572x-idk")) {
Schuyler Patton99519852016-06-10 09:35:45 +05301091 return 0;
Lokesh Vutla58a3c1b2017-12-29 11:47:57 +05301092 } else if (board_is_am574x_idk() && !strcmp(name, "am574x-idk")) {
1093 return 0;
Schuyler Pattonc665e272016-11-25 11:14:25 +05301094 } else if (board_is_am571x_idk() && !strcmp(name, "am571x-idk")) {
1095 return 0;
Lokesh Vutla638e1c02016-11-25 11:14:20 +05301096 }
1097
1098 return -1;
Lokesh Vutla00bf8b22016-06-10 09:35:43 +05301099}
1100#endif
Andreas Dannenberg5cf344b2016-06-27 09:19:22 -05001101
1102#ifdef CONFIG_TI_SECURE_DEVICE
1103void board_fit_image_post_process(void **p_image, size_t *p_size)
1104{
1105 secure_boot_verify_image(p_image, p_size);
1106}
Andrew F. Davis7d250622016-11-29 16:33:26 -06001107
1108void board_tee_image_process(ulong tee_image, size_t tee_size)
1109{
1110 secure_tee_install((u32)tee_image);
1111}
1112
Alex Kiernan53295012018-05-29 15:30:49 +00001113#if CONFIG_IS_ENABLED(FASTBOOT) && !CONFIG_IS_ENABLED(ENV_IS_NOWHERE)
1114int fastboot_set_reboot_flag(void)
1115{
1116 printf("Setting reboot to fastboot flag ...\n");
1117 env_set("dofastboot", "1");
1118 env_save();
1119 return 0;
1120}
1121#endif
1122
Andrew F. Davis7d250622016-11-29 16:33:26 -06001123U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_TEE, board_tee_image_process);
Andreas Dannenberg5cf344b2016-06-27 09:19:22 -05001124#endif