ARM: DRA7: DDR3: Add support for HW leveling
DRA7 EMIF supports Full leveling for DDR3.
Adding support for the Full leveling sequence.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
diff --git a/board/ti/beagle_x15/board.c b/board/ti/beagle_x15/board.c
index ffcd531..b32d090 100644
--- a/board/ti/beagle_x15/board.c
+++ b/board/ti/beagle_x15/board.c
@@ -68,7 +68,13 @@
.emif_rd_wr_exec_thresh = 0x00000305
};
+/* Ext phy ctrl regs 1-35 */
static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
+ 0x10040100,
+ 0x00740074,
+ 0x00780078,
+ 0x007c007c,
+ 0x007b007b,
0x00800080,
0x00360036,
0x00340034,
@@ -90,7 +96,7 @@
0x00000000,
0x00600020,
- 0x40010080,
+ 0x40011080,
0x08102040,
0x00400040,
@@ -126,6 +132,11 @@
};
static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
+ 0x10040100,
+ 0x00820082,
+ 0x008b008b,
+ 0x00800080,
+ 0x007e007e,
0x00800080,
0x00370037,
0x00390039,
@@ -145,7 +156,7 @@
0x00000000,
0x00600020,
- 0x40010080,
+ 0x40011080,
0x08102040,
0x00400040,