blob: 1694ef8d9c37e08e07a347b40e8cad0fb9e37ab8 [file] [log] [blame]
developer3f7834c2023-07-19 17:17:54 +08001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2022 MediaTek Inc.
4 * Author: Sam Shih <sam.shih@mediatek.com>
5 */
6
7/dts-v1/;
8#include "mt7988.dtsi"
9#include <dt-bindings/gpio/gpio.h>
10
11/ {
12 model = "mt7988-rfb";
13 compatible = "mediatek,mt7988-rfb";
14
15 chosen {
16 stdout-path = &uart0;
17 };
18
19 memory@40000000 {
20 device_type = "memory";
21 reg = <0 0x40000000 0 0x10000000>;
22 };
23
24 reg_3p3v: regulator-3p3v {
25 compatible = "regulator-fixed";
26 regulator-name = "fixed-3.3V";
27 regulator-min-microvolt = <3300000>;
28 regulator-max-microvolt = <3300000>;
29 regulator-boot-on;
30 regulator-always-on;
31 };
32
33 reg_1p8v: regulator-1p8v {
34 compatible = "regulator-fixed";
35 regulator-name = "fixed-1.8V";
36 regulator-min-microvolt = <1800000>;
37 regulator-max-microvolt = <1800000>;
38 regulator-boot-on;
39 regulator-always-on;
40 };
41};
42
43&uart0 {
44 status = "okay";
45};
46
47&i2c1 {
48 pinctrl-names = "default";
49 pinctrl-0 = <&i2c1_pins>;
50 status = "okay";
51};
52
developer3831fef2025-01-17 17:18:27 +080053&eth0 {
developer3f7834c2023-07-19 17:17:54 +080054 status = "okay";
developer3f7834c2023-07-19 17:17:54 +080055 phy-mode = "usxgmii";
56 mediatek,switch = "mt7988";
57
58 fixed-link {
developer540a4da2025-01-17 17:18:22 +080059 speed = <10000>;
developer3f7834c2023-07-19 17:17:54 +080060 full-duplex;
61 pause;
62 };
63};
64
developer8e4a8ca2025-01-17 17:18:17 +080065&pcie0 {
66 status = "okay";
67};
68
69&pcie1 {
70 status = "okay";
71};
72
73/* PCIE2 not working in u-boot */
74&pcie2 {
75 status = "disabled";
76};
77
78/* PCIE3 not working in u-boot */
79&pcie3 {
80 status = "disabled";
81};
82
Christian Marangi3572ee52025-01-27 14:40:42 +010083&pio {
developer3f7834c2023-07-19 17:17:54 +080084 i2c1_pins: i2c1-pins {
85 mux {
86 function = "i2c";
87 groups = "i2c1_0";
88 };
89 };
90
91 pwm_pins: pwm-pins {
92 mux {
93 function = "pwm";
94 groups = "pwm0", "pwm1", "pwm2", "pwm3", "pwm4",
95 "pwm5", "pwm6", "pwm7";
96 };
97 };
98
99 spi0_pins: spi0-pins {
100 mux {
101 function = "spi";
102 groups = "spi0", "spi0_wp_hold";
103 };
developer2602d532025-01-17 17:18:41 +0800104
105 conf-pu {
106 pins = "SPI0_CSB", "SPI0_HOLD", "SPI0_WP";
107 drive-strength = <MTK_DRIVE_8mA>;
108 bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
109 };
110
111 conf-pd {
112 pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
113 drive-strength = <MTK_DRIVE_8mA>;
114 bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
115 };
116
developer3f7834c2023-07-19 17:17:54 +0800117 };
118
119 spi2_pins: spi2-pins {
120 mux {
121 function = "spi";
122 groups = "spi2", "spi2_wp_hold";
123 };
developer2602d532025-01-17 17:18:41 +0800124
125 conf-pu {
126 pins = "SPI2_CSB", "SPI2_HOLD", "SPI2_WP";
127 drive-strength = <MTK_DRIVE_8mA>;
128 bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
129 };
130
131 conf-pd {
132 pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
133 drive-strength = <MTK_DRIVE_8mA>;
134 bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
135 };
developer3f7834c2023-07-19 17:17:54 +0800136 };
137
138 mmc0_pins_default: mmc0default {
139 mux {
140 function = "flash";
141 groups = "emmc_51";
142 };
143
144 conf-cmd-dat {
145 pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
146 "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
147 "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
148 input-enable;
developer2602d532025-01-17 17:18:41 +0800149 drive-strength = <MTK_DRIVE_4mA>;
150 mediatek,pull-up-adv = <1>; /* pull-up 10K */
developer3f7834c2023-07-19 17:17:54 +0800151 };
152
153 conf-clk {
154 pins = "EMMC_CK";
developer2602d532025-01-17 17:18:41 +0800155 drive-strength = <MTK_DRIVE_6mA>;
156 mediatek,pull-down-adv = <2>; /* pull-down 50K */
developer3f7834c2023-07-19 17:17:54 +0800157 };
158
159 conf-dsl {
160 pins = "EMMC_DSL";
developer2602d532025-01-17 17:18:41 +0800161 mediatek,pull-down-adv = <2>; /* pull-down 50K */
developer3f7834c2023-07-19 17:17:54 +0800162 };
163
164 conf-rst {
165 pins = "EMMC_RSTB";
developer2602d532025-01-17 17:18:41 +0800166 drive-strength = <MTK_DRIVE_4mA>;
167 mediatek,pull-up-adv = <1>; /* pull-up 10K */
developer3f7834c2023-07-19 17:17:54 +0800168 };
169 };
170};
171
172&pwm {
173 pinctrl-names = "default";
174 pinctrl-0 = <&pwm_pins>;
175 status = "okay";
176};
177
178&spi0 {
179 pinctrl-names = "default";
180 pinctrl-0 = <&spi0_pins>;
181 #address-cells = <1>;
182 #size-cells = <0>;
183 status = "okay";
184 must_tx;
185 enhance_timing;
186 dma_ext;
187 ipm_design;
188 support_quad;
189 tick_dly = <2>;
190 sample_sel = <0>;
191
192 spi_nand@0 {
193 compatible = "spi-nand";
194 reg = <0>;
195 spi-max-frequency = <52000000>;
developer2c98ba82025-01-17 17:18:01 +0800196 spi-rx-bus-width = <4>;
197 spi-tx-bus-width = <4>;
developer3f7834c2023-07-19 17:17:54 +0800198 };
199};
200
201&spi2 {
202 pinctrl-names = "default";
203 pinctrl-0 = <&spi2_pins>;
204 #address-cells = <1>;
205 #size-cells = <0>;
206 status = "okay";
207 must_tx;
208 enhance_timing;
209 dma_ext;
210 ipm_design;
211 support_quad;
212 tick_dly = <2>;
213 sample_sel = <0>;
214
215 spi_nor@0 {
216 compatible = "jedec,spi-nor";
217 reg = <0>;
218 spi-max-frequency = <52000000>;
developer2c98ba82025-01-17 17:18:01 +0800219 spi-rx-bus-width = <4>;
220 spi-tx-bus-width = <4>;
developer3f7834c2023-07-19 17:17:54 +0800221 };
222};
223
224&mmc0 {
225 pinctrl-names = "default";
226 pinctrl-0 = <&mmc0_pins_default>;
227 max-frequency = <52000000>;
228 bus-width = <8>;
229 cap-mmc-highspeed;
230 cap-mmc-hw-reset;
231 vmmc-supply = <&reg_3p3v>;
232 vqmmc-supply = <&reg_1p8v>;
233 non-removable;
234 status = "okay";
235};