blob: 14274e2375fd55f5910abbb3259b5c53da1bb420 [file] [log] [blame]
developer3f7834c2023-07-19 17:17:54 +08001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2022 MediaTek Inc.
4 * Author: Sam Shih <sam.shih@mediatek.com>
5 */
6
7/dts-v1/;
8#include "mt7988.dtsi"
9#include <dt-bindings/gpio/gpio.h>
10
11/ {
12 model = "mt7988-rfb";
13 compatible = "mediatek,mt7988-rfb";
14
15 chosen {
16 stdout-path = &uart0;
17 };
18
19 memory@40000000 {
20 device_type = "memory";
21 reg = <0 0x40000000 0 0x10000000>;
22 };
23
24 reg_3p3v: regulator-3p3v {
25 compatible = "regulator-fixed";
26 regulator-name = "fixed-3.3V";
27 regulator-min-microvolt = <3300000>;
28 regulator-max-microvolt = <3300000>;
29 regulator-boot-on;
30 regulator-always-on;
31 };
32
33 reg_1p8v: regulator-1p8v {
34 compatible = "regulator-fixed";
35 regulator-name = "fixed-1.8V";
36 regulator-min-microvolt = <1800000>;
37 regulator-max-microvolt = <1800000>;
38 regulator-boot-on;
39 regulator-always-on;
40 };
41};
42
43&uart0 {
44 status = "okay";
45};
46
47&i2c1 {
48 pinctrl-names = "default";
49 pinctrl-0 = <&i2c1_pins>;
50 status = "okay";
51};
52
53&eth {
54 status = "okay";
55 mediatek,gmac-id = <0>;
56 phy-mode = "usxgmii";
57 mediatek,switch = "mt7988";
58
59 fixed-link {
60 speed = <1000>;
61 full-duplex;
62 pause;
63 };
64};
65
developer8e4a8ca2025-01-17 17:18:17 +080066&pcie0 {
67 status = "okay";
68};
69
70&pcie1 {
71 status = "okay";
72};
73
74/* PCIE2 not working in u-boot */
75&pcie2 {
76 status = "disabled";
77};
78
79/* PCIE3 not working in u-boot */
80&pcie3 {
81 status = "disabled";
82};
83
developer3f7834c2023-07-19 17:17:54 +080084&pinctrl {
85 i2c1_pins: i2c1-pins {
86 mux {
87 function = "i2c";
88 groups = "i2c1_0";
89 };
90 };
91
92 pwm_pins: pwm-pins {
93 mux {
94 function = "pwm";
95 groups = "pwm0", "pwm1", "pwm2", "pwm3", "pwm4",
96 "pwm5", "pwm6", "pwm7";
97 };
98 };
99
100 spi0_pins: spi0-pins {
101 mux {
102 function = "spi";
103 groups = "spi0", "spi0_wp_hold";
104 };
105 };
106
107 spi2_pins: spi2-pins {
108 mux {
109 function = "spi";
110 groups = "spi2", "spi2_wp_hold";
111 };
112 };
113
114 mmc0_pins_default: mmc0default {
115 mux {
116 function = "flash";
117 groups = "emmc_51";
118 };
119
120 conf-cmd-dat {
121 pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
122 "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
123 "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
124 input-enable;
125 };
126
127 conf-clk {
128 pins = "EMMC_CK";
129 };
130
131 conf-dsl {
132 pins = "EMMC_DSL";
133 };
134
135 conf-rst {
136 pins = "EMMC_RSTB";
137 };
138 };
139};
140
141&pwm {
142 pinctrl-names = "default";
143 pinctrl-0 = <&pwm_pins>;
144 status = "okay";
145};
146
147&spi0 {
148 pinctrl-names = "default";
149 pinctrl-0 = <&spi0_pins>;
150 #address-cells = <1>;
151 #size-cells = <0>;
152 status = "okay";
153 must_tx;
154 enhance_timing;
155 dma_ext;
156 ipm_design;
157 support_quad;
158 tick_dly = <2>;
159 sample_sel = <0>;
160
161 spi_nand@0 {
162 compatible = "spi-nand";
163 reg = <0>;
164 spi-max-frequency = <52000000>;
developer2c98ba82025-01-17 17:18:01 +0800165 spi-rx-bus-width = <4>;
166 spi-tx-bus-width = <4>;
developer3f7834c2023-07-19 17:17:54 +0800167 };
168};
169
170&spi2 {
171 pinctrl-names = "default";
172 pinctrl-0 = <&spi2_pins>;
173 #address-cells = <1>;
174 #size-cells = <0>;
175 status = "okay";
176 must_tx;
177 enhance_timing;
178 dma_ext;
179 ipm_design;
180 support_quad;
181 tick_dly = <2>;
182 sample_sel = <0>;
183
184 spi_nor@0 {
185 compatible = "jedec,spi-nor";
186 reg = <0>;
187 spi-max-frequency = <52000000>;
developer2c98ba82025-01-17 17:18:01 +0800188 spi-rx-bus-width = <4>;
189 spi-tx-bus-width = <4>;
developer3f7834c2023-07-19 17:17:54 +0800190 };
191};
192
193&mmc0 {
194 pinctrl-names = "default";
195 pinctrl-0 = <&mmc0_pins_default>;
196 max-frequency = <52000000>;
197 bus-width = <8>;
198 cap-mmc-highspeed;
199 cap-mmc-hw-reset;
200 vmmc-supply = <&reg_3p3v>;
201 vqmmc-supply = <&reg_1p8v>;
202 non-removable;
203 status = "okay";
204};