blob: b4a26efe3027f9bfc1e5e286ec0a919e74004860 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Christophe Leroy069fa832017-07-06 10:23:22 +02002/*
3 * Copyright 2008 (C) Bryan O'Donoghue
4 *
5 * Code copied & edited from Freescale mpc85xx stuff.
Christophe Leroy069fa832017-07-06 10:23:22 +02006 */
7
8#include <common.h>
Simon Glassa9dc0682019-12-28 10:44:59 -07009#include <time.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060010#include <asm/global_data.h>
Masahiro Yamada75f82d02018-03-05 01:20:11 +090011#include <linux/libfdt.h>
Christophe Leroy069fa832017-07-06 10:23:22 +020012#include <fdt_support.h>
13
14DECLARE_GLOBAL_DATA_PTR;
15
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +090016void ft_cpu_setup(void *blob, struct bd_info *bd)
Christophe Leroy069fa832017-07-06 10:23:22 +020017{
18 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
Christophe Leroy48f896d2017-07-06 10:33:17 +020019 "timebase-frequency", get_tbclk(), 1);
Christophe Leroy069fa832017-07-06 10:23:22 +020020 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
Christophe Leroy48f896d2017-07-06 10:33:17 +020021 "bus-frequency", bd->bi_busfreq, 1);
Christophe Leroy069fa832017-07-06 10:23:22 +020022 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
Christophe Leroy48f896d2017-07-06 10:33:17 +020023 "clock-frequency", bd->bi_intfreq, 1);
Christophe Leroy0bc2dc22017-07-06 10:33:19 +020024 do_fixup_by_compat_u32(blob, "fsl,pq1-soc", "clock-frequency",
25 bd->bi_intfreq, 1);
Christophe Leroy069fa832017-07-06 10:23:22 +020026 do_fixup_by_compat_u32(blob, "fsl,cpm-brg", "clock-frequency",
Christophe Leroy48f896d2017-07-06 10:33:17 +020027 gd->arch.brg_clk, 1);
Christophe Leroy069fa832017-07-06 10:23:22 +020028
Stefan Roesea13a2aa2020-08-12 13:16:36 +020029 fdt_fixup_memory(blob, (u64)gd->ram_base, (u64)gd->ram_size);
Christophe Leroy069fa832017-07-06 10:23:22 +020030}