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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Christophe Leroy069fa832017-07-06 10:23:22 +02002/*
3 * Copyright 2008 (C) Bryan O'Donoghue
4 *
5 * Code copied & edited from Freescale mpc85xx stuff.
Christophe Leroy069fa832017-07-06 10:23:22 +02006 */
7
8#include <common.h>
Masahiro Yamada75f82d02018-03-05 01:20:11 +09009#include <linux/libfdt.h>
Christophe Leroy069fa832017-07-06 10:23:22 +020010#include <fdt_support.h>
11
12DECLARE_GLOBAL_DATA_PTR;
13
14void ft_cpu_setup(void *blob, bd_t *bd)
15{
16 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
Christophe Leroy48f896d2017-07-06 10:33:17 +020017 "timebase-frequency", get_tbclk(), 1);
Christophe Leroy069fa832017-07-06 10:23:22 +020018 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
Christophe Leroy48f896d2017-07-06 10:33:17 +020019 "bus-frequency", bd->bi_busfreq, 1);
Christophe Leroy069fa832017-07-06 10:23:22 +020020 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
Christophe Leroy48f896d2017-07-06 10:33:17 +020021 "clock-frequency", bd->bi_intfreq, 1);
Christophe Leroy0bc2dc22017-07-06 10:33:19 +020022 do_fixup_by_compat_u32(blob, "fsl,pq1-soc", "clock-frequency",
23 bd->bi_intfreq, 1);
Christophe Leroy069fa832017-07-06 10:23:22 +020024 do_fixup_by_compat_u32(blob, "fsl,cpm-brg", "clock-frequency",
Christophe Leroy48f896d2017-07-06 10:33:17 +020025 gd->arch.brg_clk, 1);
Christophe Leroy069fa832017-07-06 10:23:22 +020026
27 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
28}