blob: 9c46762418142dfa8522c61f07bba34232514f9a [file] [log] [blame]
Christophe Leroy069fa832017-07-06 10:23:22 +02001/*
2 * Copyright 2008 (C) Bryan O'Donoghue
3 *
4 * Code copied & edited from Freescale mpc85xx stuff.
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#include <common.h>
Masahiro Yamada75f82d02018-03-05 01:20:11 +090010#include <linux/libfdt.h>
Christophe Leroy069fa832017-07-06 10:23:22 +020011#include <fdt_support.h>
12
13DECLARE_GLOBAL_DATA_PTR;
14
15void ft_cpu_setup(void *blob, bd_t *bd)
16{
17 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
Christophe Leroy48f896d2017-07-06 10:33:17 +020018 "timebase-frequency", get_tbclk(), 1);
Christophe Leroy069fa832017-07-06 10:23:22 +020019 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
Christophe Leroy48f896d2017-07-06 10:33:17 +020020 "bus-frequency", bd->bi_busfreq, 1);
Christophe Leroy069fa832017-07-06 10:23:22 +020021 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
Christophe Leroy48f896d2017-07-06 10:33:17 +020022 "clock-frequency", bd->bi_intfreq, 1);
Christophe Leroy0bc2dc22017-07-06 10:33:19 +020023 do_fixup_by_compat_u32(blob, "fsl,pq1-soc", "clock-frequency",
24 bd->bi_intfreq, 1);
Christophe Leroy069fa832017-07-06 10:23:22 +020025 do_fixup_by_compat_u32(blob, "fsl,cpm-brg", "clock-frequency",
Christophe Leroy48f896d2017-07-06 10:33:17 +020026 gd->arch.brg_clk, 1);
Christophe Leroy069fa832017-07-06 10:23:22 +020027
28 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
29}