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Masahiro Yamada92b8c2f2016-01-12 16:36:38 +09001menu "Clock"
2
Simon Glass36ad2342015-06-23 15:39:15 -06003config CLK
4 bool "Enable clock driver support"
5 depends on DM
6 help
7 This allows drivers to be provided for clock generators, including
8 oscillators and PLLs. Devices can use a common clock API to request
9 a particular clock rate and check on available clocks. Clocks can
10 feed into other clocks in a tree structure, with multiplexers to
11 choose the source for each clock.
12
Masahiro Yamadab16de452015-08-12 07:31:46 +090013config SPL_CLK
Simon Glass36ad2342015-06-23 15:39:15 -060014 bool "Enable clock support in SPL"
Wenyou Yange4cf4132017-07-31 15:21:57 +080015 depends on CLK && SPL && SPL_DM
Simon Glass36ad2342015-06-23 15:39:15 -060016 help
17 The clock subsystem adds a small amount of overhead to the image.
18 If this is acceptable and you have a need to use clock drivers in
19 SPL, enable this option. It might provide a cleaner interface to
20 setting up clocks within SPL, and allows the same drivers to be
21 used as U-Boot proper.
Masahiro Yamada92b8c2f2016-01-12 16:36:38 +090022
Philipp Tomsich592c3db2017-06-29 01:45:01 +020023config TPL_CLK
24 bool "Enable clock support in TPL"
25 depends on CLK && TPL_DM
26 help
27 The clock subsystem adds a small amount of overhead to the image.
28 If this is acceptable and you have a need to use clock drivers in
29 SPL, enable this option. It might provide a cleaner interface to
30 setting up clocks within TPL, and allows the same drivers to be
31 used as U-Boot proper.
32
Álvaro Fernández Rojasc35611c2017-05-07 20:13:01 +020033config CLK_BCM6345
34 bool "Clock controller driver for BCM6345"
35 depends on CLK && ARCH_BMIPS
36 default y
37 help
38 This clock driver adds support for enabling and disabling peripheral
39 clocks on BCM6345 SoCs. HW has no rate changing capabilities.
40
Paul Burton0399f442016-09-08 07:47:38 +010041config CLK_BOSTON
42 def_bool y if TARGET_BOSTON
43 depends on CLK
44 select REGMAP
45 select SYSCON
46 help
47 Enable this to support the clocks
48
Lukasz Majewski4de44bb2019-06-24 15:50:45 +020049config SPL_CLK_CCF
50 bool "SPL Common Clock Framework [CCF] support "
Adam Fordac4d80e2019-08-24 13:50:34 -050051 depends on SPL
Lukasz Majewski4de44bb2019-06-24 15:50:45 +020052 help
53 Enable this option if you want to (re-)use the Linux kernel's Common
54 Clock Framework [CCF] code in U-Boot's SPL.
55
Peng Fan2d9bd932019-07-31 07:01:54 +000056config SPL_CLK_COMPOSITE_CCF
57 bool "SPL Common Clock Framework [CCF] composite clk support "
58 depends on SPL_CLK_CCF
59 help
60 Enable this option if you want to (re-)use the Linux kernel's Common
61 Clock Framework [CCF] composite code in U-Boot's SPL.
62
Lukasz Majewski4de44bb2019-06-24 15:50:45 +020063config CLK_CCF
64 bool "Common Clock Framework [CCF] support "
Lukasz Majewski4de44bb2019-06-24 15:50:45 +020065 help
66 Enable this option if you want to (re-)use the Linux kernel's Common
67 Clock Framework [CCF] code in U-Boot's clock driver.
68
Peng Fan2d9bd932019-07-31 07:01:54 +000069config CLK_COMPOSITE_CCF
70 bool "Common Clock Framework [CCF] composite clk support "
71 depends on CLK_CCF
72 help
73 Enable this option if you want to (re-)use the Linux kernel's Common
74 Clock Framework [CCF] composite code in U-Boot's clock driver.
75
Simon Glass6eb4e3c2020-02-06 09:54:53 -070076config CLK_INTEL
77 bool "Enable clock driver for Intel x86"
78 depends on CLK && X86
79 help
80 This provides very basic support for clocks on Intel SoCs. The driver
81 is barely used at present but could be expanded as needs arise.
82 Much clock configuration in U-Boot is either set up by the FSP, or
83 set up by U-Boot itself but only statically. Thus the driver does not
84 support changing clock rates, only querying them.
85
Stefan Roese560b07f2020-07-30 13:56:16 +020086config CLK_OCTEON
87 bool "Clock controller driver for Marvell MIPS Octeon"
88 depends on CLK && ARCH_OCTEON
89 default y
90 help
91 Enable this to support the clocks on Octeon MIPS platforms.
92
Patrice Chotardd4f2d202017-11-15 13:14:48 +010093config CLK_STM32F
94 bool "Enable clock driver support for STM32F family"
95 depends on CLK && (STM32F7 || STM32F4)
96 default y
97 help
98 This clock driver adds support for RCC clock management
99 for STM32F4 and STM32F7 SoCs.
100
Eugeniy Paltsev7e1fb092017-12-10 21:20:08 +0300101config CLK_HSDK
Eugeniy Paltsev6bd63fc2020-05-07 22:20:10 +0300102 bool "Enable cgu clock driver for HSDK boards"
103 depends on CLK && TARGET_HSDK
Eugeniy Paltsev7e1fb092017-12-10 21:20:08 +0300104 help
Eugeniy Paltsev6bd63fc2020-05-07 22:20:10 +0300105 Enable this to support the cgu clocks on Synopsys ARC HSDK and
106 Synopsys ARC HSDK-4xD boards
Eugeniy Paltsev7e1fb092017-12-10 21:20:08 +0300107
Siva Durga Prasad Paladuguf7a71202019-06-23 12:24:57 +0530108config CLK_VERSAL
109 bool "Enable clock driver support for Versal"
110 depends on ARCH_VERSAL
111 select ZYNQMP_FIRMWARE
112 help
113 This clock driver adds support for clock realted settings for
114 Versal platform.
115
Liviu Dudauba024e62018-09-17 17:50:00 +0100116config CLK_VEXPRESS_OSC
117 bool "Enable driver for Arm Versatile Express OSC clock generators"
118 depends on CLK && VEXPRESS_CONFIG
119 help
120 This clock driver adds support for clock generators present on
121 Arm Versatile Express platforms.
122
Stefan Herbrechtsmeierf1f88c92017-01-17 16:27:29 +0100123config CLK_ZYNQ
124 bool "Enable clock driver support for Zynq"
125 depends on CLK && ARCH_ZYNQ
126 default y
127 help
Michal Simek8ce90432021-04-07 14:36:14 +0200128 This clock driver adds support for clock related settings for
Stefan Herbrechtsmeierf1f88c92017-01-17 16:27:29 +0100129 Zynq platform.
130
Zhengxun39df0532021-06-11 15:10:48 +0000131config CLK_XLNX_CLKWZRD
132 bool "Xilinx Clocking Wizard"
133 depends on CLK
134 help
135 Support for the Xilinx Clocking Wizard IP core clock generator.
136 The wizard support for dynamically reconfiguring the clocking
137 primitives for Multiply, Divide, Phase Shift/Offset, or Duty
138 Cycle. Limited by U-Boot clk uclass without set_phase API and
139 set_duty_cycle API, this driver only supports set_rate to modify
140 the frequency.
141
Siva Durga Prasad Paladugu468b55f2016-11-15 16:15:41 +0530142config CLK_ZYNQMP
143 bool "Enable clock driver support for ZynqMP"
144 depends on ARCH_ZYNQMP
Rajan Vaja833be322019-02-15 04:45:32 -0800145 select ZYNQMP_FIRMWARE
Siva Durga Prasad Paladugu468b55f2016-11-15 16:15:41 +0530146 help
147 This clock driver adds support for clock realted settings for
148 ZynqMP platform.
149
Patrick Delaunaye6ab6272018-03-12 10:46:15 +0100150config CLK_STM32MP1
151 bool "Enable RCC clock driver for STM32MP1"
152 depends on ARCH_STM32MP && CLK
153 default y
154 help
155 Enable the STM32 clock (RCC) driver. Enable support for
156 manipulating STM32MP1's on-SoC clocks.
157
Tero Kristo814c6112019-09-27 19:14:26 +0300158config CLK_CDCE9XX
159 bool "Enable CDCD9XX clock driver"
160 depends on CLK
161 help
162 Enable the clock synthesizer driver for CDCE913/925/937/949
163 series of chips.
164
Etienne Carriere78928e12020-09-09 18:44:04 +0200165config CLK_SCMI
166 bool "Enable SCMI clock driver"
167 depends on SCMI_FIRMWARE
168 help
169 Enable this option if you want to support clock devices exposed
170 by a SCMI agent based on SCMI clock protocol communication
171 with a SCMI server.
172
Sean Anderson152919d2021-06-11 00:16:14 -0400173config CLK_K210
174 bool "Clock support for Kendryte K210"
175 depends on CLK
176 help
177 This enables support clock driver for Kendryte K210 platforms.
178
179config CLK_K210_SET_RATE
180 bool "Enable setting the Kendryte K210 PLL rate"
181 depends on CLK_K210
182 help
183 Add functionality to calculate new rates for K210 PLLs. Enabling this
184 feature adds around 1K to U-Boot's final size.
185
Anup Patel00a156d2019-06-25 06:31:02 +0000186source "drivers/clk/analogbits/Kconfig"
Wenyou Yang8c772bd2016-07-20 17:55:12 +0800187source "drivers/clk/at91/Kconfig"
Jagan Teki9d2787c2018-07-30 18:26:18 +0530188source "drivers/clk/exynos/Kconfig"
Peng Fan5e80d5a2018-10-18 14:28:30 +0200189source "drivers/clk/imx/Kconfig"
Jerome Brunet3da39a82019-02-10 14:54:30 +0100190source "drivers/clk/meson/Kconfig"
Padmarao Begari0c4ae802021-01-15 08:20:38 +0530191source "drivers/clk/microchip/Kconfig"
Marek Behún61d74e82018-04-24 17:21:25 +0200192source "drivers/clk/mvebu/Kconfig"
Manivannan Sadhasivam91a85132018-06-14 23:38:35 +0530193source "drivers/clk/owl/Kconfig"
Jagan Teki9d2787c2018-07-30 18:26:18 +0530194source "drivers/clk/renesas/Kconfig"
Jagan Teki1d150b42018-12-22 21:32:49 +0530195source "drivers/clk/sunxi/Kconfig"
Anup Patel42fdf082019-02-25 08:14:49 +0000196source "drivers/clk/sifive/Kconfig"
Jagan Teki9d2787c2018-07-30 18:26:18 +0530197source "drivers/clk/tegra/Kconfig"
Dario Binacchida3b0202020-12-30 00:06:32 +0100198source "drivers/clk/ti/Kconfig"
Jagan Teki9d2787c2018-07-30 18:26:18 +0530199source "drivers/clk/uniphier/Kconfig"
Masahiro Yamadae4dfb052016-02-02 21:11:32 +0900200
Mario Sixa3c07062018-04-27 14:53:15 +0200201config ICS8N3QV01
202 bool "Enable ICS8N3QV01 VCXO driver"
203 depends on CLK
204 help
205 Support for the ICS8N3QV01 Quad-Frequency VCXO (Voltage-Controlled
206 Crystal Oscillator). The output frequency can be programmed via an
207 I2C interface.
208
Mario Six7cab1472018-08-06 10:23:36 +0200209config CLK_MPC83XX
210 bool "Enable MPC83xx clock driver"
211 depends on CLK
212 help
213 Support for the clock driver of the MPC83xx series of SoCs.
214
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200215config SANDBOX_CLK_CCF
216 bool "Sandbox Common Clock Framework [CCF] support "
217 depends on SANDBOX
218 select CLK_CCF
219 help
220 Enable this option if you want to test the Linux kernel's Common
221 Clock Framework [CCF] code in U-Boot's Sandbox clock driver.
222
Adam Forddb7b2f42021-06-04 12:26:06 -0500223config CLK_VERSACLOCK
224 tristate "Enable VersaClock 5/6 devices"
225 depends on CLK
226 depends on CLK_CCF
227 depends on OF_CONTROL
228 help
229 This driver supports the IDT VersaClock 5 and VersaClock 6
230 programmable clock generators.
231
Masahiro Yamada92b8c2f2016-01-12 16:36:38 +0900232endmenu