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Ruchika Gupta8ca8d822010-12-15 17:02:08 +00001/*
2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
3 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Ruchika Gupta8ca8d822010-12-15 17:02:08 +00005 */
6
7#ifndef __FSL_SECURE_BOOT_H
8#define __FSL_SECURE_BOOT_H
gaurav rana8b5ea652015-02-27 09:46:17 +05309#include <asm/config_mpc85xx.h>
Ruchika Gupta8ca8d822010-12-15 17:02:08 +000010
Po Liud1030092013-08-21 14:20:21 +080011#ifdef CONFIG_SECURE_BOOT
Aneesh Bansal43104702016-01-22 16:37:24 +053012
13#ifndef CONFIG_FIT_SIGNATURE
14#define CONFIG_CHAIN_OF_TRUST
gaurav rana8b5ea652015-02-27 09:46:17 +053015#endif
16
Ruchika Gupta8ca8d822010-12-15 17:02:08 +000017#if defined(CONFIG_FSL_CORENET)
18#define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000
York Sun4620e1f2016-11-15 18:32:50 -080019#elif defined(CONFIG_TARGET_BSC9132QDS)
Aneesh Bansalbf955b22014-03-12 00:07:27 +053020#define CONFIG_SYS_PBI_FLASH_BASE 0xc8000000
York Sunc6c51ae2016-11-16 11:51:24 -080021#elif defined(CONFIG_TARGET_C29XPCIE)
Aneesh Bansal11421b42014-12-12 15:35:04 +053022#define CONFIG_SYS_PBI_FLASH_BASE 0xcc000000
Ruchika Gupta8ca8d822010-12-15 17:02:08 +000023#else
24#define CONFIG_SYS_PBI_FLASH_BASE 0xce000000
25#endif
26#define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000
27
York Sun2dfafc62016-11-18 11:47:35 -080028#if defined(CONFIG_TARGET_B4860QDS) || \
29 defined(CONFIG_TARGET_B4420QDS) || \
Aneesh Bansalc25baec2014-03-18 23:40:59 +053030 defined(CONFIG_T4240QDS) || \
Aneesh Bansala02a44b2014-03-18 23:41:14 +053031 defined(CONFIG_T2080QDS) || \
Aneesh Bansalb6425492014-04-22 15:17:06 +053032 defined(CONFIG_T2080RDB) || \
Aneesh Bansala02a44b2014-03-18 23:41:14 +053033 defined(CONFIG_T1040QDS) || \
gaurav ranaabfd4482015-03-26 15:52:47 +053034 defined(CONFIG_T104xD4QDS) || \
Shengzhou Liue6fb7702014-11-24 17:11:54 +080035 defined(CONFIG_T104xRDB) || \
gaurav ranaabfd4482015-03-26 15:52:47 +053036 defined(CONFIG_T104xD4RDB) || \
York Sunbcee92e2016-11-18 12:35:47 -080037 defined(CONFIG_ARCH_T1023) || \
Shengzhou Liue6fb7702014-11-24 17:11:54 +080038 defined(CONFIG_PPC_T1024)
Sumit Gargafaca2a2016-07-14 12:27:52 -040039#ifndef CONFIG_SYS_RAMBOOT
Aneesh Bansal8bcbc272014-03-18 23:40:26 +053040#define CONFIG_SYS_CPC_REINIT_F
Sumit Gargafaca2a2016-07-14 12:27:52 -040041#endif
gaurav rana8b5ea652015-02-27 09:46:17 +053042#define CONFIG_KEY_REVOCATION
Aneesh Bansal8bcbc272014-03-18 23:40:26 +053043#undef CONFIG_SYS_INIT_L3_ADDR
44#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000
45#endif
46
Aneesh Bansale0f50152015-06-16 10:36:00 +053047#if defined(CONFIG_RAMBOOT_PBL)
48#undef CONFIG_SYS_INIT_L3_ADDR
Sumit Gargafaca2a2016-07-14 12:27:52 -040049#ifdef CONFIG_SYS_INIT_L3_VADDR
50#define CONFIG_SYS_INIT_L3_ADDR \
51 (CONFIG_SYS_INIT_L3_VADDR & ~0xFFF00000) | \
52 0xbff00000
53#else
54#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000
55#endif
Aneesh Bansale0f50152015-06-16 10:36:00 +053056#endif
57
York Sunc6c51ae2016-11-16 11:51:24 -080058#if defined(CONFIG_TARGET_C29XPCIE)
gaurav rana8b5ea652015-02-27 09:46:17 +053059#define CONFIG_KEY_REVOCATION
60#endif
61
York Sundf70d062016-11-18 11:20:40 -080062#if defined(CONFIG_ARCH_P3041) || \
York Sun84be8a92016-11-18 11:24:40 -080063 defined(CONFIG_ARCH_P4080) || \
York Sun2ed73f42016-11-18 11:30:56 -080064 defined(CONFIG_ARCH_P5020) || \
York Suna3c5b662016-11-18 11:39:36 -080065 defined(CONFIG_ARCH_P5040) || \
York Sun5786fca2016-11-18 11:15:21 -080066 defined(CONFIG_ARCH_P2041)
gaurav rana8b5ea652015-02-27 09:46:17 +053067 #define CONFIG_FSL_TRUST_ARCH_v1
68#endif
69
Aneesh Bansald31bb3e2015-07-31 14:10:03 +053070#if defined(CONFIG_FSL_CORENET) && !defined(CONFIG_SYS_RAMBOOT)
gaurav rana8b5ea652015-02-27 09:46:17 +053071/* The key used for verification of next level images
72 * is picked up from an Extension Table which has
73 * been verified by the ISBC (Internal Secure boot Code)
Aneesh Bansald31bb3e2015-07-31 14:10:03 +053074 * in boot ROM of the SoC.
75 * The feature is only applicable in case of NOR boot and is
76 * not applicable in case of RAMBOOT (NAND, SD, SPI).
gaurav rana8b5ea652015-02-27 09:46:17 +053077 */
78#define CONFIG_FSL_ISBC_KEY_EXT
79#endif
Aneesh Bansal43104702016-01-22 16:37:24 +053080#endif /* #ifdef CONFIG_SECURE_BOOT */
gaurav rana8b5ea652015-02-27 09:46:17 +053081
Aneesh Bansal43104702016-01-22 16:37:24 +053082#ifdef CONFIG_CHAIN_OF_TRUST
Simon Glass3aa66122016-09-12 23:18:23 -060083#ifdef CONFIG_SPL_BUILD
Sumit Gargf6d96cb2016-07-14 12:27:51 -040084/*
85 * PPAACT and SPAACT table for PAMU must be placed on DDR after DDR init
86 * due to space crunch on CPC and thus malloc will not work.
87 */
88#define CONFIG_SPL_PPAACT_ADDR 0x2e000000
89#define CONFIG_SPL_SPAACT_ADDR 0x2f000000
90#define CONFIG_SPL_JR0_LIODN_S 454
91#define CONFIG_SPL_JR0_LIODN_NS 458
92/*
93 * Define the key hash for U-Boot here if public/private key pair used to
94 * sign U-boot are different from the SRK hash put in the fuse
95 * Example of defining KEY_HASH is
96 * #define CONFIG_SPL_UBOOT_KEY_HASH \
97 * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b"
98 * else leave it defined as NULL
99 */
100
101#define CONFIG_SPL_UBOOT_KEY_HASH NULL
102#endif /* ifdef CONFIG_SPL_BUILD */
103
Aneesh Bansal43104702016-01-22 16:37:24 +0530104#define CONFIG_CMD_ESBC_VALIDATE
105#define CONFIG_CMD_BLOB
106#define CONFIG_FSL_SEC_MON
107#define CONFIG_SHA_PROG_HW_ACCEL
Aneesh Bansal43104702016-01-22 16:37:24 +0530108#define CONFIG_RSA_FREESCALE_EXP
109
Aneesh Bansal43104702016-01-22 16:37:24 +0530110#ifndef CONFIG_FSL_CAAM
111#define CONFIG_FSL_CAAM
112#endif
113
Sumit Gargf6d96cb2016-07-14 12:27:51 -0400114#ifndef CONFIG_SPL_BUILD
115/*
116 * fsl_setenv_chain_of_trust() must be called from
Aneesh Bansalc6249092016-01-22 16:37:27 +0530117 * board_late_init()
118 */
119#ifndef CONFIG_BOARD_LATE_INIT
120#define CONFIG_BOARD_LATE_INIT
121#endif
122
Aneesh Bansalb69061d2015-06-16 10:36:43 +0530123/* If Boot Script is not on NOR and is required to be copied on RAM */
124#ifdef CONFIG_BOOTSCRIPT_COPY_RAM
125#define CONFIG_BS_HDR_ADDR_RAM 0x00010000
Sumit Garg45642832016-06-14 13:52:39 -0400126#define CONFIG_BS_HDR_ADDR_DEVICE 0x00800000
Aneesh Bansalb69061d2015-06-16 10:36:43 +0530127#define CONFIG_BS_HDR_SIZE 0x00002000
128#define CONFIG_BS_ADDR_RAM 0x00012000
Sumit Garg45642832016-06-14 13:52:39 -0400129#define CONFIG_BS_ADDR_DEVICE 0x00802000
Aneesh Bansalb69061d2015-06-16 10:36:43 +0530130#define CONFIG_BS_SIZE 0x00001000
131
132#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM
133#else
134
gaurav ranaf79323c2015-03-10 14:08:50 +0530135/* The bootscript header address is different for B4860 because the NOR
136 * mapping is different on B4 due to reduced NOR size.
137 */
York Sun2dfafc62016-11-18 11:47:35 -0800138#if defined(CONFIG_TARGET_B4860QDS) || defined(CONFIG_TARGET_B4420QDS)
gaurav ranaf79323c2015-03-10 14:08:50 +0530139#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xecc00000
140#elif defined(CONFIG_FSL_CORENET)
141#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xe8e00000
York Sun4620e1f2016-11-15 18:32:50 -0800142#elif defined(CONFIG_TARGET_BSC9132QDS)
gaurav ranaf79323c2015-03-10 14:08:50 +0530143#define CONFIG_BOOTSCRIPT_HDR_ADDR 0x88020000
York Sunc6c51ae2016-11-16 11:51:24 -0800144#elif defined(CONFIG_TARGET_C29XPCIE)
gaurav ranaf79323c2015-03-10 14:08:50 +0530145#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xec020000
146#else
147#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xee020000
148#endif
149
Aneesh Bansal43104702016-01-22 16:37:24 +0530150#endif /* #ifdef CONFIG_BOOTSCRIPT_COPY_RAM */
gaurav ranaf79323c2015-03-10 14:08:50 +0530151
Aneesh Bansal43104702016-01-22 16:37:24 +0530152#include <config_fsl_chain_trust.h>
Sumit Gargf6d96cb2016-07-14 12:27:51 -0400153#endif /* #ifndef CONFIG_SPL_BUILD */
Aneesh Bansal43104702016-01-22 16:37:24 +0530154#endif /* #ifdef CONFIG_CHAIN_OF_TRUST */
Po Liud1030092013-08-21 14:20:21 +0800155#endif