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git01.mediatek.com / filogic / uboot / bb1187bc91afeb703cb44bf38afb73234de6a749 / . / arch / arm / include / asm / arch-rockchip / cru_rk3368.h
blob: ed2a61218552bd88d26addf0adf3cd82712602c7 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Andy Yanb9909aa2017-05-15 17:49:56 +0800[diff] [blame]2/*
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
4 * Author: Andy Yan <andy.yan@rock-chips.com>
Andy Yanb9909aa2017-05-15 17:49:56 +0800[diff] [blame]5 */
6#ifndef _ASM_ARCH_CRU_RK3368_H
7#define _ASM_ARCH_CRU_RK3368_H
8
Simon Glass4dcacfc2020-05-10 11:40:13 -0600[diff] [blame]9#ifndef __ASSEMBLY__
10#include <linux/bitops.h>
11#endif
12
Andy Yanb9909aa2017-05-15 17:49:56 +0800[diff] [blame]13/* RK3368 clock numbers */
14enum rk3368_pll_id {
15 APLLB,
16 APLLL,
17 DPLL,
18 CPLL,
19 GPLL,
20 NPLL,
21 PLL_COUNT,
22};
23
24struct rk3368_cru {
25 struct rk3368_pll {
26 unsigned int con0;
27 unsigned int con1;
28 unsigned int con2;
29 unsigned int con3;
30 } pll[6];
31 unsigned int reserved[0x28];
32 unsigned int clksel_con[56];
33 unsigned int reserved1[8];
34 unsigned int clkgate_con[25];
35 unsigned int reserved2[7];
36 unsigned int glb_srst_fst_val;
37 unsigned int glb_srst_snd_val;
38 unsigned int reserved3[0x1e];
39 unsigned int softrst_con[15];
40 unsigned int reserved4[0x11];
41 unsigned int misc_con;
42 unsigned int glb_cnt_th;
43 unsigned int glb_rst_con;
44 unsigned int glb_rst_st;
45 unsigned int reserved5[0x1c];
46 unsigned int sdmmc_con[2];
47 unsigned int sdio0_con[2];
48 unsigned int sdio1_con[2];
49 unsigned int emmc_con[2];
50};
51check_member(rk3368_cru, emmc_con[1], 0x41c);
52
53struct rk3368_clk_priv {
54 struct rk3368_cru *cru;
Andy Yanb9909aa2017-05-15 17:49:56 +0800[diff] [blame]55};
56
57enum {
58 /* PLL CON0 */
59 PLL_NR_SHIFT = 8,
60 PLL_NR_MASK = GENMASK(13, 8),
61 PLL_OD_SHIFT = 0,
62 PLL_OD_MASK = GENMASK(3, 0),
63
64 /* PLL CON1 */
65 PLL_LOCK_STA = BIT(31),
66 PLL_NF_SHIFT = 0,
67 PLL_NF_MASK = GENMASK(12, 0),
68
69 /* PLL CON2 */
70 PLL_BWADJ_SHIFT = 0,
71 PLL_BWADJ_MASK = GENMASK(11, 0),
72
73 /* PLL CON3 */
74 PLL_MODE_SHIFT = 8,
75 PLL_MODE_MASK = GENMASK(9, 8),
76 PLL_MODE_SLOW = 0,
77 PLL_MODE_NORMAL = 1,
78 PLL_MODE_DEEP_SLOW = 3,
79 PLL_RESET_SHIFT = 5,
80 PLL_RESET = 1,
81 PLL_RESET_MASK = GENMASK(5, 5),
82
83 /* CLKSEL12_CON */
84 MCU_STCLK_DIV_SHIFT = 8,
85 MCU_STCLK_DIV_MASK = GENMASK(10, 8),
86 MCU_PLL_SEL_SHIFT = 7,
87 MCU_PLL_SEL_MASK = BIT(7),
88 MCU_PLL_SEL_CPLL = 0,
89 MCU_PLL_SEL_GPLL = 1,
90 MCU_CLK_DIV_SHIFT = 0,
91 MCU_CLK_DIV_MASK = GENMASK(4, 0),
92
David Wu4771ba62017-09-20 14:37:50 +0800[diff] [blame]93 /* CLKSEL_CON25 */
94 CLK_SARADC_DIV_CON_SHIFT = 8,
95 CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8),
96 CLK_SARADC_DIV_CON_WIDTH = 8,
97
Philipp Tomsicha249f102017-07-14 19:57:39 +0200[diff] [blame]98 /* CLKSEL43_CON */
David Wue72793d2018-01-13 14:07:04 +0800[diff] [blame]99 GMAC_DIV_CON_SHIFT = 0x0,
100 GMAC_DIV_CON_MASK = GENMASK(4, 0),
101 GMAC_PLL_SHIFT = 6,
102 GMAC_PLL_MASK = GENMASK(7, 6),
103 GMAC_PLL_SELECT_NEW = (0x0 << GMAC_PLL_SHIFT),
104 GMAC_PLL_SELECT_CODEC = (0x1 << GMAC_PLL_SHIFT),
105 GMAC_PLL_SELECT_GENERAL = (0x2 << GMAC_PLL_SHIFT),
Philipp Tomsicha249f102017-07-14 19:57:39 +0200[diff] [blame]106 GMAC_MUX_SEL_EXTCLK = BIT(8),
107
Andy Yanb9909aa2017-05-15 17:49:56 +0800[diff] [blame]108 /* CLKSEL51_CON */
109 MMC_PLL_SEL_SHIFT = 8,
110 MMC_PLL_SEL_MASK = GENMASK(9, 8),
Philipp Tomsichfbf07a52017-07-04 14:49:38 +0200[diff] [blame]111 MMC_PLL_SEL_CPLL = (0 << MMC_PLL_SEL_SHIFT),
112 MMC_PLL_SEL_GPLL = (1 << MMC_PLL_SEL_SHIFT),
113 MMC_PLL_SEL_USBPHY_480M = (2 << MMC_PLL_SEL_SHIFT),
114 MMC_PLL_SEL_24M = (3 << MMC_PLL_SEL_SHIFT),
Andy Yanb9909aa2017-05-15 17:49:56 +0800[diff] [blame]115 MMC_CLK_DIV_SHIFT = 0,
116 MMC_CLK_DIV_MASK = GENMASK(6, 0),
117
118 /* SOFTRST1_CON */
119 MCU_PO_SRST_MASK = BIT(13),
120 MCU_SYS_SRST_MASK = BIT(12),
Philipp Tomsichd4d9c802017-07-04 14:50:11 +0200[diff] [blame]121 DMA1_SRST_REQ = BIT(2),
122
123 /* SOFTRST4_CON */
124 DMA2_SRST_REQ = BIT(0),
Andy Yanb9909aa2017-05-15 17:49:56 +0800[diff] [blame]125
126 /* GLB_RST_CON */
127 PMU_GLB_SRST_CTRL_SHIFT = 2,
128 PMU_GLB_SRST_CTRL_MASK = GENMASK(3, 2),
Wolfgang Denk62fb2b42021-09-27 17:42:39 +0200[diff] [blame]129 PMU_RST_BY_FST_GLB_SRST = 0,
130 PMU_RST_BY_SND_GLB_SRST = 1,
Andy Yanb9909aa2017-05-15 17:49:56 +0800[diff] [blame]131 PMU_RST_DISABLE = 2,
132 WDT_GLB_SRST_CTRL_SHIFT = 1,
133 WDT_GLB_SRST_CTRL_MASK = BIT(1),
Wolfgang Denk62fb2b42021-09-27 17:42:39 +0200[diff] [blame]134 WDT_TRIGGER_SND_GLB_SRST = 0,
135 WDT_TRIGGER_FST_GLB_SRST = 1,
136 TSADC_GLB_SRST_CTRL_SHIFT = 0,
137 TSADC_GLB_SRST_CTRL_MASK = BIT(0),
138 TSADC_TRIGGER_SND_GLB_SRST = 0,
139 TSADC_TRIGGER_FST_GLB_SRST = 1,
Andy Yanb9909aa2017-05-15 17:49:56 +0800[diff] [blame]140
141};
142#endif