| commit | 4771ba647659899480f11146a3a8973edbd525d6 | [log] [tgz] |
|---|---|---|
| author | David Wu <david.wu@rock-chips.com> | Wed Sep 20 14:37:50 2017 +0800 |
| committer | Philipp Tomsich <philipp.tomsich@theobroma-systems.com> | Sun Oct 01 00:33:30 2017 +0200 |
| tree | c9a66b0378ef68ef7f9273b4598d0143cb7d5a1c | |
| parent | a9422235a4bacd1847613a279a1f2eecd21d0c68 [diff] |
rockchip: clk: Add rk3368 SARADC clock support The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1). SARADC integer divider control register is 8-bits width. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>