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git01.mediatek.com / filogic / uboot / bae55654982c61c03e149ce98b508cba239b89df / . / arch / arm / mach-socfpga / wrap_sdram_config.c
blob: 8f3fbaf80c8c61703d0226880821cc5811a2a42b [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]2/*
3 * Copyright (C) 2015 Marek Vasut <marex@denx.de>
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]4 */
5
Tom Rinidec7ea02024-05-20 13:35:03 -0600[diff] [blame]6#include <config.h>
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]7#include <errno.h>
Tom Rinidec7ea02024-05-20 13:35:03 -0600[diff] [blame]8#include <linux/types.h>
9#include <linux/kernel.h>
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]10#include <asm/arch/sdram.h>
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]11
Marek Vasut372f70d2015-08-10 21:21:07 +0200[diff] [blame]12/* Board-specific header. */
13#include <qts/sdram_config.h>
Marek Vasut3384e742015-08-02 17:15:19 +0200[diff] [blame]14
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]15static const struct socfpga_sdram_config sdram_config = {
16 .ctrl_cfg =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]17 (CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]18 SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]19 (CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]20 SDR_CTRLGRP_CTRLCFG_MEMBL_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]21 (CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]22 SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]23 (CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]24 SDR_CTRLGRP_CTRLCFG_ECCEN_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]25 (CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]26 SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]27 (CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]28 SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]29 (CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]30 SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]31 (CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]32 SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]33 (CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]34 SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB),
35 .dram_timing1 =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]36 (CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]37 SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]38 (CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]39 SDR_CTRLGRP_DRAMTIMING1_TAL_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]40 (CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]41 SDR_CTRLGRP_DRAMTIMING1_TCL_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]42 (CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]43 SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]44 (CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]45 SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]46 (CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]47 SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB),
48 .dram_timing2 =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]49 (CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]50 SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]51 (CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]52 SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]53 (CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]54 SDR_CTRLGRP_DRAMTIMING2_TRP_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]55 (CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]56 SDR_CTRLGRP_DRAMTIMING2_TWR_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]57 (CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]58 SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB),
59 .dram_timing3 =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]60 (CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]61 SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]62 (CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]63 SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]64 (CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]65 SDR_CTRLGRP_DRAMTIMING3_TRC_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]66 (CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]67 SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]68 (CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]69 SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB),
70 .dram_timing4 =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]71 (CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]72 SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]73 (CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]74 SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB),
75 .lowpwr_timing =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]76 (CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]77 SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]78 (CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]79 SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB),
80 .dram_odt =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]81 (CFG_HPS_SDR_CTRLCFG_DRAMODT_READ <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]82 SDR_CTRLGRP_DRAMODT_READ_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]83 (CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]84 SDR_CTRLGRP_DRAMODT_WRITE_LSB),
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]85#if (CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 2) /* DDR3 */
Chin Liang See3ea59512016-09-21 10:25:56 +0800[diff] [blame]86 .extratime1 =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]87 (CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR <<
Marek Vasut6bccacf2019-10-18 00:22:31 +0200[diff] [blame]88 SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]89 (CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC <<
Marek Vasut6bccacf2019-10-18 00:22:31 +0200[diff] [blame]90 SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]91 (CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP <<
Marek Vasut6bccacf2019-10-18 00:22:31 +0200[diff] [blame]92 SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB),
93#endif
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]94 .dram_addrw =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]95 (CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]96 SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]97 (CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]98 SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]99 (CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]100 SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]101 ((CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]102 SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB),
103 .dram_if_width =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]104 (CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]105 SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB),
106 .dram_dev_width =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]107 (CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]108 SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB),
109 .dram_intr =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]110 (CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]111 SDR_CTRLGRP_DRAMINTR_INTREN_LSB),
112 .lowpwr_eq =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]113 (CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]114 SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB),
115 .static_cfg =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]116 (CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]117 SDR_CTRLGRP_STATICCFG_MEMBL_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]118 (CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]119 SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB),
120 .ctrl_width =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]121 (CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]122 SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB),
123 .cport_width =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]124 (CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]125 SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB),
126 .cport_wmap =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]127 (CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]128 SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB),
129 .cport_rmap =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]130 (CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]131 SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB),
132 .rfifo_cmap =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]133 (CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]134 SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB),
135 .wfifo_cmap =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]136 (CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]137 SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB),
138 .cport_rdwr =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]139 (CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]140 SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB),
141 .port_cfg =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]142 (CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]143 SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB),
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]144 .fpgaport_rst = CFG_HPS_SDR_CTRLCFG_FPGAPORTRST,
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]145 .fifo_cfg =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]146 (CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]147 SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]148 (CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]149 SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB),
150 .mp_priority =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]151 (CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]152 SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB),
153 .mp_weight0 =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]154 (CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]155 SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB),
156 .mp_weight1 =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]157 (CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]158 SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]159 (CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]160 SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB),
161 .mp_weight2 =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]162 (CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]163 SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB),
164 .mp_weight3 =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]165 (CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]166 SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB),
167 .mp_pacing0 =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]168 (CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]169 SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB),
170 .mp_pacing1 =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]171 (CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]172 SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB) |
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]173 (CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]174 SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB),
175 .mp_pacing2 =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]176 (CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]177 SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB),
178 .mp_pacing3 =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]179 (CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]180 SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB),
181 .mp_threshold0 =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]182 (CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]183 SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB),
184 .mp_threshold1 =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]185 (CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]186 SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB),
187 .mp_threshold2 =
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]188 (CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]189 SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB),
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]190 .phy_ctrl0 = CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0,
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]191};
192
Marek Vasut39b620e2015-08-02 18:12:08 +0200[diff] [blame]193static const struct socfpga_sdram_rw_mgr_config rw_mgr_config = {
194 .activate_0_and_1 = RW_MGR_ACTIVATE_0_AND_1,
195 .activate_0_and_1_wait1 = RW_MGR_ACTIVATE_0_AND_1_WAIT1,
196 .activate_0_and_1_wait2 = RW_MGR_ACTIVATE_0_AND_1_WAIT2,
Marek Vasut39b620e2015-08-02 18:12:08 +0200[diff] [blame]197 .clear_dqs_enable = RW_MGR_CLEAR_DQS_ENABLE,
198 .guaranteed_read = RW_MGR_GUARANTEED_READ,
199 .guaranteed_read_cont = RW_MGR_GUARANTEED_READ_CONT,
200 .guaranteed_write = RW_MGR_GUARANTEED_WRITE,
201 .guaranteed_write_wait0 = RW_MGR_GUARANTEED_WRITE_WAIT0,
202 .guaranteed_write_wait1 = RW_MGR_GUARANTEED_WRITE_WAIT1,
203 .guaranteed_write_wait2 = RW_MGR_GUARANTEED_WRITE_WAIT2,
204 .guaranteed_write_wait3 = RW_MGR_GUARANTEED_WRITE_WAIT3,
Marek Vasut39b620e2015-08-02 18:12:08 +0200[diff] [blame]205 .idle_loop1 = RW_MGR_IDLE_LOOP1,
206 .idle_loop2 = RW_MGR_IDLE_LOOP2,
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]207#if (CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 1) /* DDR2 */
Marek Vasut6bccacf2019-10-18 00:22:31 +0200[diff] [blame]208 .emr = RW_MGR_EMR,
209 .emr2 = RW_MGR_EMR2,
210 .emr3 = RW_MGR_EMR3,
211 .init_reset_0_cke_0 = RW_MGR_INIT_CKE_0,
212 .nop = RW_MGR_NOP,
213 .refresh = RW_MGR_REFRESH,
214 .mr_calib = RW_MGR_MR_CALIB,
215 .mr_user = RW_MGR_MR_USER,
216 .mr_dll_reset = RW_MGR_MR_DLL_RESET,
217 .emr_ocd_enable = RW_MGR_EMR_OCD_ENABLE,
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]218#elif (CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 2) /* DDR3 */
Marek Vasut6bccacf2019-10-18 00:22:31 +0200[diff] [blame]219 .activate_1 = RW_MGR_ACTIVATE_1,
220 .idle = RW_MGR_IDLE,
Marek Vasut39b620e2015-08-02 18:12:08 +0200[diff] [blame]221 .init_reset_0_cke_0 = RW_MGR_INIT_RESET_0_CKE_0,
222 .init_reset_1_cke_0 = RW_MGR_INIT_RESET_1_CKE_0,
Marek Vasut6bccacf2019-10-18 00:22:31 +0200[diff] [blame]223 .mrs1 = RW_MGR_MRS1,
224 .mrs1_mirr = RW_MGR_MRS1_MIRR,
225 .mrs2 = RW_MGR_MRS2,
226 .mrs2_mirr = RW_MGR_MRS2_MIRR,
227 .mrs3 = RW_MGR_MRS3,
228 .mrs3_mirr = RW_MGR_MRS3_MIRR,
229 .refresh_all = RW_MGR_REFRESH_ALL,
230 .rreturn = RW_MGR_RETURN,
231 .sgle_read = RW_MGR_SGLE_READ,
232 .zqcl = RW_MGR_ZQCL,
233 .mrs0_dll_reset = RW_MGR_MRS0_DLL_RESET,
234 .mrs0_dll_reset_mirr = RW_MGR_MRS0_DLL_RESET_MIRR,
235 .mrs0_user = RW_MGR_MRS0_USER,
236 .mrs0_user_mirr = RW_MGR_MRS0_USER_MIRR,
237#else
238#error LPDDR2 and other DRAM types are not yet supported
239#endif
Marek Vasut39b620e2015-08-02 18:12:08 +0200[diff] [blame]240 .lfsr_wr_rd_bank_0 = RW_MGR_LFSR_WR_RD_BANK_0,
241 .lfsr_wr_rd_bank_0_data = RW_MGR_LFSR_WR_RD_BANK_0_DATA,
242 .lfsr_wr_rd_bank_0_dqs = RW_MGR_LFSR_WR_RD_BANK_0_DQS,
243 .lfsr_wr_rd_bank_0_nop = RW_MGR_LFSR_WR_RD_BANK_0_NOP,
244 .lfsr_wr_rd_bank_0_wait = RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
245 .lfsr_wr_rd_bank_0_wl_1 = RW_MGR_LFSR_WR_RD_BANK_0_WL_1,
246 .lfsr_wr_rd_dm_bank_0 = RW_MGR_LFSR_WR_RD_DM_BANK_0,
247 .lfsr_wr_rd_dm_bank_0_data = RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
248 .lfsr_wr_rd_dm_bank_0_dqs = RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
249 .lfsr_wr_rd_dm_bank_0_nop = RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
250 .lfsr_wr_rd_dm_bank_0_wait = RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
251 .lfsr_wr_rd_dm_bank_0_wl_1 = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1,
Marek Vasut39b620e2015-08-02 18:12:08 +0200[diff] [blame]252 .precharge_all = RW_MGR_PRECHARGE_ALL,
253 .read_b2b = RW_MGR_READ_B2B,
254 .read_b2b_wait1 = RW_MGR_READ_B2B_WAIT1,
255 .read_b2b_wait2 = RW_MGR_READ_B2B_WAIT2,
Marek Vasut39b620e2015-08-02 18:12:08 +0200[diff] [blame]256
257 .true_mem_data_mask_width = RW_MGR_TRUE_MEM_DATA_MASK_WIDTH,
258 .mem_address_mirroring = RW_MGR_MEM_ADDRESS_MIRRORING,
259 .mem_data_mask_width = RW_MGR_MEM_DATA_MASK_WIDTH,
260 .mem_data_width = RW_MGR_MEM_DATA_WIDTH,
261 .mem_dq_per_read_dqs = RW_MGR_MEM_DQ_PER_READ_DQS,
262 .mem_dq_per_write_dqs = RW_MGR_MEM_DQ_PER_WRITE_DQS,
263 .mem_if_read_dqs_width = RW_MGR_MEM_IF_READ_DQS_WIDTH,
264 .mem_if_write_dqs_width = RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
265 .mem_number_of_cs_per_dimm = RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
266 .mem_number_of_ranks = RW_MGR_MEM_NUMBER_OF_RANKS,
267 .mem_virtual_groups_per_read_dqs =
268 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
269 .mem_virtual_groups_per_write_dqs =
270 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS,
271};
272
Simon Goldschmidtceab2692018-11-14 21:05:12 +0100[diff] [blame]273static const struct socfpga_sdram_io_config io_config = {
Marek Vasut3bf92042015-08-02 19:00:23 +0200[diff] [blame]274 .delay_per_dchain_tap = IO_DELAY_PER_DCHAIN_TAP,
275 .delay_per_dqs_en_dchain_tap = IO_DELAY_PER_DQS_EN_DCHAIN_TAP,
276 .delay_per_opa_tap = IO_DELAY_PER_OPA_TAP,
277 .dll_chain_length = IO_DLL_CHAIN_LENGTH,
278 .dqdqs_out_phase_max = IO_DQDQS_OUT_PHASE_MAX,
279 .dqs_en_delay_max = IO_DQS_EN_DELAY_MAX,
280 .dqs_en_delay_offset = IO_DQS_EN_DELAY_OFFSET,
281 .dqs_en_phase_max = IO_DQS_EN_PHASE_MAX,
282 .dqs_in_delay_max = IO_DQS_IN_DELAY_MAX,
283 .dqs_in_reserve = IO_DQS_IN_RESERVE,
284 .dqs_out_reserve = IO_DQS_OUT_RESERVE,
285 .io_in_delay_max = IO_IO_IN_DELAY_MAX,
286 .io_out1_delay_max = IO_IO_OUT1_DELAY_MAX,
287 .io_out2_delay_max = IO_IO_OUT2_DELAY_MAX,
288 .shift_dqs_en_when_shift_dqs = IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS,
289};
290
Simon Goldschmidtceab2692018-11-14 21:05:12 +0100[diff] [blame]291static const struct socfpga_sdram_misc_config misc_config = {
Tom Rinidcdd3bd2022-10-28 20:27:14 -0400[diff] [blame]292#if (CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 1) /* DDR2 */
Marek Vasut6bccacf2019-10-18 00:22:31 +0200[diff] [blame]293 .afi_clk_freq = AFI_CLK_FREQ,
294#endif
Marek Vasutf00a6ea2015-08-02 19:18:47 +0200[diff] [blame]295 .afi_rate_ratio = AFI_RATE_RATIO,
296 .calib_lfifo_offset = CALIB_LFIFO_OFFSET,
297 .calib_vfifo_offset = CALIB_VFIFO_OFFSET,
298 .enable_super_quick_calibration = ENABLE_SUPER_QUICK_CALIBRATION,
299 .max_latency_count_width = MAX_LATENCY_COUNT_WIDTH,
300 .read_valid_fifo_size = READ_VALID_FIFO_SIZE,
301 .reg_file_init_seq_signature = REG_FILE_INIT_SEQ_SIGNATURE,
302 .tinit_cntr0_val = TINIT_CNTR0_VAL,
303 .tinit_cntr1_val = TINIT_CNTR1_VAL,
304 .tinit_cntr2_val = TINIT_CNTR2_VAL,
305 .treset_cntr0_val = TRESET_CNTR0_VAL,
306 .treset_cntr1_val = TRESET_CNTR1_VAL,
307 .treset_cntr2_val = TRESET_CNTR2_VAL,
308};
309
Marek Vasut32ada572015-08-01 21:35:18 +0200[diff] [blame]310const struct socfpga_sdram_config *socfpga_get_sdram_config(void)
311{
312 return &sdram_config;
313}
Marek Vasut3384e742015-08-02 17:15:19 +0200[diff] [blame]314
315void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem)
316{
317 *init = ac_rom_init;
318 *nelem = ARRAY_SIZE(ac_rom_init);
319}
320
321void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem)
322{
323 *init = inst_rom_init;
324 *nelem = ARRAY_SIZE(inst_rom_init);
325}
Marek Vasut39b620e2015-08-02 18:12:08 +0200[diff] [blame]326
327const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void)
328{
329 return &rw_mgr_config;
330}
Marek Vasut3bf92042015-08-02 19:00:23 +0200[diff] [blame]331
332const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config(void)
333{
334 return &io_config;
335}
Marek Vasutf00a6ea2015-08-02 19:18:47 +0200[diff] [blame]336
337const struct socfpga_sdram_misc_config *socfpga_get_sdram_misc_config(void)
338{
339 return &misc_config;
340}