Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2001 |
| 4 | * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com. |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | /* |
| 8 | * This provides a bit-banged interface to the ethernet MII management |
| 9 | * channel. |
| 10 | */ |
| 11 | |
| 12 | #include <common.h> |
Simon Glass | dbad346 | 2015-04-05 16:07:39 -0600 | [diff] [blame] | 13 | #include <dm.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 14 | #include <log.h> |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 15 | #include <miiphy.h> |
Andy Fleming | aecf6fc | 2011-04-08 02:10:27 -0500 | [diff] [blame] | 16 | #include <phy.h> |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 17 | #include <linux/delay.h> |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 18 | |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 19 | #include <asm/types.h> |
| 20 | #include <linux/list.h> |
| 21 | #include <malloc.h> |
| 22 | #include <net.h> |
| 23 | |
| 24 | /* local debug macro */ |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 25 | #undef MII_DEBUG |
| 26 | |
| 27 | #undef debug |
| 28 | #ifdef MII_DEBUG |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 29 | #define debug(fmt, args...) printf(fmt, ##args) |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 30 | #else |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 31 | #define debug(fmt, args...) |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 32 | #endif /* MII_DEBUG */ |
| 33 | |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 34 | static struct list_head mii_devs; |
| 35 | static struct mii_dev *current_mii; |
| 36 | |
Mike Frysinger | 24a9008 | 2010-07-27 18:35:09 -0400 | [diff] [blame] | 37 | /* |
| 38 | * Lookup the mii_dev struct by the registered device name. |
| 39 | */ |
Andy Fleming | aecf6fc | 2011-04-08 02:10:27 -0500 | [diff] [blame] | 40 | struct mii_dev *miiphy_get_dev_by_name(const char *devname) |
Mike Frysinger | 24a9008 | 2010-07-27 18:35:09 -0400 | [diff] [blame] | 41 | { |
| 42 | struct list_head *entry; |
| 43 | struct mii_dev *dev; |
| 44 | |
| 45 | if (!devname) { |
| 46 | printf("NULL device name!\n"); |
| 47 | return NULL; |
| 48 | } |
| 49 | |
| 50 | list_for_each(entry, &mii_devs) { |
| 51 | dev = list_entry(entry, struct mii_dev, link); |
| 52 | if (strcmp(dev->name, devname) == 0) |
| 53 | return dev; |
| 54 | } |
| 55 | |
Mike Frysinger | 24a9008 | 2010-07-27 18:35:09 -0400 | [diff] [blame] | 56 | return NULL; |
| 57 | } |
| 58 | |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 59 | /***************************************************************************** |
| 60 | * |
Marian Balakowicz | cbdd1c8 | 2005-11-30 18:06:04 +0100 | [diff] [blame] | 61 | * Initialize global data. Need to be called before any other miiphy routine. |
| 62 | */ |
Mike Frysinger | 5ff5fdb | 2010-07-27 18:35:08 -0400 | [diff] [blame] | 63 | void miiphy_init(void) |
Marian Balakowicz | cbdd1c8 | 2005-11-30 18:06:04 +0100 | [diff] [blame] | 64 | { |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 65 | INIT_LIST_HEAD(&mii_devs); |
Larry Johnson | 81b974b | 2007-10-31 11:21:29 -0500 | [diff] [blame] | 66 | current_mii = NULL; |
Marian Balakowicz | cbdd1c8 | 2005-11-30 18:06:04 +0100 | [diff] [blame] | 67 | } |
| 68 | |
Andy Fleming | aecf6fc | 2011-04-08 02:10:27 -0500 | [diff] [blame] | 69 | struct mii_dev *mdio_alloc(void) |
| 70 | { |
| 71 | struct mii_dev *bus; |
| 72 | |
| 73 | bus = malloc(sizeof(*bus)); |
| 74 | if (!bus) |
| 75 | return bus; |
| 76 | |
| 77 | memset(bus, 0, sizeof(*bus)); |
| 78 | |
| 79 | /* initalize mii_dev struct fields */ |
| 80 | INIT_LIST_HEAD(&bus->link); |
| 81 | |
| 82 | return bus; |
| 83 | } |
| 84 | |
Bin Meng | a961e1f | 2015-10-07 21:32:37 -0700 | [diff] [blame] | 85 | void mdio_free(struct mii_dev *bus) |
| 86 | { |
| 87 | free(bus); |
| 88 | } |
| 89 | |
Andy Fleming | aecf6fc | 2011-04-08 02:10:27 -0500 | [diff] [blame] | 90 | int mdio_register(struct mii_dev *bus) |
| 91 | { |
Peng Fan | cd41c21 | 2015-11-24 17:03:47 +0800 | [diff] [blame] | 92 | if (!bus || !bus->read || !bus->write) |
Andy Fleming | aecf6fc | 2011-04-08 02:10:27 -0500 | [diff] [blame] | 93 | return -1; |
| 94 | |
| 95 | /* check if we have unique name */ |
| 96 | if (miiphy_get_dev_by_name(bus->name)) { |
| 97 | printf("mdio_register: non unique device name '%s'\n", |
| 98 | bus->name); |
| 99 | return -1; |
| 100 | } |
| 101 | |
| 102 | /* add it to the list */ |
| 103 | list_add_tail(&bus->link, &mii_devs); |
| 104 | |
| 105 | if (!current_mii) |
| 106 | current_mii = bus; |
| 107 | |
| 108 | return 0; |
| 109 | } |
| 110 | |
Michal Simek | 1a548f5 | 2016-12-08 10:06:26 +0100 | [diff] [blame] | 111 | int mdio_register_seq(struct mii_dev *bus, int seq) |
| 112 | { |
| 113 | int ret; |
| 114 | |
| 115 | /* Setup a unique name for each mdio bus */ |
| 116 | ret = snprintf(bus->name, MDIO_NAME_LEN, "eth%d", seq); |
| 117 | if (ret < 0) |
| 118 | return ret; |
| 119 | |
| 120 | return mdio_register(bus); |
| 121 | } |
| 122 | |
Bin Meng | a961e1f | 2015-10-07 21:32:37 -0700 | [diff] [blame] | 123 | int mdio_unregister(struct mii_dev *bus) |
| 124 | { |
| 125 | if (!bus) |
| 126 | return 0; |
| 127 | |
| 128 | /* delete it from the list */ |
| 129 | list_del(&bus->link); |
| 130 | |
| 131 | if (current_mii == bus) |
| 132 | current_mii = NULL; |
| 133 | |
| 134 | return 0; |
| 135 | } |
| 136 | |
Andy Fleming | aecf6fc | 2011-04-08 02:10:27 -0500 | [diff] [blame] | 137 | void mdio_list_devices(void) |
| 138 | { |
| 139 | struct list_head *entry; |
| 140 | |
| 141 | list_for_each(entry, &mii_devs) { |
| 142 | int i; |
| 143 | struct mii_dev *bus = list_entry(entry, struct mii_dev, link); |
| 144 | |
| 145 | printf("%s:\n", bus->name); |
| 146 | |
| 147 | for (i = 0; i < PHY_MAX_ADDR; i++) { |
| 148 | struct phy_device *phydev = bus->phymap[i]; |
| 149 | |
| 150 | if (phydev) { |
Michal Simek | fca1e84 | 2016-11-16 08:41:01 +0100 | [diff] [blame] | 151 | printf("%x - %s", i, phydev->drv->name); |
Andy Fleming | aecf6fc | 2011-04-08 02:10:27 -0500 | [diff] [blame] | 152 | |
| 153 | if (phydev->dev) |
| 154 | printf(" <--> %s\n", phydev->dev->name); |
| 155 | else |
| 156 | printf("\n"); |
| 157 | } |
| 158 | } |
| 159 | } |
| 160 | } |
| 161 | |
Mike Frysinger | 5ff5fdb | 2010-07-27 18:35:08 -0400 | [diff] [blame] | 162 | int miiphy_set_current_dev(const char *devname) |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 163 | { |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 164 | struct mii_dev *dev; |
| 165 | |
Andy Fleming | aecf6fc | 2011-04-08 02:10:27 -0500 | [diff] [blame] | 166 | dev = miiphy_get_dev_by_name(devname); |
Mike Frysinger | 24a9008 | 2010-07-27 18:35:09 -0400 | [diff] [blame] | 167 | if (dev) { |
| 168 | current_mii = dev; |
| 169 | return 0; |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 170 | } |
| 171 | |
Andy Fleming | aecf6fc | 2011-04-08 02:10:27 -0500 | [diff] [blame] | 172 | printf("No such device: %s\n", devname); |
| 173 | |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 174 | return 1; |
| 175 | } |
| 176 | |
Andy Fleming | aecf6fc | 2011-04-08 02:10:27 -0500 | [diff] [blame] | 177 | struct mii_dev *mdio_get_current_dev(void) |
| 178 | { |
| 179 | return current_mii; |
| 180 | } |
| 181 | |
Pankaj Bansal | 7c18fe8 | 2018-09-18 15:46:48 +0530 | [diff] [blame] | 182 | struct list_head *mdio_get_list_head(void) |
| 183 | { |
| 184 | return &mii_devs; |
| 185 | } |
| 186 | |
Andy Fleming | aecf6fc | 2011-04-08 02:10:27 -0500 | [diff] [blame] | 187 | struct phy_device *mdio_phydev_for_ethname(const char *ethname) |
| 188 | { |
| 189 | struct list_head *entry; |
| 190 | struct mii_dev *bus; |
| 191 | |
| 192 | list_for_each(entry, &mii_devs) { |
| 193 | int i; |
| 194 | bus = list_entry(entry, struct mii_dev, link); |
| 195 | |
| 196 | for (i = 0; i < PHY_MAX_ADDR; i++) { |
| 197 | if (!bus->phymap[i] || !bus->phymap[i]->dev) |
| 198 | continue; |
| 199 | |
| 200 | if (strcmp(bus->phymap[i]->dev->name, ethname) == 0) |
| 201 | return bus->phymap[i]; |
| 202 | } |
| 203 | } |
| 204 | |
| 205 | printf("%s is not a known ethernet\n", ethname); |
| 206 | return NULL; |
| 207 | } |
| 208 | |
Mike Frysinger | 5ff5fdb | 2010-07-27 18:35:08 -0400 | [diff] [blame] | 209 | const char *miiphy_get_current_dev(void) |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 210 | { |
| 211 | if (current_mii) |
| 212 | return current_mii->name; |
| 213 | |
| 214 | return NULL; |
| 215 | } |
| 216 | |
Mike Frysinger | bd17e7a | 2010-07-27 18:35:10 -0400 | [diff] [blame] | 217 | static struct mii_dev *miiphy_get_active_dev(const char *devname) |
| 218 | { |
| 219 | /* If the current mii is the one we want, return it */ |
| 220 | if (current_mii) |
| 221 | if (strcmp(current_mii->name, devname) == 0) |
| 222 | return current_mii; |
| 223 | |
| 224 | /* Otherwise, set the active one to the one we want */ |
| 225 | if (miiphy_set_current_dev(devname)) |
| 226 | return NULL; |
| 227 | else |
| 228 | return current_mii; |
| 229 | } |
| 230 | |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 231 | /***************************************************************************** |
| 232 | * |
| 233 | * Read to variable <value> from the PHY attached to device <devname>, |
| 234 | * use PHY address <addr> and register <reg>. |
| 235 | * |
Andy Fleming | 896a717 | 2011-10-31 09:46:13 -0500 | [diff] [blame] | 236 | * This API is deprecated. Use phy_read on a phy_device found via phy_connect |
| 237 | * |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 238 | * Returns: |
| 239 | * 0 on success |
| 240 | */ |
Wolfgang Denk | 934fcb6 | 2011-12-07 08:35:14 +0100 | [diff] [blame] | 241 | int miiphy_read(const char *devname, unsigned char addr, unsigned char reg, |
Larry Johnson | 81b974b | 2007-10-31 11:21:29 -0500 | [diff] [blame] | 242 | unsigned short *value) |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 243 | { |
Andy Fleming | aecf6fc | 2011-04-08 02:10:27 -0500 | [diff] [blame] | 244 | struct mii_dev *bus; |
Anatolij Gustschin | 1bbce3a | 2011-04-30 02:17:44 +0000 | [diff] [blame] | 245 | int ret; |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 246 | |
Andy Fleming | aecf6fc | 2011-04-08 02:10:27 -0500 | [diff] [blame] | 247 | bus = miiphy_get_active_dev(devname); |
Anatolij Gustschin | 1bbce3a | 2011-04-30 02:17:44 +0000 | [diff] [blame] | 248 | if (!bus) |
Andy Fleming | aecf6fc | 2011-04-08 02:10:27 -0500 | [diff] [blame] | 249 | return 1; |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 250 | |
Anatolij Gustschin | 1bbce3a | 2011-04-30 02:17:44 +0000 | [diff] [blame] | 251 | ret = bus->read(bus, addr, MDIO_DEVAD_NONE, reg); |
| 252 | if (ret < 0) |
| 253 | return 1; |
| 254 | |
| 255 | *value = (unsigned short)ret; |
| 256 | return 0; |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 257 | } |
| 258 | |
| 259 | /***************************************************************************** |
| 260 | * |
| 261 | * Write <value> to the PHY attached to device <devname>, |
| 262 | * use PHY address <addr> and register <reg>. |
| 263 | * |
Andy Fleming | 896a717 | 2011-10-31 09:46:13 -0500 | [diff] [blame] | 264 | * This API is deprecated. Use phy_write on a phy_device found by phy_connect |
| 265 | * |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 266 | * Returns: |
| 267 | * 0 on success |
| 268 | */ |
Wolfgang Denk | 934fcb6 | 2011-12-07 08:35:14 +0100 | [diff] [blame] | 269 | int miiphy_write(const char *devname, unsigned char addr, unsigned char reg, |
Larry Johnson | 81b974b | 2007-10-31 11:21:29 -0500 | [diff] [blame] | 270 | unsigned short value) |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 271 | { |
Andy Fleming | aecf6fc | 2011-04-08 02:10:27 -0500 | [diff] [blame] | 272 | struct mii_dev *bus; |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 273 | |
Andy Fleming | aecf6fc | 2011-04-08 02:10:27 -0500 | [diff] [blame] | 274 | bus = miiphy_get_active_dev(devname); |
| 275 | if (bus) |
| 276 | return bus->write(bus, addr, MDIO_DEVAD_NONE, reg, value); |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 277 | |
Mike Frysinger | 24a9008 | 2010-07-27 18:35:09 -0400 | [diff] [blame] | 278 | return 1; |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 279 | } |
| 280 | |
| 281 | /***************************************************************************** |
| 282 | * |
| 283 | * Print out list of registered MII capable devices. |
| 284 | */ |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 285 | void miiphy_listdev(void) |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 286 | { |
| 287 | struct list_head *entry; |
| 288 | struct mii_dev *dev; |
| 289 | |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 290 | puts("MII devices: "); |
| 291 | list_for_each(entry, &mii_devs) { |
| 292 | dev = list_entry(entry, struct mii_dev, link); |
| 293 | printf("'%s' ", dev->name); |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 294 | } |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 295 | puts("\n"); |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 296 | |
| 297 | if (current_mii) |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 298 | printf("Current device: '%s'\n", current_mii->name); |
Marian Balakowicz | aab8c49 | 2005-10-28 22:30:33 +0200 | [diff] [blame] | 299 | } |
| 300 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 301 | /***************************************************************************** |
| 302 | * |
| 303 | * Read the OUI, manufacture's model number, and revision number. |
| 304 | * |
| 305 | * OUI: 22 bits (unsigned int) |
| 306 | * Model: 6 bits (unsigned char) |
| 307 | * Revision: 4 bits (unsigned char) |
| 308 | * |
Andy Fleming | 896a717 | 2011-10-31 09:46:13 -0500 | [diff] [blame] | 309 | * This API is deprecated. |
| 310 | * |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 311 | * Returns: |
| 312 | * 0 on success |
| 313 | */ |
Mike Frysinger | 5ff5fdb | 2010-07-27 18:35:08 -0400 | [diff] [blame] | 314 | int miiphy_info(const char *devname, unsigned char addr, unsigned int *oui, |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 315 | unsigned char *model, unsigned char *rev) |
| 316 | { |
| 317 | unsigned int reg = 0; |
wdenk | f4cec3f | 2003-12-06 23:20:41 +0000 | [diff] [blame] | 318 | unsigned short tmp; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 319 | |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 320 | if (miiphy_read(devname, addr, MII_PHYSID2, &tmp) != 0) { |
| 321 | debug("PHY ID register 2 read failed\n"); |
| 322 | return -1; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 323 | } |
wdenk | f4cec3f | 2003-12-06 23:20:41 +0000 | [diff] [blame] | 324 | reg = tmp; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 325 | |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 326 | debug("MII_PHYSID2 @ 0x%x = 0x%04x\n", addr, reg); |
Shinya Kuribayashi | 49e42af | 2008-01-19 10:25:59 +0900 | [diff] [blame] | 327 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 328 | if (reg == 0xFFFF) { |
| 329 | /* No physical device present at this address */ |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 330 | return -1; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 331 | } |
| 332 | |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 333 | if (miiphy_read(devname, addr, MII_PHYSID1, &tmp) != 0) { |
| 334 | debug("PHY ID register 1 read failed\n"); |
| 335 | return -1; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 336 | } |
wdenk | f4cec3f | 2003-12-06 23:20:41 +0000 | [diff] [blame] | 337 | reg |= tmp << 16; |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 338 | debug("PHY_PHYIDR[1,2] @ 0x%x = 0x%08x\n", addr, reg); |
Shinya Kuribayashi | 49e42af | 2008-01-19 10:25:59 +0900 | [diff] [blame] | 339 | |
Larry Johnson | 81b974b | 2007-10-31 11:21:29 -0500 | [diff] [blame] | 340 | *oui = (reg >> 10); |
| 341 | *model = (unsigned char)((reg >> 4) & 0x0000003F); |
| 342 | *rev = (unsigned char)(reg & 0x0000000F); |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 343 | return 0; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 344 | } |
| 345 | |
Andy Fleming | aecf6fc | 2011-04-08 02:10:27 -0500 | [diff] [blame] | 346 | #ifndef CONFIG_PHYLIB |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 347 | /***************************************************************************** |
| 348 | * |
| 349 | * Reset the PHY. |
Andy Fleming | 896a717 | 2011-10-31 09:46:13 -0500 | [diff] [blame] | 350 | * |
| 351 | * This API is deprecated. Use PHYLIB. |
| 352 | * |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 353 | * Returns: |
| 354 | * 0 on success |
| 355 | */ |
Mike Frysinger | 5ff5fdb | 2010-07-27 18:35:08 -0400 | [diff] [blame] | 356 | int miiphy_reset(const char *devname, unsigned char addr) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 357 | { |
| 358 | unsigned short reg; |
Stefan Roese | 2e53636 | 2010-02-02 13:43:48 +0100 | [diff] [blame] | 359 | int timeout = 500; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 360 | |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 361 | if (miiphy_read(devname, addr, MII_BMCR, ®) != 0) { |
| 362 | debug("PHY status read failed\n"); |
| 363 | return -1; |
Wolfgang Denk | 8ff63c2 | 2005-08-12 23:15:53 +0200 | [diff] [blame] | 364 | } |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 365 | if (miiphy_write(devname, addr, MII_BMCR, reg | BMCR_RESET) != 0) { |
| 366 | debug("PHY reset failed\n"); |
| 367 | return -1; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 368 | } |
wdenk | 2cefd15 | 2004-02-08 22:55:38 +0000 | [diff] [blame] | 369 | #ifdef CONFIG_PHY_RESET_DELAY |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 370 | udelay(CONFIG_PHY_RESET_DELAY); /* Intel LXT971A needs this */ |
wdenk | 2cefd15 | 2004-02-08 22:55:38 +0000 | [diff] [blame] | 371 | #endif |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 372 | /* |
| 373 | * Poll the control register for the reset bit to go to 0 (it is |
| 374 | * auto-clearing). This should happen within 0.5 seconds per the |
| 375 | * IEEE spec. |
| 376 | */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 377 | reg = 0x8000; |
Stefan Roese | 2e53636 | 2010-02-02 13:43:48 +0100 | [diff] [blame] | 378 | while (((reg & 0x8000) != 0) && timeout--) { |
Mike Frysinger | d63ee71 | 2010-12-23 15:40:12 -0500 | [diff] [blame] | 379 | if (miiphy_read(devname, addr, MII_BMCR, ®) != 0) { |
Stefan Roese | 2e53636 | 2010-02-02 13:43:48 +0100 | [diff] [blame] | 380 | debug("PHY status read failed\n"); |
| 381 | return -1; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 382 | } |
Stefan Roese | 2e53636 | 2010-02-02 13:43:48 +0100 | [diff] [blame] | 383 | udelay(1000); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 384 | } |
| 385 | if ((reg & 0x8000) == 0) { |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 386 | return 0; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 387 | } else { |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 388 | puts("PHY reset timed out\n"); |
| 389 | return -1; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 390 | } |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 391 | return 0; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 392 | } |
Andy Fleming | aecf6fc | 2011-04-08 02:10:27 -0500 | [diff] [blame] | 393 | #endif /* !PHYLIB */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 394 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 395 | /***************************************************************************** |
| 396 | * |
Larry Johnson | 966a80b | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 397 | * Determine the ethernet speed (10/100/1000). Return 10 on error. |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 398 | */ |
Mike Frysinger | 5ff5fdb | 2010-07-27 18:35:08 -0400 | [diff] [blame] | 399 | int miiphy_speed(const char *devname, unsigned char addr) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 400 | { |
Dongpo Li | ce29024 | 2016-08-22 21:03:29 +0800 | [diff] [blame] | 401 | u16 bmcr, anlpar, adv; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 402 | |
wdenk | eec9a3d | 2004-03-23 23:20:24 +0000 | [diff] [blame] | 403 | #if defined(CONFIG_PHY_GIGE) |
Larry Johnson | 966a80b | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 404 | u16 btsr; |
| 405 | |
| 406 | /* |
| 407 | * Check for 1000BASE-X. If it is supported, then assume that the speed |
| 408 | * is 1000. |
| 409 | */ |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 410 | if (miiphy_is_1000base_x(devname, addr)) |
Larry Johnson | 966a80b | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 411 | return _1000BASET; |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 412 | |
Larry Johnson | 966a80b | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 413 | /* |
| 414 | * No 1000BASE-X, so assume 1000BASE-T/100BASE-TX/10BASE-T register set. |
| 415 | */ |
| 416 | /* Check for 1000BASE-T. */ |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 417 | if (miiphy_read(devname, addr, MII_STAT1000, &btsr)) { |
| 418 | printf("PHY 1000BT status"); |
Larry Johnson | 966a80b | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 419 | goto miiphy_read_failed; |
| 420 | } |
| 421 | if (btsr != 0xFFFF && |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 422 | (btsr & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD))) |
Larry Johnson | 966a80b | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 423 | return _1000BASET; |
wdenk | eec9a3d | 2004-03-23 23:20:24 +0000 | [diff] [blame] | 424 | #endif /* CONFIG_PHY_GIGE */ |
wdenk | ed2ac4b | 2004-03-14 18:23:55 +0000 | [diff] [blame] | 425 | |
wdenk | e3a0680 | 2004-06-06 23:13:55 +0000 | [diff] [blame] | 426 | /* Check Basic Management Control Register first. */ |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 427 | if (miiphy_read(devname, addr, MII_BMCR, &bmcr)) { |
| 428 | printf("PHY speed"); |
Larry Johnson | 966a80b | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 429 | goto miiphy_read_failed; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 430 | } |
wdenk | e3a0680 | 2004-06-06 23:13:55 +0000 | [diff] [blame] | 431 | /* Check if auto-negotiation is on. */ |
Mike Frysinger | d63ee71 | 2010-12-23 15:40:12 -0500 | [diff] [blame] | 432 | if (bmcr & BMCR_ANENABLE) { |
wdenk | e3a0680 | 2004-06-06 23:13:55 +0000 | [diff] [blame] | 433 | /* Get auto-negotiation results. */ |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 434 | if (miiphy_read(devname, addr, MII_LPA, &anlpar)) { |
| 435 | printf("PHY AN speed"); |
Larry Johnson | 966a80b | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 436 | goto miiphy_read_failed; |
wdenk | e3a0680 | 2004-06-06 23:13:55 +0000 | [diff] [blame] | 437 | } |
Dongpo Li | ce29024 | 2016-08-22 21:03:29 +0800 | [diff] [blame] | 438 | |
| 439 | if (miiphy_read(devname, addr, MII_ADVERTISE, &adv)) { |
| 440 | puts("PHY AN adv speed"); |
| 441 | goto miiphy_read_failed; |
| 442 | } |
| 443 | return ((anlpar & adv) & LPA_100) ? _100BASET : _10BASET; |
wdenk | e3a0680 | 2004-06-06 23:13:55 +0000 | [diff] [blame] | 444 | } |
| 445 | /* Get speed from basic control settings. */ |
Mike Frysinger | d63ee71 | 2010-12-23 15:40:12 -0500 | [diff] [blame] | 446 | return (bmcr & BMCR_SPEED100) ? _100BASET : _10BASET; |
wdenk | e3a0680 | 2004-06-06 23:13:55 +0000 | [diff] [blame] | 447 | |
Michael Zaidman | 6dbca5f | 2010-02-28 16:28:25 +0200 | [diff] [blame] | 448 | miiphy_read_failed: |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 449 | printf(" read failed, assuming 10BASE-T\n"); |
Larry Johnson | 966a80b | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 450 | return _10BASET; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 451 | } |
| 452 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 453 | /***************************************************************************** |
| 454 | * |
Larry Johnson | 966a80b | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 455 | * Determine full/half duplex. Return half on error. |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 456 | */ |
Mike Frysinger | 5ff5fdb | 2010-07-27 18:35:08 -0400 | [diff] [blame] | 457 | int miiphy_duplex(const char *devname, unsigned char addr) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 458 | { |
Dongpo Li | ce29024 | 2016-08-22 21:03:29 +0800 | [diff] [blame] | 459 | u16 bmcr, anlpar, adv; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 460 | |
wdenk | eec9a3d | 2004-03-23 23:20:24 +0000 | [diff] [blame] | 461 | #if defined(CONFIG_PHY_GIGE) |
Larry Johnson | 966a80b | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 462 | u16 btsr; |
| 463 | |
| 464 | /* Check for 1000BASE-X. */ |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 465 | if (miiphy_is_1000base_x(devname, addr)) { |
Larry Johnson | 966a80b | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 466 | /* 1000BASE-X */ |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 467 | if (miiphy_read(devname, addr, MII_LPA, &anlpar)) { |
| 468 | printf("1000BASE-X PHY AN duplex"); |
Larry Johnson | 966a80b | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 469 | goto miiphy_read_failed; |
wdenk | ed2ac4b | 2004-03-14 18:23:55 +0000 | [diff] [blame] | 470 | } |
| 471 | } |
Larry Johnson | 966a80b | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 472 | /* |
| 473 | * No 1000BASE-X, so assume 1000BASE-T/100BASE-TX/10BASE-T register set. |
| 474 | */ |
| 475 | /* Check for 1000BASE-T. */ |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 476 | if (miiphy_read(devname, addr, MII_STAT1000, &btsr)) { |
| 477 | printf("PHY 1000BT status"); |
Larry Johnson | 966a80b | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 478 | goto miiphy_read_failed; |
| 479 | } |
| 480 | if (btsr != 0xFFFF) { |
| 481 | if (btsr & PHY_1000BTSR_1000FD) { |
| 482 | return FULL; |
| 483 | } else if (btsr & PHY_1000BTSR_1000HD) { |
| 484 | return HALF; |
| 485 | } |
| 486 | } |
wdenk | eec9a3d | 2004-03-23 23:20:24 +0000 | [diff] [blame] | 487 | #endif /* CONFIG_PHY_GIGE */ |
wdenk | ed2ac4b | 2004-03-14 18:23:55 +0000 | [diff] [blame] | 488 | |
wdenk | e3a0680 | 2004-06-06 23:13:55 +0000 | [diff] [blame] | 489 | /* Check Basic Management Control Register first. */ |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 490 | if (miiphy_read(devname, addr, MII_BMCR, &bmcr)) { |
| 491 | puts("PHY duplex"); |
Larry Johnson | 966a80b | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 492 | goto miiphy_read_failed; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 493 | } |
wdenk | e3a0680 | 2004-06-06 23:13:55 +0000 | [diff] [blame] | 494 | /* Check if auto-negotiation is on. */ |
Mike Frysinger | d63ee71 | 2010-12-23 15:40:12 -0500 | [diff] [blame] | 495 | if (bmcr & BMCR_ANENABLE) { |
wdenk | e3a0680 | 2004-06-06 23:13:55 +0000 | [diff] [blame] | 496 | /* Get auto-negotiation results. */ |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 497 | if (miiphy_read(devname, addr, MII_LPA, &anlpar)) { |
| 498 | puts("PHY AN duplex"); |
Larry Johnson | 966a80b | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 499 | goto miiphy_read_failed; |
wdenk | e3a0680 | 2004-06-06 23:13:55 +0000 | [diff] [blame] | 500 | } |
Dongpo Li | ce29024 | 2016-08-22 21:03:29 +0800 | [diff] [blame] | 501 | |
| 502 | if (miiphy_read(devname, addr, MII_ADVERTISE, &adv)) { |
| 503 | puts("PHY AN adv duplex"); |
| 504 | goto miiphy_read_failed; |
| 505 | } |
| 506 | return ((anlpar & adv) & (LPA_10FULL | LPA_100FULL)) ? |
Larry Johnson | 966a80b | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 507 | FULL : HALF; |
wdenk | e3a0680 | 2004-06-06 23:13:55 +0000 | [diff] [blame] | 508 | } |
| 509 | /* Get speed from basic control settings. */ |
Mike Frysinger | d63ee71 | 2010-12-23 15:40:12 -0500 | [diff] [blame] | 510 | return (bmcr & BMCR_FULLDPLX) ? FULL : HALF; |
Larry Johnson | 966a80b | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 511 | |
Michael Zaidman | 6dbca5f | 2010-02-28 16:28:25 +0200 | [diff] [blame] | 512 | miiphy_read_failed: |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 513 | printf(" read failed, assuming half duplex\n"); |
Larry Johnson | 966a80b | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 514 | return HALF; |
| 515 | } |
wdenk | e3a0680 | 2004-06-06 23:13:55 +0000 | [diff] [blame] | 516 | |
Larry Johnson | 966a80b | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 517 | /***************************************************************************** |
| 518 | * |
| 519 | * Return 1 if PHY supports 1000BASE-X, 0 if PHY supports 10BASE-T/100BASE-TX/ |
| 520 | * 1000BASE-T, or on error. |
| 521 | */ |
Mike Frysinger | 5ff5fdb | 2010-07-27 18:35:08 -0400 | [diff] [blame] | 522 | int miiphy_is_1000base_x(const char *devname, unsigned char addr) |
Larry Johnson | 966a80b | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 523 | { |
| 524 | #if defined(CONFIG_PHY_GIGE) |
| 525 | u16 exsr; |
| 526 | |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 527 | if (miiphy_read(devname, addr, MII_ESTATUS, &exsr)) { |
| 528 | printf("PHY extended status read failed, assuming no " |
Larry Johnson | 966a80b | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 529 | "1000BASE-X\n"); |
| 530 | return 0; |
| 531 | } |
Mike Frysinger | d63ee71 | 2010-12-23 15:40:12 -0500 | [diff] [blame] | 532 | return 0 != (exsr & (ESTATUS_1000XF | ESTATUS_1000XH)); |
Larry Johnson | 966a80b | 2007-11-01 08:46:50 -0500 | [diff] [blame] | 533 | #else |
| 534 | return 0; |
| 535 | #endif |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 536 | } |
| 537 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 538 | #ifdef CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
wdenk | 49c3f67 | 2003-10-08 22:33:00 +0000 | [diff] [blame] | 539 | /***************************************************************************** |
| 540 | * |
| 541 | * Determine link status |
| 542 | */ |
Mike Frysinger | 5ff5fdb | 2010-07-27 18:35:08 -0400 | [diff] [blame] | 543 | int miiphy_link(const char *devname, unsigned char addr) |
wdenk | 49c3f67 | 2003-10-08 22:33:00 +0000 | [diff] [blame] | 544 | { |
| 545 | unsigned short reg; |
| 546 | |
wdenk | 145d2c1 | 2004-04-15 21:48:45 +0000 | [diff] [blame] | 547 | /* dummy read; needed to latch some phys */ |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 548 | (void)miiphy_read(devname, addr, MII_BMSR, ®); |
| 549 | if (miiphy_read(devname, addr, MII_BMSR, ®)) { |
| 550 | puts("MII_BMSR read failed, assuming no link\n"); |
| 551 | return 0; |
wdenk | 49c3f67 | 2003-10-08 22:33:00 +0000 | [diff] [blame] | 552 | } |
| 553 | |
| 554 | /* Determine if a link is active */ |
Mike Frysinger | d63ee71 | 2010-12-23 15:40:12 -0500 | [diff] [blame] | 555 | if ((reg & BMSR_LSTATUS) != 0) { |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 556 | return 1; |
wdenk | 49c3f67 | 2003-10-08 22:33:00 +0000 | [diff] [blame] | 557 | } else { |
Andy Fleming | aea0c3e | 2011-04-07 14:38:35 -0500 | [diff] [blame] | 558 | return 0; |
wdenk | 49c3f67 | 2003-10-08 22:33:00 +0000 | [diff] [blame] | 559 | } |
| 560 | } |
| 561 | #endif |