blob: e055c08fbd6aef22e907693b00952dd6657674b7 [file] [log] [blame]
wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2001
3 * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * This provides a bit-banged interface to the ethernet MII management
26 * channel.
27 */
28
29#include <common.h>
30#include <miiphy.h>
31
Marian Balakowiczaab8c492005-10-28 22:30:33 +020032#include <asm/types.h>
33#include <linux/list.h>
34#include <malloc.h>
35#include <net.h>
36
37/* local debug macro */
Marian Balakowiczaab8c492005-10-28 22:30:33 +020038#undef MII_DEBUG
39
40#undef debug
41#ifdef MII_DEBUG
42#define debug(fmt,args...) printf (fmt ,##args)
43#else
44#define debug(fmt,args...)
45#endif /* MII_DEBUG */
46
47struct mii_dev {
48 struct list_head link;
Mike Frysinger5ff5fdb2010-07-27 18:35:08 -040049 const char *name;
50 int (*read) (const char *devname, unsigned char addr,
Larry Johnson81b974b2007-10-31 11:21:29 -050051 unsigned char reg, unsigned short *value);
Mike Frysinger5ff5fdb2010-07-27 18:35:08 -040052 int (*write) (const char *devname, unsigned char addr,
Larry Johnson81b974b2007-10-31 11:21:29 -050053 unsigned char reg, unsigned short value);
Marian Balakowiczaab8c492005-10-28 22:30:33 +020054};
55
56static struct list_head mii_devs;
57static struct mii_dev *current_mii;
58
Mike Frysinger24a90082010-07-27 18:35:09 -040059/*
60 * Lookup the mii_dev struct by the registered device name.
61 */
62static struct mii_dev *miiphy_get_dev_by_name(const char *devname, int quiet)
63{
64 struct list_head *entry;
65 struct mii_dev *dev;
66
67 if (!devname) {
68 printf("NULL device name!\n");
69 return NULL;
70 }
71
72 list_for_each(entry, &mii_devs) {
73 dev = list_entry(entry, struct mii_dev, link);
74 if (strcmp(dev->name, devname) == 0)
75 return dev;
76 }
77
78 if (!quiet)
79 printf("No such device: %s\n", devname);
80 return NULL;
81}
82
Marian Balakowiczaab8c492005-10-28 22:30:33 +020083/*****************************************************************************
84 *
Marian Balakowiczcbdd1c82005-11-30 18:06:04 +010085 * Initialize global data. Need to be called before any other miiphy routine.
86 */
Mike Frysinger5ff5fdb2010-07-27 18:35:08 -040087void miiphy_init(void)
Marian Balakowiczcbdd1c82005-11-30 18:06:04 +010088{
Larry Johnson81b974b2007-10-31 11:21:29 -050089 INIT_LIST_HEAD (&mii_devs);
90 current_mii = NULL;
Marian Balakowiczcbdd1c82005-11-30 18:06:04 +010091}
92
93/*****************************************************************************
94 *
Marian Balakowiczaab8c492005-10-28 22:30:33 +020095 * Register read and write MII access routines for the device <name>.
96 */
Mike Frysinger5ff5fdb2010-07-27 18:35:08 -040097void miiphy_register(const char *name,
98 int (*read) (const char *devname, unsigned char addr,
Larry Johnson81b974b2007-10-31 11:21:29 -050099 unsigned char reg, unsigned short *value),
Mike Frysinger5ff5fdb2010-07-27 18:35:08 -0400100 int (*write) (const char *devname, unsigned char addr,
Larry Johnson81b974b2007-10-31 11:21:29 -0500101 unsigned char reg, unsigned short value))
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200102{
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200103 struct mii_dev *new_dev;
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200104 unsigned int name_len;
Mike Frysinger5ff5fdb2010-07-27 18:35:08 -0400105 char *new_name;
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200106
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200107 /* check if we have unique name */
Mike Frysinger24a90082010-07-27 18:35:09 -0400108 new_dev = miiphy_get_dev_by_name(name, 1);
109 if (new_dev) {
110 printf("miiphy_register: non unique device name '%s'\n", name);
111 return;
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200112 }
113
114 /* allocate memory */
Larry Johnson81b974b2007-10-31 11:21:29 -0500115 name_len = strlen (name);
116 new_dev =
117 (struct mii_dev *)malloc (sizeof (struct mii_dev) + name_len + 1);
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200118
Larry Johnson81b974b2007-10-31 11:21:29 -0500119 if (new_dev == NULL) {
120 printf ("miiphy_register: cannot allocate memory for '%s'\n",
121 name);
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200122 return;
123 }
Larry Johnson81b974b2007-10-31 11:21:29 -0500124 memset (new_dev, 0, sizeof (struct mii_dev) + name_len);
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200125
126 /* initalize mii_dev struct fields */
Larry Johnson81b974b2007-10-31 11:21:29 -0500127 INIT_LIST_HEAD (&new_dev->link);
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200128 new_dev->read = read;
129 new_dev->write = write;
Mike Frysinger5ff5fdb2010-07-27 18:35:08 -0400130 new_dev->name = new_name = (char *)(new_dev + 1);
131 strncpy (new_name, name, name_len);
132 new_name[name_len] = '\0';
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200133
Larry Johnson81b974b2007-10-31 11:21:29 -0500134 debug ("miiphy_register: added '%s', read=0x%08lx, write=0x%08lx\n",
135 new_dev->name, new_dev->read, new_dev->write);
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200136
137 /* add it to the list */
Larry Johnson81b974b2007-10-31 11:21:29 -0500138 list_add_tail (&new_dev->link, &mii_devs);
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200139
140 if (!current_mii)
141 current_mii = new_dev;
142}
143
Mike Frysinger5ff5fdb2010-07-27 18:35:08 -0400144int miiphy_set_current_dev(const char *devname)
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200145{
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200146 struct mii_dev *dev;
147
Mike Frysinger24a90082010-07-27 18:35:09 -0400148 dev = miiphy_get_dev_by_name(devname, 0);
149 if (dev) {
150 current_mii = dev;
151 return 0;
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200152 }
153
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200154 return 1;
155}
156
Mike Frysinger5ff5fdb2010-07-27 18:35:08 -0400157const char *miiphy_get_current_dev(void)
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200158{
159 if (current_mii)
160 return current_mii->name;
161
162 return NULL;
163}
164
165/*****************************************************************************
166 *
167 * Read to variable <value> from the PHY attached to device <devname>,
168 * use PHY address <addr> and register <reg>.
169 *
170 * Returns:
171 * 0 on success
172 */
Mike Frysinger5ff5fdb2010-07-27 18:35:08 -0400173int miiphy_read(const char *devname, unsigned char addr, unsigned char reg,
Larry Johnson81b974b2007-10-31 11:21:29 -0500174 unsigned short *value)
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200175{
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200176 struct mii_dev *dev;
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200177
Mike Frysinger24a90082010-07-27 18:35:09 -0400178 dev = miiphy_get_dev_by_name(devname, 0);
179 if (dev)
180 return dev->read(devname, addr, reg, value);
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200181
Mike Frysinger24a90082010-07-27 18:35:09 -0400182 return 1;
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200183}
184
185/*****************************************************************************
186 *
187 * Write <value> to the PHY attached to device <devname>,
188 * use PHY address <addr> and register <reg>.
189 *
190 * Returns:
191 * 0 on success
192 */
Mike Frysinger5ff5fdb2010-07-27 18:35:08 -0400193int miiphy_write(const char *devname, unsigned char addr, unsigned char reg,
Larry Johnson81b974b2007-10-31 11:21:29 -0500194 unsigned short value)
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200195{
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200196 struct mii_dev *dev;
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200197
Mike Frysinger24a90082010-07-27 18:35:09 -0400198 dev = miiphy_get_dev_by_name(devname, 0);
199 if (dev)
200 return dev->write(devname, addr, reg, value);
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200201
Mike Frysinger24a90082010-07-27 18:35:09 -0400202 return 1;
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200203}
204
205/*****************************************************************************
206 *
207 * Print out list of registered MII capable devices.
208 */
Larry Johnson81b974b2007-10-31 11:21:29 -0500209void miiphy_listdev (void)
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200210{
211 struct list_head *entry;
212 struct mii_dev *dev;
213
Larry Johnson81b974b2007-10-31 11:21:29 -0500214 puts ("MII devices: ");
215 list_for_each (entry, &mii_devs) {
216 dev = list_entry (entry, struct mii_dev, link);
217 printf ("'%s' ", dev->name);
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200218 }
Larry Johnson81b974b2007-10-31 11:21:29 -0500219 puts ("\n");
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200220
221 if (current_mii)
Larry Johnson81b974b2007-10-31 11:21:29 -0500222 printf ("Current device: '%s'\n", current_mii->name);
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200223}
224
wdenkc6097192002-11-03 00:24:07 +0000225/*****************************************************************************
226 *
227 * Read the OUI, manufacture's model number, and revision number.
228 *
229 * OUI: 22 bits (unsigned int)
230 * Model: 6 bits (unsigned char)
231 * Revision: 4 bits (unsigned char)
232 *
233 * Returns:
234 * 0 on success
235 */
Mike Frysinger5ff5fdb2010-07-27 18:35:08 -0400236int miiphy_info(const char *devname, unsigned char addr, unsigned int *oui,
wdenkc6097192002-11-03 00:24:07 +0000237 unsigned char *model, unsigned char *rev)
238{
239 unsigned int reg = 0;
wdenkf4cec3f2003-12-06 23:20:41 +0000240 unsigned short tmp;
wdenkc6097192002-11-03 00:24:07 +0000241
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200242 if (miiphy_read (devname, addr, PHY_PHYIDR2, &tmp) != 0) {
Shinya Kuribayashi49e42af2008-01-19 10:25:59 +0900243 debug ("PHY ID register 2 read failed\n");
wdenkc6097192002-11-03 00:24:07 +0000244 return (-1);
245 }
wdenkf4cec3f2003-12-06 23:20:41 +0000246 reg = tmp;
wdenkc6097192002-11-03 00:24:07 +0000247
Shinya Kuribayashi49e42af2008-01-19 10:25:59 +0900248 debug ("PHY_PHYIDR2 @ 0x%x = 0x%04x\n", addr, reg);
249
wdenkc6097192002-11-03 00:24:07 +0000250 if (reg == 0xFFFF) {
251 /* No physical device present at this address */
252 return (-1);
253 }
254
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200255 if (miiphy_read (devname, addr, PHY_PHYIDR1, &tmp) != 0) {
Shinya Kuribayashi49e42af2008-01-19 10:25:59 +0900256 debug ("PHY ID register 1 read failed\n");
wdenkc6097192002-11-03 00:24:07 +0000257 return (-1);
258 }
wdenkf4cec3f2003-12-06 23:20:41 +0000259 reg |= tmp << 16;
Shinya Kuribayashi49e42af2008-01-19 10:25:59 +0900260 debug ("PHY_PHYIDR[1,2] @ 0x%x = 0x%08x\n", addr, reg);
261
Larry Johnson81b974b2007-10-31 11:21:29 -0500262 *oui = (reg >> 10);
263 *model = (unsigned char)((reg >> 4) & 0x0000003F);
264 *rev = (unsigned char)(reg & 0x0000000F);
wdenkc6097192002-11-03 00:24:07 +0000265 return (0);
266}
267
wdenkc6097192002-11-03 00:24:07 +0000268/*****************************************************************************
269 *
270 * Reset the PHY.
271 * Returns:
272 * 0 on success
273 */
Mike Frysinger5ff5fdb2010-07-27 18:35:08 -0400274int miiphy_reset(const char *devname, unsigned char addr)
wdenkc6097192002-11-03 00:24:07 +0000275{
276 unsigned short reg;
Stefan Roese2e536362010-02-02 13:43:48 +0100277 int timeout = 500;
wdenkc6097192002-11-03 00:24:07 +0000278
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200279 if (miiphy_read (devname, addr, PHY_BMCR, &reg) != 0) {
Shinya Kuribayashi49e42af2008-01-19 10:25:59 +0900280 debug ("PHY status read failed\n");
Wolfgang Denk8ff63c22005-08-12 23:15:53 +0200281 return (-1);
282 }
Niklaus Giger23f55e82009-09-23 08:12:14 +0200283 if (miiphy_write (devname, addr, PHY_BMCR, reg | PHY_BMCR_RESET) != 0) {
Shinya Kuribayashi49e42af2008-01-19 10:25:59 +0900284 debug ("PHY reset failed\n");
wdenkc6097192002-11-03 00:24:07 +0000285 return (-1);
286 }
wdenk2cefd152004-02-08 22:55:38 +0000287#ifdef CONFIG_PHY_RESET_DELAY
288 udelay (CONFIG_PHY_RESET_DELAY); /* Intel LXT971A needs this */
289#endif
wdenkc6097192002-11-03 00:24:07 +0000290 /*
291 * Poll the control register for the reset bit to go to 0 (it is
292 * auto-clearing). This should happen within 0.5 seconds per the
293 * IEEE spec.
294 */
wdenkc6097192002-11-03 00:24:07 +0000295 reg = 0x8000;
Stefan Roese2e536362010-02-02 13:43:48 +0100296 while (((reg & 0x8000) != 0) && timeout--) {
297 if (miiphy_read(devname, addr, PHY_BMCR, &reg) != 0) {
298 debug("PHY status read failed\n");
299 return -1;
wdenkc6097192002-11-03 00:24:07 +0000300 }
Stefan Roese2e536362010-02-02 13:43:48 +0100301 udelay(1000);
wdenkc6097192002-11-03 00:24:07 +0000302 }
303 if ((reg & 0x8000) == 0) {
304 return (0);
305 } else {
wdenk42c05472004-03-23 22:14:11 +0000306 puts ("PHY reset timed out\n");
wdenkc6097192002-11-03 00:24:07 +0000307 return (-1);
308 }
309 return (0);
310}
311
wdenkc6097192002-11-03 00:24:07 +0000312/*****************************************************************************
313 *
Larry Johnson966a80b2007-11-01 08:46:50 -0500314 * Determine the ethernet speed (10/100/1000). Return 10 on error.
wdenkc6097192002-11-03 00:24:07 +0000315 */
Mike Frysinger5ff5fdb2010-07-27 18:35:08 -0400316int miiphy_speed(const char *devname, unsigned char addr)
wdenkc6097192002-11-03 00:24:07 +0000317{
Larry Johnson966a80b2007-11-01 08:46:50 -0500318 u16 bmcr, anlpar;
wdenkc6097192002-11-03 00:24:07 +0000319
wdenkeec9a3d2004-03-23 23:20:24 +0000320#if defined(CONFIG_PHY_GIGE)
Larry Johnson966a80b2007-11-01 08:46:50 -0500321 u16 btsr;
322
323 /*
324 * Check for 1000BASE-X. If it is supported, then assume that the speed
325 * is 1000.
326 */
327 if (miiphy_is_1000base_x (devname, addr)) {
328 return _1000BASET;
329 }
330 /*
331 * No 1000BASE-X, so assume 1000BASE-T/100BASE-TX/10BASE-T register set.
332 */
333 /* Check for 1000BASE-T. */
334 if (miiphy_read (devname, addr, PHY_1000BTSR, &btsr)) {
335 printf ("PHY 1000BT status");
336 goto miiphy_read_failed;
337 }
338 if (btsr != 0xFFFF &&
339 (btsr & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD))) {
340 return _1000BASET;
wdenked2ac4b2004-03-14 18:23:55 +0000341 }
wdenkeec9a3d2004-03-23 23:20:24 +0000342#endif /* CONFIG_PHY_GIGE */
wdenked2ac4b2004-03-14 18:23:55 +0000343
wdenke3a06802004-06-06 23:13:55 +0000344 /* Check Basic Management Control Register first. */
Larry Johnson966a80b2007-11-01 08:46:50 -0500345 if (miiphy_read (devname, addr, PHY_BMCR, &bmcr)) {
346 printf ("PHY speed");
347 goto miiphy_read_failed;
wdenkc6097192002-11-03 00:24:07 +0000348 }
wdenke3a06802004-06-06 23:13:55 +0000349 /* Check if auto-negotiation is on. */
Larry Johnson966a80b2007-11-01 08:46:50 -0500350 if (bmcr & PHY_BMCR_AUTON) {
wdenke3a06802004-06-06 23:13:55 +0000351 /* Get auto-negotiation results. */
Larry Johnson966a80b2007-11-01 08:46:50 -0500352 if (miiphy_read (devname, addr, PHY_ANLPAR, &anlpar)) {
353 printf ("PHY AN speed");
354 goto miiphy_read_failed;
wdenke3a06802004-06-06 23:13:55 +0000355 }
Larry Johnson966a80b2007-11-01 08:46:50 -0500356 return (anlpar & PHY_ANLPAR_100) ? _100BASET : _10BASET;
wdenke3a06802004-06-06 23:13:55 +0000357 }
358 /* Get speed from basic control settings. */
Larry Johnson966a80b2007-11-01 08:46:50 -0500359 return (bmcr & PHY_BMCR_100MB) ? _100BASET : _10BASET;
wdenke3a06802004-06-06 23:13:55 +0000360
Michael Zaidman6dbca5f2010-02-28 16:28:25 +0200361miiphy_read_failed:
Larry Johnson966a80b2007-11-01 08:46:50 -0500362 printf (" read failed, assuming 10BASE-T\n");
363 return _10BASET;
wdenkc6097192002-11-03 00:24:07 +0000364}
365
wdenkc6097192002-11-03 00:24:07 +0000366/*****************************************************************************
367 *
Larry Johnson966a80b2007-11-01 08:46:50 -0500368 * Determine full/half duplex. Return half on error.
wdenkc6097192002-11-03 00:24:07 +0000369 */
Mike Frysinger5ff5fdb2010-07-27 18:35:08 -0400370int miiphy_duplex(const char *devname, unsigned char addr)
wdenkc6097192002-11-03 00:24:07 +0000371{
Larry Johnson966a80b2007-11-01 08:46:50 -0500372 u16 bmcr, anlpar;
wdenkc6097192002-11-03 00:24:07 +0000373
wdenkeec9a3d2004-03-23 23:20:24 +0000374#if defined(CONFIG_PHY_GIGE)
Larry Johnson966a80b2007-11-01 08:46:50 -0500375 u16 btsr;
376
377 /* Check for 1000BASE-X. */
378 if (miiphy_is_1000base_x (devname, addr)) {
379 /* 1000BASE-X */
380 if (miiphy_read (devname, addr, PHY_ANLPAR, &anlpar)) {
381 printf ("1000BASE-X PHY AN duplex");
382 goto miiphy_read_failed;
wdenked2ac4b2004-03-14 18:23:55 +0000383 }
384 }
Larry Johnson966a80b2007-11-01 08:46:50 -0500385 /*
386 * No 1000BASE-X, so assume 1000BASE-T/100BASE-TX/10BASE-T register set.
387 */
388 /* Check for 1000BASE-T. */
389 if (miiphy_read (devname, addr, PHY_1000BTSR, &btsr)) {
390 printf ("PHY 1000BT status");
391 goto miiphy_read_failed;
392 }
393 if (btsr != 0xFFFF) {
394 if (btsr & PHY_1000BTSR_1000FD) {
395 return FULL;
396 } else if (btsr & PHY_1000BTSR_1000HD) {
397 return HALF;
398 }
399 }
wdenkeec9a3d2004-03-23 23:20:24 +0000400#endif /* CONFIG_PHY_GIGE */
wdenked2ac4b2004-03-14 18:23:55 +0000401
wdenke3a06802004-06-06 23:13:55 +0000402 /* Check Basic Management Control Register first. */
Larry Johnson966a80b2007-11-01 08:46:50 -0500403 if (miiphy_read (devname, addr, PHY_BMCR, &bmcr)) {
404 puts ("PHY duplex");
405 goto miiphy_read_failed;
wdenkc6097192002-11-03 00:24:07 +0000406 }
wdenke3a06802004-06-06 23:13:55 +0000407 /* Check if auto-negotiation is on. */
Larry Johnson966a80b2007-11-01 08:46:50 -0500408 if (bmcr & PHY_BMCR_AUTON) {
wdenke3a06802004-06-06 23:13:55 +0000409 /* Get auto-negotiation results. */
Larry Johnson966a80b2007-11-01 08:46:50 -0500410 if (miiphy_read (devname, addr, PHY_ANLPAR, &anlpar)) {
411 puts ("PHY AN duplex");
412 goto miiphy_read_failed;
wdenke3a06802004-06-06 23:13:55 +0000413 }
Larry Johnson966a80b2007-11-01 08:46:50 -0500414 return (anlpar & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD)) ?
415 FULL : HALF;
wdenke3a06802004-06-06 23:13:55 +0000416 }
417 /* Get speed from basic control settings. */
Larry Johnson966a80b2007-11-01 08:46:50 -0500418 return (bmcr & PHY_BMCR_DPLX) ? FULL : HALF;
419
Michael Zaidman6dbca5f2010-02-28 16:28:25 +0200420miiphy_read_failed:
Larry Johnson966a80b2007-11-01 08:46:50 -0500421 printf (" read failed, assuming half duplex\n");
422 return HALF;
423}
wdenke3a06802004-06-06 23:13:55 +0000424
Larry Johnson966a80b2007-11-01 08:46:50 -0500425/*****************************************************************************
426 *
427 * Return 1 if PHY supports 1000BASE-X, 0 if PHY supports 10BASE-T/100BASE-TX/
428 * 1000BASE-T, or on error.
429 */
Mike Frysinger5ff5fdb2010-07-27 18:35:08 -0400430int miiphy_is_1000base_x(const char *devname, unsigned char addr)
Larry Johnson966a80b2007-11-01 08:46:50 -0500431{
432#if defined(CONFIG_PHY_GIGE)
433 u16 exsr;
434
435 if (miiphy_read (devname, addr, PHY_EXSR, &exsr)) {
436 printf ("PHY extended status read failed, assuming no "
437 "1000BASE-X\n");
438 return 0;
439 }
440 return 0 != (exsr & (PHY_EXSR_1000XF | PHY_EXSR_1000XH));
441#else
442 return 0;
443#endif
wdenkc6097192002-11-03 00:24:07 +0000444}
445
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200446#ifdef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
wdenk49c3f672003-10-08 22:33:00 +0000447/*****************************************************************************
448 *
449 * Determine link status
450 */
Mike Frysinger5ff5fdb2010-07-27 18:35:08 -0400451int miiphy_link(const char *devname, unsigned char addr)
wdenk49c3f672003-10-08 22:33:00 +0000452{
453 unsigned short reg;
454
wdenk145d2c12004-04-15 21:48:45 +0000455 /* dummy read; needed to latch some phys */
Larry Johnson81b974b2007-10-31 11:21:29 -0500456 (void)miiphy_read (devname, addr, PHY_BMSR, &reg);
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200457 if (miiphy_read (devname, addr, PHY_BMSR, &reg)) {
wdenk42c05472004-03-23 22:14:11 +0000458 puts ("PHY_BMSR read failed, assuming no link\n");
wdenk49c3f672003-10-08 22:33:00 +0000459 return (0);
460 }
461
462 /* Determine if a link is active */
463 if ((reg & PHY_BMSR_LS) != 0) {
464 return (1);
465 } else {
466 return (0);
467 }
468}
469#endif