blob: e282096a13460866c9f7b2054b3ce8c38de48f7f [file] [log] [blame]
wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2001
3 * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * This provides a bit-banged interface to the ethernet MII management
26 * channel.
27 */
28
29#include <common.h>
30#include <miiphy.h>
31
Marian Balakowiczaab8c492005-10-28 22:30:33 +020032#include <asm/types.h>
33#include <linux/list.h>
34#include <malloc.h>
35#include <net.h>
36
37/* local debug macro */
Marian Balakowiczaab8c492005-10-28 22:30:33 +020038#undef MII_DEBUG
39
40#undef debug
41#ifdef MII_DEBUG
42#define debug(fmt,args...) printf (fmt ,##args)
43#else
44#define debug(fmt,args...)
45#endif /* MII_DEBUG */
46
47struct mii_dev {
48 struct list_head link;
Mike Frysinger5ff5fdb2010-07-27 18:35:08 -040049 const char *name;
50 int (*read) (const char *devname, unsigned char addr,
Larry Johnson81b974b2007-10-31 11:21:29 -050051 unsigned char reg, unsigned short *value);
Mike Frysinger5ff5fdb2010-07-27 18:35:08 -040052 int (*write) (const char *devname, unsigned char addr,
Larry Johnson81b974b2007-10-31 11:21:29 -050053 unsigned char reg, unsigned short value);
Marian Balakowiczaab8c492005-10-28 22:30:33 +020054};
55
56static struct list_head mii_devs;
57static struct mii_dev *current_mii;
58
Mike Frysinger24a90082010-07-27 18:35:09 -040059/*
60 * Lookup the mii_dev struct by the registered device name.
61 */
62static struct mii_dev *miiphy_get_dev_by_name(const char *devname, int quiet)
63{
64 struct list_head *entry;
65 struct mii_dev *dev;
66
67 if (!devname) {
68 printf("NULL device name!\n");
69 return NULL;
70 }
71
72 list_for_each(entry, &mii_devs) {
73 dev = list_entry(entry, struct mii_dev, link);
74 if (strcmp(dev->name, devname) == 0)
75 return dev;
76 }
77
78 if (!quiet)
79 printf("No such device: %s\n", devname);
80 return NULL;
81}
82
Marian Balakowiczaab8c492005-10-28 22:30:33 +020083/*****************************************************************************
84 *
Marian Balakowiczcbdd1c82005-11-30 18:06:04 +010085 * Initialize global data. Need to be called before any other miiphy routine.
86 */
Mike Frysinger5ff5fdb2010-07-27 18:35:08 -040087void miiphy_init(void)
Marian Balakowiczcbdd1c82005-11-30 18:06:04 +010088{
Larry Johnson81b974b2007-10-31 11:21:29 -050089 INIT_LIST_HEAD (&mii_devs);
90 current_mii = NULL;
Marian Balakowiczcbdd1c82005-11-30 18:06:04 +010091}
92
93/*****************************************************************************
94 *
Marian Balakowiczaab8c492005-10-28 22:30:33 +020095 * Register read and write MII access routines for the device <name>.
96 */
Mike Frysinger5ff5fdb2010-07-27 18:35:08 -040097void miiphy_register(const char *name,
98 int (*read) (const char *devname, unsigned char addr,
Larry Johnson81b974b2007-10-31 11:21:29 -050099 unsigned char reg, unsigned short *value),
Mike Frysinger5ff5fdb2010-07-27 18:35:08 -0400100 int (*write) (const char *devname, unsigned char addr,
Larry Johnson81b974b2007-10-31 11:21:29 -0500101 unsigned char reg, unsigned short value))
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200102{
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200103 struct mii_dev *new_dev;
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200104 unsigned int name_len;
Mike Frysinger5ff5fdb2010-07-27 18:35:08 -0400105 char *new_name;
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200106
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200107 /* check if we have unique name */
Mike Frysinger24a90082010-07-27 18:35:09 -0400108 new_dev = miiphy_get_dev_by_name(name, 1);
109 if (new_dev) {
110 printf("miiphy_register: non unique device name '%s'\n", name);
111 return;
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200112 }
113
114 /* allocate memory */
Larry Johnson81b974b2007-10-31 11:21:29 -0500115 name_len = strlen (name);
116 new_dev =
117 (struct mii_dev *)malloc (sizeof (struct mii_dev) + name_len + 1);
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200118
Larry Johnson81b974b2007-10-31 11:21:29 -0500119 if (new_dev == NULL) {
120 printf ("miiphy_register: cannot allocate memory for '%s'\n",
121 name);
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200122 return;
123 }
Larry Johnson81b974b2007-10-31 11:21:29 -0500124 memset (new_dev, 0, sizeof (struct mii_dev) + name_len);
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200125
126 /* initalize mii_dev struct fields */
Larry Johnson81b974b2007-10-31 11:21:29 -0500127 INIT_LIST_HEAD (&new_dev->link);
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200128 new_dev->read = read;
129 new_dev->write = write;
Mike Frysinger5ff5fdb2010-07-27 18:35:08 -0400130 new_dev->name = new_name = (char *)(new_dev + 1);
131 strncpy (new_name, name, name_len);
132 new_name[name_len] = '\0';
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200133
Larry Johnson81b974b2007-10-31 11:21:29 -0500134 debug ("miiphy_register: added '%s', read=0x%08lx, write=0x%08lx\n",
135 new_dev->name, new_dev->read, new_dev->write);
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200136
137 /* add it to the list */
Larry Johnson81b974b2007-10-31 11:21:29 -0500138 list_add_tail (&new_dev->link, &mii_devs);
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200139
140 if (!current_mii)
141 current_mii = new_dev;
142}
143
Mike Frysinger5ff5fdb2010-07-27 18:35:08 -0400144int miiphy_set_current_dev(const char *devname)
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200145{
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200146 struct mii_dev *dev;
147
Mike Frysinger24a90082010-07-27 18:35:09 -0400148 dev = miiphy_get_dev_by_name(devname, 0);
149 if (dev) {
150 current_mii = dev;
151 return 0;
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200152 }
153
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200154 return 1;
155}
156
Mike Frysinger5ff5fdb2010-07-27 18:35:08 -0400157const char *miiphy_get_current_dev(void)
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200158{
159 if (current_mii)
160 return current_mii->name;
161
162 return NULL;
163}
164
Mike Frysingerbd17e7a2010-07-27 18:35:10 -0400165static struct mii_dev *miiphy_get_active_dev(const char *devname)
166{
167 /* If the current mii is the one we want, return it */
168 if (current_mii)
169 if (strcmp(current_mii->name, devname) == 0)
170 return current_mii;
171
172 /* Otherwise, set the active one to the one we want */
173 if (miiphy_set_current_dev(devname))
174 return NULL;
175 else
176 return current_mii;
177}
178
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200179/*****************************************************************************
180 *
181 * Read to variable <value> from the PHY attached to device <devname>,
182 * use PHY address <addr> and register <reg>.
183 *
184 * Returns:
185 * 0 on success
186 */
Mike Frysinger5ff5fdb2010-07-27 18:35:08 -0400187int miiphy_read(const char *devname, unsigned char addr, unsigned char reg,
Larry Johnson81b974b2007-10-31 11:21:29 -0500188 unsigned short *value)
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200189{
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200190 struct mii_dev *dev;
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200191
Mike Frysingerbd17e7a2010-07-27 18:35:10 -0400192 dev = miiphy_get_active_dev(devname);
Mike Frysinger24a90082010-07-27 18:35:09 -0400193 if (dev)
194 return dev->read(devname, addr, reg, value);
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200195
Mike Frysinger24a90082010-07-27 18:35:09 -0400196 return 1;
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200197}
198
199/*****************************************************************************
200 *
201 * Write <value> to the PHY attached to device <devname>,
202 * use PHY address <addr> and register <reg>.
203 *
204 * Returns:
205 * 0 on success
206 */
Mike Frysinger5ff5fdb2010-07-27 18:35:08 -0400207int miiphy_write(const char *devname, unsigned char addr, unsigned char reg,
Larry Johnson81b974b2007-10-31 11:21:29 -0500208 unsigned short value)
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200209{
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200210 struct mii_dev *dev;
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200211
Mike Frysingerbd17e7a2010-07-27 18:35:10 -0400212 dev = miiphy_get_active_dev(devname);
Mike Frysinger24a90082010-07-27 18:35:09 -0400213 if (dev)
214 return dev->write(devname, addr, reg, value);
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200215
Mike Frysinger24a90082010-07-27 18:35:09 -0400216 return 1;
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200217}
218
219/*****************************************************************************
220 *
221 * Print out list of registered MII capable devices.
222 */
Larry Johnson81b974b2007-10-31 11:21:29 -0500223void miiphy_listdev (void)
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200224{
225 struct list_head *entry;
226 struct mii_dev *dev;
227
Larry Johnson81b974b2007-10-31 11:21:29 -0500228 puts ("MII devices: ");
229 list_for_each (entry, &mii_devs) {
230 dev = list_entry (entry, struct mii_dev, link);
231 printf ("'%s' ", dev->name);
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200232 }
Larry Johnson81b974b2007-10-31 11:21:29 -0500233 puts ("\n");
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200234
235 if (current_mii)
Larry Johnson81b974b2007-10-31 11:21:29 -0500236 printf ("Current device: '%s'\n", current_mii->name);
Marian Balakowiczaab8c492005-10-28 22:30:33 +0200237}
238
wdenkc6097192002-11-03 00:24:07 +0000239/*****************************************************************************
240 *
241 * Read the OUI, manufacture's model number, and revision number.
242 *
243 * OUI: 22 bits (unsigned int)
244 * Model: 6 bits (unsigned char)
245 * Revision: 4 bits (unsigned char)
246 *
247 * Returns:
248 * 0 on success
249 */
Mike Frysinger5ff5fdb2010-07-27 18:35:08 -0400250int miiphy_info(const char *devname, unsigned char addr, unsigned int *oui,
wdenkc6097192002-11-03 00:24:07 +0000251 unsigned char *model, unsigned char *rev)
252{
253 unsigned int reg = 0;
wdenkf4cec3f2003-12-06 23:20:41 +0000254 unsigned short tmp;
wdenkc6097192002-11-03 00:24:07 +0000255
Mike Frysingerd63ee712010-12-23 15:40:12 -0500256 if (miiphy_read (devname, addr, MII_PHYSID2, &tmp) != 0) {
Shinya Kuribayashi49e42af2008-01-19 10:25:59 +0900257 debug ("PHY ID register 2 read failed\n");
wdenkc6097192002-11-03 00:24:07 +0000258 return (-1);
259 }
wdenkf4cec3f2003-12-06 23:20:41 +0000260 reg = tmp;
wdenkc6097192002-11-03 00:24:07 +0000261
Mike Frysingerd63ee712010-12-23 15:40:12 -0500262 debug ("MII_PHYSID2 @ 0x%x = 0x%04x\n", addr, reg);
Shinya Kuribayashi49e42af2008-01-19 10:25:59 +0900263
wdenkc6097192002-11-03 00:24:07 +0000264 if (reg == 0xFFFF) {
265 /* No physical device present at this address */
266 return (-1);
267 }
268
Mike Frysingerd63ee712010-12-23 15:40:12 -0500269 if (miiphy_read (devname, addr, MII_PHYSID1, &tmp) != 0) {
Shinya Kuribayashi49e42af2008-01-19 10:25:59 +0900270 debug ("PHY ID register 1 read failed\n");
wdenkc6097192002-11-03 00:24:07 +0000271 return (-1);
272 }
wdenkf4cec3f2003-12-06 23:20:41 +0000273 reg |= tmp << 16;
Shinya Kuribayashi49e42af2008-01-19 10:25:59 +0900274 debug ("PHY_PHYIDR[1,2] @ 0x%x = 0x%08x\n", addr, reg);
275
Larry Johnson81b974b2007-10-31 11:21:29 -0500276 *oui = (reg >> 10);
277 *model = (unsigned char)((reg >> 4) & 0x0000003F);
278 *rev = (unsigned char)(reg & 0x0000000F);
wdenkc6097192002-11-03 00:24:07 +0000279 return (0);
280}
281
wdenkc6097192002-11-03 00:24:07 +0000282/*****************************************************************************
283 *
284 * Reset the PHY.
285 * Returns:
286 * 0 on success
287 */
Mike Frysinger5ff5fdb2010-07-27 18:35:08 -0400288int miiphy_reset(const char *devname, unsigned char addr)
wdenkc6097192002-11-03 00:24:07 +0000289{
290 unsigned short reg;
Stefan Roese2e536362010-02-02 13:43:48 +0100291 int timeout = 500;
wdenkc6097192002-11-03 00:24:07 +0000292
Mike Frysingerd63ee712010-12-23 15:40:12 -0500293 if (miiphy_read (devname, addr, MII_BMCR, &reg) != 0) {
Shinya Kuribayashi49e42af2008-01-19 10:25:59 +0900294 debug ("PHY status read failed\n");
Wolfgang Denk8ff63c22005-08-12 23:15:53 +0200295 return (-1);
296 }
Mike Frysingerd63ee712010-12-23 15:40:12 -0500297 if (miiphy_write (devname, addr, MII_BMCR, reg | BMCR_RESET) != 0) {
Shinya Kuribayashi49e42af2008-01-19 10:25:59 +0900298 debug ("PHY reset failed\n");
wdenkc6097192002-11-03 00:24:07 +0000299 return (-1);
300 }
wdenk2cefd152004-02-08 22:55:38 +0000301#ifdef CONFIG_PHY_RESET_DELAY
302 udelay (CONFIG_PHY_RESET_DELAY); /* Intel LXT971A needs this */
303#endif
wdenkc6097192002-11-03 00:24:07 +0000304 /*
305 * Poll the control register for the reset bit to go to 0 (it is
306 * auto-clearing). This should happen within 0.5 seconds per the
307 * IEEE spec.
308 */
wdenkc6097192002-11-03 00:24:07 +0000309 reg = 0x8000;
Stefan Roese2e536362010-02-02 13:43:48 +0100310 while (((reg & 0x8000) != 0) && timeout--) {
Mike Frysingerd63ee712010-12-23 15:40:12 -0500311 if (miiphy_read(devname, addr, MII_BMCR, &reg) != 0) {
Stefan Roese2e536362010-02-02 13:43:48 +0100312 debug("PHY status read failed\n");
313 return -1;
wdenkc6097192002-11-03 00:24:07 +0000314 }
Stefan Roese2e536362010-02-02 13:43:48 +0100315 udelay(1000);
wdenkc6097192002-11-03 00:24:07 +0000316 }
317 if ((reg & 0x8000) == 0) {
318 return (0);
319 } else {
wdenk42c05472004-03-23 22:14:11 +0000320 puts ("PHY reset timed out\n");
wdenkc6097192002-11-03 00:24:07 +0000321 return (-1);
322 }
323 return (0);
324}
325
wdenkc6097192002-11-03 00:24:07 +0000326/*****************************************************************************
327 *
Larry Johnson966a80b2007-11-01 08:46:50 -0500328 * Determine the ethernet speed (10/100/1000). Return 10 on error.
wdenkc6097192002-11-03 00:24:07 +0000329 */
Mike Frysinger5ff5fdb2010-07-27 18:35:08 -0400330int miiphy_speed(const char *devname, unsigned char addr)
wdenkc6097192002-11-03 00:24:07 +0000331{
Larry Johnson966a80b2007-11-01 08:46:50 -0500332 u16 bmcr, anlpar;
wdenkc6097192002-11-03 00:24:07 +0000333
wdenkeec9a3d2004-03-23 23:20:24 +0000334#if defined(CONFIG_PHY_GIGE)
Larry Johnson966a80b2007-11-01 08:46:50 -0500335 u16 btsr;
336
337 /*
338 * Check for 1000BASE-X. If it is supported, then assume that the speed
339 * is 1000.
340 */
341 if (miiphy_is_1000base_x (devname, addr)) {
342 return _1000BASET;
343 }
344 /*
345 * No 1000BASE-X, so assume 1000BASE-T/100BASE-TX/10BASE-T register set.
346 */
347 /* Check for 1000BASE-T. */
Mike Frysingerd63ee712010-12-23 15:40:12 -0500348 if (miiphy_read (devname, addr, MII_STAT1000, &btsr)) {
Larry Johnson966a80b2007-11-01 08:46:50 -0500349 printf ("PHY 1000BT status");
350 goto miiphy_read_failed;
351 }
352 if (btsr != 0xFFFF &&
353 (btsr & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD))) {
354 return _1000BASET;
wdenked2ac4b2004-03-14 18:23:55 +0000355 }
wdenkeec9a3d2004-03-23 23:20:24 +0000356#endif /* CONFIG_PHY_GIGE */
wdenked2ac4b2004-03-14 18:23:55 +0000357
wdenke3a06802004-06-06 23:13:55 +0000358 /* Check Basic Management Control Register first. */
Mike Frysingerd63ee712010-12-23 15:40:12 -0500359 if (miiphy_read (devname, addr, MII_BMCR, &bmcr)) {
Larry Johnson966a80b2007-11-01 08:46:50 -0500360 printf ("PHY speed");
361 goto miiphy_read_failed;
wdenkc6097192002-11-03 00:24:07 +0000362 }
wdenke3a06802004-06-06 23:13:55 +0000363 /* Check if auto-negotiation is on. */
Mike Frysingerd63ee712010-12-23 15:40:12 -0500364 if (bmcr & BMCR_ANENABLE) {
wdenke3a06802004-06-06 23:13:55 +0000365 /* Get auto-negotiation results. */
Mike Frysingerd63ee712010-12-23 15:40:12 -0500366 if (miiphy_read (devname, addr, MII_LPA, &anlpar)) {
Larry Johnson966a80b2007-11-01 08:46:50 -0500367 printf ("PHY AN speed");
368 goto miiphy_read_failed;
wdenke3a06802004-06-06 23:13:55 +0000369 }
Mike Frysingerd63ee712010-12-23 15:40:12 -0500370 return (anlpar & LPA_100) ? _100BASET : _10BASET;
wdenke3a06802004-06-06 23:13:55 +0000371 }
372 /* Get speed from basic control settings. */
Mike Frysingerd63ee712010-12-23 15:40:12 -0500373 return (bmcr & BMCR_SPEED100) ? _100BASET : _10BASET;
wdenke3a06802004-06-06 23:13:55 +0000374
Michael Zaidman6dbca5f2010-02-28 16:28:25 +0200375miiphy_read_failed:
Larry Johnson966a80b2007-11-01 08:46:50 -0500376 printf (" read failed, assuming 10BASE-T\n");
377 return _10BASET;
wdenkc6097192002-11-03 00:24:07 +0000378}
379
wdenkc6097192002-11-03 00:24:07 +0000380/*****************************************************************************
381 *
Larry Johnson966a80b2007-11-01 08:46:50 -0500382 * Determine full/half duplex. Return half on error.
wdenkc6097192002-11-03 00:24:07 +0000383 */
Mike Frysinger5ff5fdb2010-07-27 18:35:08 -0400384int miiphy_duplex(const char *devname, unsigned char addr)
wdenkc6097192002-11-03 00:24:07 +0000385{
Larry Johnson966a80b2007-11-01 08:46:50 -0500386 u16 bmcr, anlpar;
wdenkc6097192002-11-03 00:24:07 +0000387
wdenkeec9a3d2004-03-23 23:20:24 +0000388#if defined(CONFIG_PHY_GIGE)
Larry Johnson966a80b2007-11-01 08:46:50 -0500389 u16 btsr;
390
391 /* Check for 1000BASE-X. */
392 if (miiphy_is_1000base_x (devname, addr)) {
393 /* 1000BASE-X */
Mike Frysingerd63ee712010-12-23 15:40:12 -0500394 if (miiphy_read (devname, addr, MII_LPA, &anlpar)) {
Larry Johnson966a80b2007-11-01 08:46:50 -0500395 printf ("1000BASE-X PHY AN duplex");
396 goto miiphy_read_failed;
wdenked2ac4b2004-03-14 18:23:55 +0000397 }
398 }
Larry Johnson966a80b2007-11-01 08:46:50 -0500399 /*
400 * No 1000BASE-X, so assume 1000BASE-T/100BASE-TX/10BASE-T register set.
401 */
402 /* Check for 1000BASE-T. */
Mike Frysingerd63ee712010-12-23 15:40:12 -0500403 if (miiphy_read (devname, addr, MII_STAT1000, &btsr)) {
Larry Johnson966a80b2007-11-01 08:46:50 -0500404 printf ("PHY 1000BT status");
405 goto miiphy_read_failed;
406 }
407 if (btsr != 0xFFFF) {
408 if (btsr & PHY_1000BTSR_1000FD) {
409 return FULL;
410 } else if (btsr & PHY_1000BTSR_1000HD) {
411 return HALF;
412 }
413 }
wdenkeec9a3d2004-03-23 23:20:24 +0000414#endif /* CONFIG_PHY_GIGE */
wdenked2ac4b2004-03-14 18:23:55 +0000415
wdenke3a06802004-06-06 23:13:55 +0000416 /* Check Basic Management Control Register first. */
Mike Frysingerd63ee712010-12-23 15:40:12 -0500417 if (miiphy_read (devname, addr, MII_BMCR, &bmcr)) {
Larry Johnson966a80b2007-11-01 08:46:50 -0500418 puts ("PHY duplex");
419 goto miiphy_read_failed;
wdenkc6097192002-11-03 00:24:07 +0000420 }
wdenke3a06802004-06-06 23:13:55 +0000421 /* Check if auto-negotiation is on. */
Mike Frysingerd63ee712010-12-23 15:40:12 -0500422 if (bmcr & BMCR_ANENABLE) {
wdenke3a06802004-06-06 23:13:55 +0000423 /* Get auto-negotiation results. */
Mike Frysingerd63ee712010-12-23 15:40:12 -0500424 if (miiphy_read (devname, addr, MII_LPA, &anlpar)) {
Larry Johnson966a80b2007-11-01 08:46:50 -0500425 puts ("PHY AN duplex");
426 goto miiphy_read_failed;
wdenke3a06802004-06-06 23:13:55 +0000427 }
Mike Frysingerd63ee712010-12-23 15:40:12 -0500428 return (anlpar & (LPA_10FULL | LPA_100FULL)) ?
Larry Johnson966a80b2007-11-01 08:46:50 -0500429 FULL : HALF;
wdenke3a06802004-06-06 23:13:55 +0000430 }
431 /* Get speed from basic control settings. */
Mike Frysingerd63ee712010-12-23 15:40:12 -0500432 return (bmcr & BMCR_FULLDPLX) ? FULL : HALF;
Larry Johnson966a80b2007-11-01 08:46:50 -0500433
Michael Zaidman6dbca5f2010-02-28 16:28:25 +0200434miiphy_read_failed:
Larry Johnson966a80b2007-11-01 08:46:50 -0500435 printf (" read failed, assuming half duplex\n");
436 return HALF;
437}
wdenke3a06802004-06-06 23:13:55 +0000438
Larry Johnson966a80b2007-11-01 08:46:50 -0500439/*****************************************************************************
440 *
441 * Return 1 if PHY supports 1000BASE-X, 0 if PHY supports 10BASE-T/100BASE-TX/
442 * 1000BASE-T, or on error.
443 */
Mike Frysinger5ff5fdb2010-07-27 18:35:08 -0400444int miiphy_is_1000base_x(const char *devname, unsigned char addr)
Larry Johnson966a80b2007-11-01 08:46:50 -0500445{
446#if defined(CONFIG_PHY_GIGE)
447 u16 exsr;
448
Mike Frysingerd63ee712010-12-23 15:40:12 -0500449 if (miiphy_read (devname, addr, MII_ESTATUS, &exsr)) {
Larry Johnson966a80b2007-11-01 08:46:50 -0500450 printf ("PHY extended status read failed, assuming no "
451 "1000BASE-X\n");
452 return 0;
453 }
Mike Frysingerd63ee712010-12-23 15:40:12 -0500454 return 0 != (exsr & (ESTATUS_1000XF | ESTATUS_1000XH));
Larry Johnson966a80b2007-11-01 08:46:50 -0500455#else
456 return 0;
457#endif
wdenkc6097192002-11-03 00:24:07 +0000458}
459
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200460#ifdef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
wdenk49c3f672003-10-08 22:33:00 +0000461/*****************************************************************************
462 *
463 * Determine link status
464 */
Mike Frysinger5ff5fdb2010-07-27 18:35:08 -0400465int miiphy_link(const char *devname, unsigned char addr)
wdenk49c3f672003-10-08 22:33:00 +0000466{
467 unsigned short reg;
468
wdenk145d2c12004-04-15 21:48:45 +0000469 /* dummy read; needed to latch some phys */
Mike Frysingerd63ee712010-12-23 15:40:12 -0500470 (void)miiphy_read (devname, addr, MII_BMSR, &reg);
471 if (miiphy_read (devname, addr, MII_BMSR, &reg)) {
472 puts ("MII_BMSR read failed, assuming no link\n");
wdenk49c3f672003-10-08 22:33:00 +0000473 return (0);
474 }
475
476 /* Determine if a link is active */
Mike Frysingerd63ee712010-12-23 15:40:12 -0500477 if ((reg & BMSR_LSTATUS) != 0) {
wdenk49c3f672003-10-08 22:33:00 +0000478 return (1);
479 } else {
480 return (0);
481 }
482}
483#endif