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git01.mediatek.com / filogic / uboot / b94a38195dacb6382b42218cac0d3d641984b3d2 / . / drivers / ddr / fsl / Kconfig
blob: b0e6df8be4124e7f181a605adc7330ad0095321a [file] [log] [blame]
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]1config SYS_FSL_DDR
2 bool
3 help
4 Select Freescale General DDR driver, shared between most Freescale
Tom Rinie5404982021-05-14 21:34:26 -0400[diff] [blame]5 PowerPC- based SoCs (such as mpc83xx, mpc85xx and ARM- based
6 Layerscape SoCs (such as ls2080a).
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]7
8config SYS_FSL_MMDC
9 bool
10 help
11 Select Freescale Multi Mode DDR controller (MMDC).
12
Tom Rini468c2d52021-08-21 13:50:18 -0400[diff] [blame]13if SYS_FSL_DDR || SYS_FSL_MMDC
14
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]15config SYS_FSL_DDR_BE
16 bool
17 help
18 Access DDR registers in big-endian
19
20config SYS_FSL_DDR_LE
21 bool
22 help
23 Access DDR registers in little-endian
24
Rajesh Bhagatba2414f2019-02-01 05:22:01 +0000[diff] [blame]25config FSL_DDR_BIST
26 bool
27
28config FSL_DDR_INTERACTIVE
29 bool
30
31config FSL_DDR_SYNC_REFRESH
32 bool
33
34config FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
35 bool
36
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]37menu "Freescale DDR controllers"
38 depends on SYS_FSL_DDR
39
York Sunfe845072016-12-28 08:43:45 -0800[diff] [blame]40config SYS_NUM_DDR_CTLRS
York Sundcd28c02016-12-28 08:43:44 -0800[diff] [blame]41 int "Maximum DDR controllers"
42 default 3 if ARCH_LS2080A || \
43 ARCH_T4240
44 default 2 if ARCH_B4860 || \
45 ARCH_BSC9132 || \
York Sundcd28c02016-12-28 08:43:44 -0800[diff] [blame]46 ARCH_P4080 || \
York Sundcd28c02016-12-28 08:43:44 -0800[diff] [blame]47 ARCH_P5040 || \
Priyanka Jainef76b2e2018-10-29 09:17:09 +0000[diff] [blame]48 ARCH_LX2160A || \
Tom Rinia7ffa3d2021-05-23 10:58:05 -0400[diff] [blame]49 ARCH_LX2162A
York Sundcd28c02016-12-28 08:43:44 -0800[diff] [blame]50 default 1
51
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]52config SYS_FSL_DDR_VER
53 int
54 default 50 if SYS_FSL_DDR_VER_50
55 default 47 if SYS_FSL_DDR_VER_47
56 default 46 if SYS_FSL_DDR_VER_46
57 default 44 if SYS_FSL_DDR_VER_44
58
59config SYS_FSL_DDR_VER_50
60 bool
61
62config SYS_FSL_DDR_VER_47
63 bool
64
65config SYS_FSL_DDR_VER_46
66 bool
67
68config SYS_FSL_DDR_VER_44
69 bool
70
71config SYS_FSL_DDRC_GEN1
72 bool
73 help
74 Enable Freescale DDR controller.
75
76config SYS_FSL_DDRC_GEN2
77 bool
78 depends on !MPC86xx
79 help
80 Enable Freescale DDR2 controller.
81
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]82config SYS_FSL_DDRC_GEN3
83 bool
84 depends on PPC
85 help
86 Enable Freescale DDR3 controller for PowerPC SoCs.
87
88config SYS_FSL_DDRC_ARM_GEN3
89 bool
90 depends on ARM
91 help
92 Enable Freescale DDR3 controller for ARM SoCs.
93
94config SYS_FSL_DDRC_GEN4
95 bool
96 help
97 Enable Freescale DDR4 controller.
98
99config SYS_FSL_HAS_DDR4
100 bool
101
102config SYS_FSL_HAS_DDR3
103 bool
104
105config SYS_FSL_HAS_DDR2
106 bool
107
108config SYS_FSL_HAS_DDR1
109 bool
110
111choice
112 prompt "DDR technology"
113 default SYS_FSL_DDR4 if SYS_FSL_HAS_DDR4
114 default SYS_FSL_DDR3 if SYS_FSL_HAS_DDR3
115 default SYS_FSL_DDR2 if SYS_FSL_HAS_DDR2
116 default SYS_FSL_DDR1 if SYS_FSL_HAS_DDR1
117
118config SYS_FSL_DDR4
119 bool "Freescale DDR4 controller"
120 depends on SYS_FSL_HAS_DDR4
Tom Rinife2cea62021-08-21 13:50:16 -0400[diff] [blame]121 imply DDR_SPD
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]122 select SYS_FSL_DDRC_GEN4
123
124config SYS_FSL_DDR3
125 bool "Freescale DDR3 controller"
126 depends on SYS_FSL_HAS_DDR3
Tom Rinife2cea62021-08-21 13:50:16 -0400[diff] [blame]127 imply DDR_SPD
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]128 select SYS_FSL_DDRC_GEN3 if PPC
129 select SYS_FSL_DDRC_ARM_GEN3 if ARM
130
131config SYS_FSL_DDR2
132 bool "Freescale DDR2 controller"
133 depends on SYS_FSL_HAS_DDR2
Tom Rinife2cea62021-08-21 13:50:16 -0400[diff] [blame]134 imply DDR_SPD
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]135 select SYS_FSL_DDRC_GEN2 if (!MPC86xx && !SYS_FSL_DDRC_GEN3)
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]136
137config SYS_FSL_DDR1
138 bool "Freescale DDR1 controller"
139 depends on SYS_FSL_HAS_DDR1
Tom Rinife2cea62021-08-21 13:50:16 -0400[diff] [blame]140 imply DDR_SPD
York Sund297d392016-12-28 08:43:40 -0800[diff] [blame]141 select SYS_FSL_DDRC_GEN1
142
143endchoice
144
145endmenu
York Sun1dc61ca2016-12-28 08:43:41 -0800[diff] [blame]146
Tom Rini468c2d52021-08-21 13:50:18 -0400[diff] [blame]147config FSL_DMA
148 def_bool y if DDR_ECC && MPC85xx && !ECC_INIT_VIA_DDRCONTROLLER
149
150config DDR_ECC
151 bool "ECC DDR memory support"
152
153config DDR_ECC_CMD
154 bool "Access the ECC features of the memory controller"
155 depends on DDR_ECC && MPC83xx
156 default y
157
158config ECC_INIT_VIA_DDRCONTROLLER
159 bool "DDR Memory controller initializes memory."
160 help
161 Use the DDR controller to auto initialize memory. If not enabled,
162 the DMA controller is responsible for doing this.
163
164endif
165
Tom Rinif7eed202021-11-13 18:10:40 -0500[diff] [blame]166menu "PowerPC / M68K initial memory controller definitions (FLASH, SDRAM, etc)"
167 depends on MCF52x2 || MPC8xx || MPC83xx || MPC85xx
168
169config SYS_BR0_PRELIM_BOOL
170 bool "Define Bank 0"
171
172config SYS_BR0_PRELIM
173 hex "Preliminary value for BR0"
174 depends on SYS_BR0_PRELIM_BOOL
175
176config SYS_OR0_PRELIM
177 hex "Preliminary value for OR0"
178 depends on SYS_BR0_PRELIM_BOOL
179
180config SYS_BR1_PRELIM_BOOL
181 bool "Define Bank 1"
182
183config SYS_BR1_PRELIM
184 hex "Preliminary value for BR1"
185 depends on SYS_BR1_PRELIM_BOOL
186
187config SYS_OR1_PRELIM
188 hex "Preliminary value for OR1"
189 depends on SYS_BR1_PRELIM_BOOL
190
191config SYS_BR2_PRELIM_BOOL
192 bool "Define Bank 2"
193
194config SYS_BR2_PRELIM
195 hex "Preliminary value for BR2"
196 depends on SYS_BR2_PRELIM_BOOL
197
198config SYS_OR2_PRELIM
199 hex "Preliminary value for OR2"
200 depends on SYS_BR2_PRELIM_BOOL
201
202config SYS_BR3_PRELIM_BOOL
203 bool "Define Bank 3"
204
205config SYS_BR3_PRELIM
206 hex "Preliminary value for BR3"
207 depends on SYS_BR3_PRELIM_BOOL
208
209config SYS_OR3_PRELIM
210 hex "Preliminary value for OR3"
211 depends on SYS_BR3_PRELIM_BOOL
212
213config SYS_BR4_PRELIM_BOOL
214 bool "Define Bank 4"
215
216config SYS_BR4_PRELIM
217 hex "Preliminary value for BR4"
218 depends on SYS_BR4_PRELIM_BOOL
219
220config SYS_OR4_PRELIM
221 hex "Preliminary value for OR4"
222 depends on SYS_BR4_PRELIM_BOOL
223
224config SYS_BR5_PRELIM_BOOL
225 bool "Define Bank 5"
226
227config SYS_BR5_PRELIM
228 hex "Preliminary value for BR5"
229 depends on SYS_BR5_PRELIM_BOOL
230
231config SYS_OR5_PRELIM
232 hex "Preliminary value for OR5"
233 depends on SYS_BR5_PRELIM_BOOL
234
235config SYS_BR6_PRELIM_BOOL
236 bool "Define Bank 6"
237
238config SYS_BR6_PRELIM
239 hex "Preliminary value for BR6"
240 depends on SYS_BR6_PRELIM_BOOL
241
242config SYS_OR6_PRELIM
243 hex "Preliminary value for OR6"
244 depends on SYS_BR6_PRELIM_BOOL
245
246config SYS_BR7_PRELIM_BOOL
247 bool "Define Bank 7"
248
249config SYS_BR7_PRELIM
250 hex "Preliminary value for BR7"
251 depends on SYS_BR7_PRELIM_BOOL
252
253config SYS_OR7_PRELIM
254 hex "Preliminary value for OR7"
255 depends on SYS_BR7_PRELIM_BOOL
256endmenu
257
York Sun1dc61ca2016-12-28 08:43:41 -0800[diff] [blame]258config SYS_FSL_ERRATUM_A008378
259 bool
260
Joakim Tjernlund477602c2019-11-20 17:07:34 +0100[diff] [blame]261config SYS_FSL_ERRATUM_A008109
262 bool
263
York Sun1dc61ca2016-12-28 08:43:41 -0800[diff] [blame]264config SYS_FSL_ERRATUM_A008511
265 bool
266
267config SYS_FSL_ERRATUM_A009663
268 bool
269
270config SYS_FSL_ERRATUM_A009801
271 bool
272
273config SYS_FSL_ERRATUM_A009803
274 bool
275
276config SYS_FSL_ERRATUM_A009942
277 bool
278
279config SYS_FSL_ERRATUM_A010165
280 bool
York Sunbe735532016-12-28 08:43:43 -0800[diff] [blame]281
282config SYS_FSL_ERRATUM_NMG_DDR120
283 bool
284
285config SYS_FSL_ERRATUM_DDR_115
286 bool
287
288config SYS_FSL_ERRATUM_DDR111_DDR134
289 bool
290
291config SYS_FSL_ERRATUM_DDR_A003
292 bool
293
294config SYS_FSL_ERRATUM_DDR_A003474
295 bool